1278839 九、發明說明： 【發明所屬之技術領域】 一本發明係有關於一種光碟裝置，尤有關於一種使用槽溝進行 資料的記錄/播放之高密度之光碟裝置。 【先前技術】 近年來，在下世代DVD上提議HD(Hi-Definition，高清晰度） -DVD。在HD-DVD，沿襲現行之DVD之光碟構造，在確保和勵 之互換性下，實現DVD以上之更高密度化。 > ,HD —DVD之一種特徵在於採用在槽溝(groove)及平台（land) 都記錄資料之平台•槽溝記錄方式。令平台執道及槽溝軌道顫動 (蛇行），在本顫動埋入位址資訊。具體而言，使用相位調變，以4 個相位0度之波表示位元「〇」，以4個相位度之波表示位元 「1」，表達位址資訊。將同相位之波設置4個之多個係要利用多 餘性提高位址資訊之偵測精度。此外，位址資訊係將二進位資料 變換成灰碼後埋入顫動。在此，灰碼係將相鄰之二進位資料間之 碼間距離，即反相位元數設為1之碼。因而，位址「〇」以灰碼 「00000000」，位址「1」以灰碼「00000001」，位址「2」以灰碼 「00000011」，位址「3」以灰碼「00000010」，位址「4」以灰碼 ’ 「00000110」等表達。 ” 而，令槽溝顫動，埋入位址資訊，也可只在槽溝記錄或播放 資料。在此情況，因不必供給平台位址資訊，不必將位址資訊變 換成灰碼後埋入。又，也可在槽溝之位址資訊附加CRC(Cyclie Redundancy Check :循環冗數核對）用之檢查位元。在只在槽溝記 錄資料之情況，也使用相位調變，以4個相位〇度之波表示位元 「0」，以4個相位180度之波表示位元「1」，表達位址資訊。和 在槽溝及平台記錄資料之光碟之情況一樣，以4個同相之波表達^ 位元係為了使得可都用一台光碟裝置驅動兩光碟。將只在槽溝記 錄資料之光碟設為「HD DVD—R」（寫一次），將在槽溝及平^記^ 5 1278839 資料之光碟設為「HD DVD—rw」（可重寫）時，R·或rw都可驅動。 、【專利文獻1】「日經ElectronicslO月13日號」日經BP 社’ 2003年10月13日發行，pi26〜134。 【發明内容】 一 發明欲解決之問顥 於是，使用相位調變，以4個相位〇度之波表示位元「〇」， 相位180度之波表示位元「丨」，表達位址f訊，基本上依 康广數決原理可較「G」或「丨」。即，在_到相位㈣之波有 古、相位180度之波只有1個之情況，可確定這係「〇」。可是， 相，0度之祕3個，仙無法保證是否真正是「。」，希望可更 ，精度。此外，在偵湖相位Q度之波有2個、相位18〇 又之，有2個之各佔-半之情況，無法判定資料係「0」或是「j」。 "畜然’使用CRC用檢查位元進行循環冗數核對，可判定是否 但是例如在附加了 9位元之檢查位元之情況，也止 ;口 、測么生3位元以内之錯誤，無法訂正錯誤而確定正確之位 址0 /η Ρΐί，日巧目的在於提供—種光碟裝置，對於使用相位調變以4 „「°」、'1」並埋入位址資訊之光碟’令提 局位址負δίΐ之偵測（或解調）精度。 解決問題的方4 種光碟裝置，對藉著令槽_動而埋人位址資訊 f 己錄或!#放資料，其特徵為該顫動信號用N個同相 立乂 固位赠料；在該位址資訊附加既定之CRC用檢查 料定裝置，在触該_魏後制之位址資訊 二?之情況，將該顧動之同相位之波係Ν/2個之位 7」疋二貝、，日誤位兀後，置換位元資料，使得和該crc杳 位兀一致。 一 又’本發明係-種光碟裝置，對藉著令槽溝顫動而埋入位址 6 1278839 資訊之光碟之槽溝記錄或播放資料，其特徵為該顫動信號用N個 同相位之波構成^一個位元貧料，在禮位址資訊附加既定之crc用 ，查位元；具有位址決定裝置，在播放該顫動信號後得到之位址 資訊之CRC結果不一致之情況，將該顫動之同相位之波係個 以下之位元判定為讀取錯誤位元後，置換位元資料r使得和該CRC 用檢查位元一致。 / 一又，本發明係一種光碟裝置，對藉著令槽溝顫動而埋入位址 資afl之光碟之槽溝記錄或播放資料，其特徵為該顫動信號用n個 同相位之波構成一個位元資料；在該位址資訊附加既定之CRC用 位兀，具有位址決定裝置，在播放該顫動信號後得到之位址 貧訊之CRC結果不-致之情況，將該觸之同相位之波係ν/2個 之位元判定為讀取錯誤位元後，置換位元資料，使得和該用 檢查位元一致，在利用該置換也和該CRC用檢查位元不一致之 ί Hi之同相位之波係N—1個以下之位元判定為讀取錯誤 位7L後，置換位元資料，使得和該CRC用檢查位元一致。 之、古在grg結果不—致之情況，魏於顫動之同相位 ，J N/2 月/〆二1個之情況，當作在該位元發生錯誤，crc么士果 變成不-致’將該位元作㈣^果 誤。 1兀作馮錯祆位兀，猎者進行置換處理訂正錯 【實施方式】 以下，依照圖面說明本發明之實施例。 達光之整體構造圖。利用主軸馬 i 3G進行伺服控制，使得變成所要之轉 疋杜尽貫施例，例如，驅動哭 間分割成多個區，驅動成在^碟10在自内圈至外圈之 10例如係ffl) DVD-R。 麵固定之線速度(ZCLV)。光碟 7 1278839 或接受來自光碟10照射f射光之f射二極體⑽ 和光碟1〇相向的配置。言號之光偵測器⑽， 拾取頭16，用驅動器8在光碟10之徑向驅動光 一樣利關服處理哭3G驅動器20和驅動器14 光拾取頭16 ΐ ‘ L r服控制。又，利用驅動器22驅動 22，使得驅動電一動功率控制電路(APC)24控制驅動器 流，使得變成^匕^之值。職嫌_ 22之驅動電 Power ft1G之戰區域(PCA)執行麵 光碟10之PCa人H控制)所選擇之最佳記錄功率。0PC係在 測試資料，坪估的變化的記錄測試資料後，播放該 錄功率^處i 口4後，選擇可得到所要之信號品質之記 等。 t#uaai採用卢值或T值、調變度、跳動（jitter) 放功Ϊίί 1〇所記錄之資料時’自光拾取頭16之LD照射播 RF電^來^光^^將^反射光轉換為電氣信號後輸出。供給 產生焦點誤差信差 自播放信號 Μ α愿3追恥差#唬後，供給伺服處理器30。伺服 才Hfw依Γ、這些誤差信號對光拾取頭16進行飼服控制，將光 才口取頭16保持在對焦狀態或對執狀態。 頭16對光碟ig之槽溝記錄/播放。在光碟ig形成螺 万疋狀之槽溝。又，RF電路26供給位址解碼電路28播放信號所含 之位址信號。位址解碼電路28自位址信號將光碟1〇之位址資訊 解調後，供給伺服處理器30或系統控制器32。以顫動信號將位址 及執道位址。位址資訊經相位調變後，用4個相位〇度之波表示 位元值「0」，用4個相位180度之波表示位元值「丨」。這些4個 同相位之波構成多餘系。 一 RF電路26供給二值化電路34播放用RF信號。二值化電路 34將播放信號二值化後，將所得到之信號供給編碼/解碼電路36。 8 1278839 • 在編碼/解碼電路36，將二值化信號解調及訂正錯誤後得到播放資 料，經由界面I/F40向個人電腦等主裝置輸出該播放資料。此外、， 在向主裝置輪出播放資料時’編碼/解碼電路將播放眘 •於緩衝記憶體38後輸出。 、”曰 • 乂在光碟10記錄資料時，經由界面1/刚供給編碼/解碼電路 36來自主裝置之應記錄之資料。編碼/解碼電路36將應記錄之資 ΐ儲存於緩衝記憶體38後，將該應記錄之資料編碼後，作為調變 貧料(Ε^Μ 調變（Eight to Twelve Modulation))供給寫策略電二 • ，。寫策略電路42按照既定之記錄策略將調變資料轉換為多脈衝 •(脈衝串）後，作為記錄資料供給驅動器22。記錄策略係例如由在 誠 多脈衝之前頭脈衝之脈寬或後續脈衝之脈寬、脈衝占空比所構 ^。因記錄策略影響記錄品質，一般固定為某最佳策略。在〇pc 時一併設定記錄策略也可。自光拾取頭16之LD照射依據記錄資 料進行功率調變後之雷射光，在光碟1〇記錄資料。記錄資料後： 光拾取頭16照射播放功率之雷射光，播放該記錄資料，供給卯 電路26。RF電路26供給二值化電路34播放信號，供給^缚 碼電路36>二值化後之資料。編碼/解碼電路36將調變資料解碼 後，和在緩衝a己憶體38所儲存之記錄資料比對。供給系統控制器 32查證結果。系統控制器32按照查證結果決定繼續記錄資 & 暴行交替處理0 、〆 • 在這種構造，在槽溝記錄/播放資料，追蹤槽溝軌道，用位址 解碼電路28偵測位址後供給系統控制器32之情況，在正常之續 取時可連續偵測到4個同相位之波，此時按照該相位可確定位^ 值為「0」或「1」。可是，在只偵測到3個同相位之波時，或只偵 測到2個同相位之波時，可能發生位址資訊之讀取錯誤。在前者 之情況（同相位之波為3個），也可依據多數決之原理按照該相位 確定位元值，但是其可靠性相對的降低。至於後者之情況（同相位 之波為2個）’無法依據多數決之原理確定位元值。在任一種情況， 都讀成0或1之其中之一後，判定和CRC用之檢查位元是否一致， 9 1278839 就是錯誤。CRC係周知之技術，將檢 一對象之貝枓*作一進位貝料，以產生多項式之計算式處理 生固疋之位70數之檢查用位元後，附加於檢查 =田藉著播放檢查對象之資料，用產生多項式處理^判$1278839 IX. Description of the Invention: [Technical Field] The present invention relates to an optical disk device, and more particularly to a high-density optical disk device for recording/playing data using a groove. [Prior Art] In recent years, HD (Hi-Definition, High Definition)-DVD has been proposed on the next generation DVD. In the HD-DVD, the optical disc structure of the current DVD is followed, and the density of the DVD or higher is achieved with the compatibility of the excitation and the excitation. > , HD - A feature of DVD is the use of a platform/groove recording method for recording data in both grooves and land. Let the platform obey and the groove track vibrate (snake), and embed the address information in this vibration. Specifically, with phase modulation, the bit "〇" is represented by four phases of 0 degrees, and the bit "1" is represented by waves of four phase degrees to express the address information. Setting multiple waves of the same phase to multiple systems requires the use of redundancy to improve the detection accuracy of the address information. In addition, the address information is converted into gray code after the binary data is converted into tremor. Here, the gray code sets the code-to-code distance between adjacent binary data, that is, the number of inverse phase elements to one. Therefore, the address "〇" is a gray code "00000000", the address "1" is a gray code "00000001", the address "2" is a gray code "00000011", and the address "3" is a gray code "00000010". The address "4" is expressed by gray code ' "00000110" or the like. However, if the groove is vibrated and the address information is buried, the data can be recorded or played only in the slot. In this case, since it is not necessary to supply the platform address information, it is not necessary to convert the address information into a gray code and embed it. In addition, it is also possible to add a check bit for CRC (Cyclie Redundancy Check) to the address information of the groove. In the case of recording data only in the groove, phase modulation is also used, with four phases 〇 The wave of degree represents the bit "0", and the bit "1" is represented by the wave of four phases of 180 degrees, and the address information is expressed. As in the case of the disc and the disc on which the data is recorded, the four in-phase waves are expressed in order to enable the two discs to be driven by one optical disc device. Set the disc that only records data in the slot to "HD DVD-R" (write once), and set the disc in the slot and ping ^ 5 1278839 data to "HD DVD-rw" (rewritable). , R · or rw can be driven. [Patent Document 1] "Nikkei Electronics, October 13th", Nikkei BP, was released on October 13, 2003, pi26~134. SUMMARY OF THE INVENTION In order to solve the problem, a phase modulation is used to represent a bit "〇" with a wave of four phase twists, and a wave of a phase of 180 degrees represents a bit "丨", and the address is f Basically, the principle of "K" or "丨" can be compared. That is, in the case where the wave of _ to phase (4) has an ancient wave with only one phase of 180 degrees, it can be determined that this is "〇". However, the phase, 3 secrets of 0 degrees, can not guarantee whether it is really ".", hope can be more accurate. In addition, there are two waves in the phase of the lake in the lake, and the phase is 18 〇. There are two cases of each of the two, and it is impossible to determine whether the data is "0" or "j". "Yaoran' uses the CRC check bit to perform the loop redundancy check, and can determine whether it is, for example, the case where the check bit of 9 bits is added, and the error of the mouth or the test is less than 3 bits. Unable to correct the error and determine the correct address 0 /η Ρΐί, the purpose of the day is to provide a kind of optical disc device, for the use of phase modulation with 4 „“°”, '1' and embed the address information of the disc' The location address is negative δίΐ detection (or demodulation) accuracy. The four types of optical disc devices that solve the problem are buried in the address information, or recorded in the address information, which is characterized by the fact that the dither signal is fixed by N in-phase solids; The address information is attached to the predetermined CRC inspection device, and in the case of touching the address information of the wei post-production system, the wave of the phase of the same phase is /2 digits. After the day is misplaced, the bit data is replaced so that it coincides with the crc unit. In addition, the invention relates to a disc device for recording or playing back a groove of an optical disc embedded with an address of 6 1278839 by means of a groove flutter, characterized in that the dither signal is composed of N waves of the same phase. ^ One bit of poor material, the location information is attached to the established crc, and the bit is checked; and the address determining device has an inconsistent CRC result of the address information obtained after playing the jitter signal, and the jitter is After the bit phase of the same phase is determined to be the read error bit, the replacement bit data r is made to coincide with the check bit of the CRC. / In addition, the present invention is an optical disc device for recording or playing back data in a groove of a disc which is buried in a position by a flutter, and is characterized in that the dither signal is composed of n waves of the same phase. Bit data; in the address information, a predetermined CRC bit is added, and an address determining device is used. After the jitter signal is played, the CRC result of the address poor message is not obtained, and the touch is in phase. After the bit system ν/2 bits are determined to read the error bit, the bit data is replaced so as to be consistent with the check bit, and the replacement is also inconsistent with the check bit of the CRC. When the bit phase N-1 or less bits are determined to be the read error bit 7L, the bit data is replaced so as to coincide with the CRC check bit. The result of the ancient grg is not - the situation, the same phase of Wei tremble, JN / 2 / 〆 2, as the error occurs in the bit, crc sorrow becomes not - "will The bit is (4)^ fruit error. 1 兀 冯 冯 祆 兀 兀 兀 兀 兀 兀 兀 兀 兀 进行 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎The overall structure of Daguang. The servo control is performed by the spindle horse i 3G, so that the desired transition is completed. For example, the driving crying is divided into a plurality of zones, and the driving is 10 in the inner ring to the outer ring, for example, ffl. ) DVD-R. Fixed line speed (ZCLV). Disc 7 1278839 or a configuration in which the f-diode (10) from the optical disc 10 is irradiated with light and the disc 1 。. The light detector (10) of the mark, the pickup head 16, drives the light in the radial direction of the optical disk 10 by the driver 8 as well as the crying 3G driver 20 and the driver 14 optical pickup 16 ‘ LL service control. Further, the drive 22 is driven 22 so that the drive electric power control circuit (APC) 24 controls the drive flow so as to become a value. Driver's _ 22 drive power Power ft1G battle area (PCA) execution surface CD 10 PCa person H control) The best recording power selected. 0PC is used to record the test data after the test data and the change of the ping estimate. After playing the recorded power ^ at port 4, select the desired signal quality and so on. t#uaai uses Lu value or T value, modulation degree, jitter (jitter), and 放 ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί Output after conversion to electrical signal. The supply produces a focus error spread. The self-playback signal Μ α wishes 3 chasing the difference #唬 is supplied to the servo processor 30. The servo Hfw relies on these error signals to perform the feeding control of the optical pickup 16 to maintain the optical pickup 16 in the in-focus state or in the opposite state. The first 16 records/plays the groove of the optical disc ig. In the optical disc ig, a spiral groove is formed. Further, the RF circuit 26 supplies the address decoding circuit 28 to play the address signal included in the signal. The address decoding circuit 28 demodulates the address information of the optical disk 1 from the address signal, and supplies it to the servo processor 30 or the system controller 32. The address and the address of the address will be transmitted by the dither signal. After the address information is phase-modulated, the bit value "0" is represented by the wave of four phase twists, and the bit value "丨" is represented by the wave of four phases of 180 degrees. These four waves of the same phase constitute the redundant system. An RF circuit 26 supplies the binarization circuit 34 to play the RF signal. The binarization circuit 34 binarizes the playback signal, and supplies the obtained signal to the encoding/decoding circuit 36. 8 1278839 • In the encoding/decoding circuit 36, the binarized signal is demodulated and corrected, and the broadcast data is obtained, and the broadcast data is output to the host device such as a personal computer via the interface I/F40. In addition, the encoding/decoding circuit will be played carefully after buffering the memory 38 when the playback material is rotated to the main device. When the data is recorded on the optical disc 10, the information to be recorded from the main apparatus is supplied to the encoding/decoding circuit 36 via the interface 1/. The encoding/decoding circuit 36 stores the information to be recorded in the buffer memory 38. After encoding the information to be recorded, it is supplied to the write strategy as a modified tough material (Eight to Twelve Modulation). The write strategy circuit 42 converts the modulated data according to the established recording strategy. After the multi-pulse (burst), it is supplied to the driver 22 as a recording material. The recording strategy is composed, for example, by the pulse width of the head pulse or the pulse width of the subsequent pulse before the Chengdu pulse, and the pulse duty ratio. The quality of the recording is generally fixed to a certain optimal strategy. The recording strategy can also be set at the time of 〇pc. The LD illumination from the optical pickup head 16 is based on the recorded data, and the laser light is modulated after the power is modulated. After recording the data: the optical pickup 16 irradiates the laser light of the playback power, plays the recorded data, and supplies it to the buffer circuit 26. The RF circuit 26 supplies the binary circuit 34 to play the signal, and supplies the code circuit 36> After binarization, the encoding/decoding circuit 36 decodes the modulated data and compares it with the recorded data stored in the buffer a. The system controller 32 verifies the result. The system controller 32 verifies the data. As a result, it is decided to continue the recording and the atrocities are alternately processed. 0, 〆 In this configuration, the data is recorded/played in the groove, the groove track is tracked, and the address is decoded by the address decoding circuit 28 to supply the system controller 32. In the normal renewal, four waves of the same phase can be continuously detected. At this time, according to the phase, the value of the bit ^ can be determined as "0" or "1". However, when only three waves of the same phase are detected, or only two waves of the same phase are detected, the reading of the address information may occur. In the former case (three waves in the same phase), the bit value can also be determined according to the phase according to the majority principle, but the reliability is relatively lowered. As for the latter case (two waves of the same phase), the bit value cannot be determined according to the principle of majority decision. In either case, after reading one of 0 or 1, the decision is the same as the check bit used by the CRC. 9 1278839 is an error. CRC is a well-known technology that will test the object of a beibei* as a carry-in material, to generate a polynomial calculation method to process 70-bit inspection bits, and attach it to the inspection = field by play check Object data, using polynomial processing ^ judgment $
元是否一致，判定有無錯誤。同位位元係1位元之CRC 用之^查位元’可_ 1位元之錯誤。設CR S二位元以内之錯誤，但是因在哪-錄元二 = 正錯誤。尤其，在用12位元構成位址資‘ J#况技咢适些12位兀之全部之可能之組合係不切實 _用在本實施例，在所棘之位址資訊之CRC之結果和CRC 用之k查位致而欺發生了錯誤之情況 貧訊之哪-個位元位置發生了錯誤而、止 nf ^4，紐纽誤之位元位ί 疋個之凊況判疋正確的讀取；而在同相位之读不0 4 判定在該位元位置發生了錯誤。 ’疋個之情況 數電解碼€路28之計數同相位之波之個數之計 造上具有將自RF信號所抽出之顫動信號二值化^ 1數1路在構 互斥性邏輯和(E0R)閘以及計數^c。—彳化器28a、 E〇R ,1 28Ϊ^- 〇 輯和後向計數器28C [出二基ί時鐘信號之互斥性邏 f號和基準時鐘信號都是ΐ二值化顧 動信號和基準時鐘信號之一方為Η值化顫 因此，在圖3之期間Ta(位址資 元'、^出信號變成 取顫動信號時，在二值化顫動 1，兀貝枓長度）正常的讀 化摘仏虎存在4剌之脈衝，因總是變 10Whether the yuan is consistent and whether there is an error. The parity of the CRC of the 1-bit element of the parity bit is _1 bit error. Set the error within the CR S two-bit, but because of where-recorded two = positive error. In particular, it is not practical to use the 12-bit component to form the location of the location. It is not practical to use the CRC result and CRC in the address information of the spine. Use k to check the position and deceive the wrong situation. Which of the poor information - the position of a bit has occurred, and the nf ^4, the position of the New Zealand error ί 疋 凊 疋 疋 疋 疋 疋 correct reading Taken; while reading in the same phase is not 0 4 It is determined that an error has occurred at the bit position. 'The number of cases of electric decoding, the number of waves of the same phase of the road 28 is calculated to have the dithering of the dither signal extracted from the RF signal ^ 1 number 1 way in the mutual exclusion logic sum ( E0R) gate and count ^c. - 彳化器28a, E〇R, 1 28Ϊ^- 〇 and back counter 28C [External 逻 时钟 时钟 时钟 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和One of the clock signals is devaluation. Therefore, during the period of Fig. 3, the normal reading of the Ta (the address of the element ', the signal of the signal becomes a dithering signal, the binarization of the vibrating 1, the length of the mussels) There is a pulse of 4剌 in the tiger, because it always changes to 10
1278839 =22=::。，信號總是變成l，在計數請 在4個也正I f讀取顫動信號時，在二值化顫動信號存 總是變成H疋，*基準時鐘信號同—值，輸出信號 位之波之個貞測到脈衝數為0個，即180度之同相 生ii 。可是:在圖3之期間Tc在顫動信號讀取發 在二值化法偵測第2個之波iig之情況’變成 :值r里ίίΐ只含3個h之脈衝，因在基準時鐘信號和本部 9»扁/,、，在輸出信號變成包含1個脈衝200。因此，在計數哭 以1所1個’即G度之同相位之波之個數為3個二 ^不3十數同相位之波之個數後，供給系統控制器32。 計數哭本實侧之紐㈣解碱職糊。首先，用 31甘it Λ位0度之波之個數C(S101)。接著，系統控制器 係4個之情況，可蚊其位元值係「G」，而在波之個數 ’「、 ^即180度之波之個數係4個）之情況，可決定其位元值係 1」，未發生讀取錯誤。1278839 = 22 =::. , the signal always becomes l. When counting the dither signal in 4 counts, the binarized jitter signal always becomes H疋, * the reference clock signal has the same value, and the output signal bit wave The number of pulses measured is 0, that is, 180 degrees of in-phase ii. However, during the period of Figure 3, Tc is in the case where the dithering signal is read by the binarization method to detect the second wave iig' becomes: the value r ίίΐ contains only 3 h pulses, because of the reference clock signal and The headquarters 9» flat /,,, in the output signal becomes a pulse containing 200. Therefore, the system controller 32 is supplied to the system controller 32 after counting the number of waves in the same phase as one of the ones, i.e., the G-degrees, in the number of three, two, or three, ten-phase waves. Count the crying of the real side of the New Zealand (four) to dissolve the alkali paste. First, use 31 Ganit to clamp the number of waves of 0 degrees (S101). Then, in the case of four system controllers, the bit value of the mosquito can be "G", and the number of waves can be determined by the number of waves "", that is, the number of waves of 180 degrees is four). The bit value is 1" and no read error has occurred.
样、、蓋不是C=0或4之情況，即，在W、2或3之情況，T 二f ?在雜几設定錯誤旗標(S1G3)。將設定了錯誤旗標之位元 特疋為應訂正錯誤之位元。 级垂t圖5表不在系統控制器32之CRC之流程圖。輸入在位址解 ^電路28所播放之位址資訊(S201)。此時，因也平行的執行圖4 =不之處理，也和位址資訊一起輸入錯誤旗標之有無。例如，在 U位7^之位址資訊之情況，位址資訊係「〇〇〇〇〇〇〇〇〇111」，在第2 位元和第3位元設定了錯誤旗標等。接著，系統控制器32將所入 之位址資訊當作二進位資料，使用產生多項式處理，處生值 後’判定和預先附加之CRC用之檢查位元是否一致(S2〇2)。在CRC ，OK，即和CRC用之檢查位元一致之情況，表示正常的讀取，確 疋位址。而，在CRC係NG，即和CRC用之檢查位元不一致之情況， 11 1278839 制H 32藉著職依據錯縣標特定錄元健，訂正錯誤 在圖6表示在圖5之S2〇3之詳細 制器32判定設定了錯誤旗標百先’系統控 (S301)。在錯誤位元係只有—個公（錯J =)是否是多個 置換每些錯块位元後，判定和CRC $况 (=)==㈤F對 再進行。因此，在錯誤位元為2 ^情亥f ’不必 核對就夠了。-樣的，在錯誤位元為3位1之::合 ‘環=合=環環冗 :組合㈣正叙她f訊’完成錯么合在之^況在 ’在置換錯餘元時，不是對於錯齡元之全呷之可 前進二 ==ϊ之Ϊ提下位址成為自已確定之正前之位址 咖，查位^不=之自情位址之組合時和 波之個數不是0個或4個之位元發生錯誤，特定錯誤位元^立置， 12 1278839 不是4個之位元，但是在CRC之絲係不一致 =;同相位之波之個數，置換同相位之波之個數= 』:ΐί實f tj，將同相位之波之個數不是4個之位元當作 ▲ Γϊίΐ 將同相位之波之個數是2個之位元當作^ 換也可。即，在同相位之波之個數是1個或3個之情況 依據夕數決之顧決定位元值，但是因這些具有某種程度之 性^作為不是錯誤位元處理。只將_位之波之個數是2個^ 位7〇虽作錯雜（置換，也在循觀數核對—致之組合不 情況，接著使職同她之波之健是丨_ 3個德元也 錯誤位元而置換之處理演算法也可。 在圖7表示這種纽之處職簡。首先，滅輸入位址資 汛後’祕控制器32判定位址資訊之CRC值（在產生多項式處理 之值）和CRC用檢查位元是否一致(S4〇2)。在CRC不一致而判定恥 之情況，置換同相位之波之個數c為2個之位元後判定CRC是否 -致(S403、S404)。在〇2之位元存在有多個之情況，對於全部 之"L能之f合置換後判定其CRC是否一致。如上述所示，首先(優 先）旨δ式麦成自正剞之位址只前進一個位址之組合，判定其⑶匸是 否一致，可。在CRC —致之情況，在該組合確定位址資訊(S4〇8)。 而，在嘗試02之位元之全部之組合CRC都不一致之情況，接著 ，（M、2、3之位元當作錯誤位元置換(S4〇5)。然後，再判定 疋否一致（S406)。在CRC —致之情況，在該組合確定位址資訊 (S408)。在嘗試全部之組合都不一致之情況，最後判定錯誤 (S407)。於是，藉著首先只對於c=2之位元置換，然後，置換C=1、 2、3之位元，可期待錯誤訂正時間縮短。 13 !278839 數為2個(相H t 了⑽’在位元資料相位G度之波之個 之ϋΐΐ ί度之波之健為2個)之位元有4個(超出CRC =*1性咖上之纽，_法 = 【圖式簡單說明】 圖1為實施例之整體構造圖。 圖2為實施例之位址解碼電路之構造圖。 圖3 (a)〜（d)為顫動信號之時序圖。 圖4為實施例之錯誤位元特定處理流程圖。 圖5為實施例之錯誤訂正處理流程圖。 圖6為錯誤訂正之詳細處理流程圖。 圖7為錯誤訂正之別的處理流程圖。 【主要元件符號說明】 1〇光碟 12主軸馬達(SPM) 14驅動器 16光拾取頭 18螺桿馬達 20驅動器 22驅動器 24 APC(自動功率控制電路） 26 RF(射頻）電路 28位址解碼電路 28a二值化器 28b EOR 閘 28c比率計數器 30伺服處理器 1278839 32系統控制器 34二值化電路 36編碼/解碼電路 38緩衝記憶體 40界面I/F 42寫策略電路The case, the cover is not the case of C=0 or 4, that is, in the case of W, 2 or 3, T 2 f is set in the error flag (S1G3). The bit with the error flag set is specified as the bit that should correct the error. The graph of the CRC is not in the flow chart of the system controller 32. The address information played by the address decoding circuit 28 is input (S201). At this time, because of the parallel execution of Fig. 4 = no processing, the error flag is also input together with the address information. For example, in the case of the address information of the U bit 7^, the address information is "〇〇〇〇〇〇〇〇〇111", and an error flag is set in the second bit and the third bit. Next, the system controller 32 treats the entered address information as binary data, using the generator polynomial processing, and determines whether the check bits for the CRC and the pre-attached CRC are identical (S2〇2). In the case of CRC, OK, that is, the check bit used by the CRC, it indicates normal reading and confirming the address. However, in the case of the CRC system NG, that is, the check bit used for the CRC is inconsistent, the H 32 of the 1 278 839 system is based on the wrong record of the county standard, and the correction error is shown in Fig. 6 in S2〇3 of Fig. 5. The detail controller 32 determines that the error flag is set to be 'system control' (S301). In the error bit system, only if the public (wrong J =) is a plurality of replacements for each of the wrong block bits, the decision and the CRC $ condition (=) == (five) F pairs are performed again. Therefore, it is sufficient that the error bit is 2^情海f' without checking. - Like, in the wrong bit is 3 digits 1:: combined 'ring = combined = ring ring redundancy: combination (four) is positive about her f message 'finish the wrong thing in the case of 'in the replacement wrong element, It is not for the whole age of the wrong age. It is possible to advance 2 == ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ , , , , , 0 or 4 bits have an error, the specific error bit is set to stand, 12 1278839 is not 4 bits, but the CRC is inconsistent =; the number of waves in the same phase, replacing the wave in the same phase The number = 』: ΐί real f tj, the number of waves of the same phase is not 4 bits as ▲ Γϊίΐ The number of waves in the same phase is 2 bits as ^ can also be changed. That is, in the case where the number of waves in the same phase is one or three, the bit value is determined based on the number of eves, but these have a certain degree of reliability as the processing of the error bit. Only the number of waves of _ bit is 2 ^ bit 7 〇 Although it is miscellaneous (replacement, it is also checking the number of observations - the combination is not the case, and then the health of her job is 丨 _ 3 eth The processing algorithm for the replacement of the error bit is also possible. In Figure 7, the job is simplified. First, after the input address is verified, the secret controller 32 determines the CRC value of the address information (in the generation Whether the value of the polynomial processing is consistent with the check bit of the CRC (S4〇2). When the CRC is inconsistent and the shame is determined, the number c of the waves in which the in-phase is replaced is two bits, and it is determined whether the CRC is - ( S403 and S404). If there are a plurality of bits in 〇2, it is determined whether or not the CRCs of all the quotations of the quotients of the quotations are equal. As described above, first (priority) Since the address of the positive address is only forwarded by a combination of addresses, it is determined whether or not (3) is consistent, but in the case of CRC, the address information is determined in the combination (S4〇8). In the case where all the combinations of the CRCs are inconsistent, then (the bits of M, 2, and 3 are replaced as the wrong bits (S4〇5). Then, The determination is not the same (S406). In the case of the CRC, the address information is determined in the combination (S408). In the case where all combinations are attempted to be inconsistent, the error is finally determined (S407). Thus, by first only for The bit replacement of c=2, and then the bit of C=1, 2, 3 is replaced, and the error correction time can be expected to be shortened. 13 !278839 The number is 2 (phase H t (10)' in the bit data phase G degree The wave of the ί 度 之 之 为 为 2 ί ί ί ί ί ί ί ί CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC CRC Fig. 2 is a structural diagram of the address decoding circuit of the embodiment. Fig. 3 (a) to (d) are timing charts of the dither signal. Fig. 4 is a flow chart of the specific processing of the error bit of the embodiment. Flowchart of the error correction processing of the embodiment Fig. 6 is a detailed processing flowchart of the error correction. Fig. 7 is a flowchart of the processing of the error correction. [Description of main component symbols] 1 〇Disc 12 spindle motor (SPM) 14 driver 16 Optical pickup head 18 screw motor 20 driver 22 driver 24 APC (automatic power control circuit) 26 RF ( Frequency circuit 28 address decoding circuit 28a binarizer 28b EOR gate 28c ratio counter 30 servo processor 1278839 32 system controller 34 binarization circuit 36 encoding/decoding circuit 38 buffer memory 40 interface I/F 42 write strategy Circuit