TWI278688B - Source driving integrated circuit of liquid crystal display module and source driving system using the same - Google Patents

Source driving integrated circuit of liquid crystal display module and source driving system using the same Download PDF

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TWI278688B
TWI278688B TW93115157A TW93115157A TWI278688B TW I278688 B TWI278688 B TW I278688B TW 93115157 A TW93115157 A TW 93115157A TW 93115157 A TW93115157 A TW 93115157A TW I278688 B TWI278688 B TW I278688B
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source
integrated circuit
gamma correction
output
gamma
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TW93115157A
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TW200538797A (en
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Dae-Keun Han
Dae-Seong Kim
Joon-Ho Na
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Silicon Works Co Ltd
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Abstract

The present invention relates to a source driving IC and a source driving system using the same for a LCD module. The source driving system includes a first source driving IC, a n-th source driving IC, and a second source driving IC. The self Gamma Correction Voltage is input and buffered in the first source driving IC, and the buffered self Gamma Correction Voltage is output to the second source driving IC and to the n-th source driving IC via an external circuitry of the first source driving IC. Another Gamma Correction Voltage is input and buffered in the n-th source driving IC, and the buffered another Gamma Correction Voltage is then output to the first source driving IC and the second source driving IC via the external circuitry of the n-th source driving IC. The buffered self Gamma Correction Voltage and the buffered another Gamma Correction Voltage are input to the second source driving IC via the external circuitry of the second source driving IC. The present invention employs a Gamma buffer corresponding to a specific Gamma Correction Voltage to avoid the driving voltage difference between the source driving ICs, and to improve the displaying quality. Further, the Gamma buffer part containing Gamma buffers is integrated into the source driving IC to minimize the number of LCD components.

Description

1278688 玖、發明說明: 【發明所屬之技術領域】 本發明係關於一種液晶顯示裝置,特別係關於一種 改善晝質且減少零件數目之 LCD ( Liquid Crystal Display,液晶顯示器,以下簡稱 LCD )模組之源極驅動 積體電路及其源極驅動系統。1278688 发明, the invention description: [Technical Field] The present invention relates to a liquid crystal display device, and more particularly to an LCD (Liquid Crystal Display, LCD for short) module for improving the quality of the enamel and reducing the number of parts. The source drives the integrated circuit and its source drive system.

【先前技術】 一般來說,LCD係以行列式驅動積體電路,將經由個 人電腦等的圖像處理器處理之影像情報等之數位資料變 換為液晶驅動用信號’施加電壓於液晶上’以顯不影像情 報的顯示裝置。 第1圖係例舉一習知之LCD模組方塊示意圖。習知 之L C D模組係包含一源極驅動系統1 0 0、一源極電路方塊 2 0 0、一閘極驅動系統3 0 0、一閘極電路方塊4 0 0以及一 LCD 面板 500。[Prior Art] In general, an LCD drives an integrated circuit in an ideographic manner, and converts digital data such as video information processed by an image processor such as a personal computer into a liquid crystal driving signal 'applying a voltage to the liquid crystal'. A display device that does not display image information. FIG. 1 is a block diagram showing a conventional LCD module. The conventional L C D module includes a source drive system 100, a source circuit block 200, a gate drive system 300, a gate circuit block 400, and an LCD panel 500.

源極電路方塊2 0 0係包含一時序控制部2 1 0、一電源 部2 2 0以及一伽瑪校正電壓產生部2 3 0。時序控制部2 1 0 係將VGA ( Video Graphic Adapter )埠傳達之影像信號變 換為各種信號,並傳送時序控制信號至源極驅動系統1 0 0 與閘極驅動系統3 00。電源部220係將VGA埠提供之電 源供給至源極驅動系統1 0 0、閘極驅動系統3 0 0以及時序 控制部2 1 0。伽瑪校正電壓產生部2 3 0係以電源部2 2 0提 供的電源產生伽瑪校正電壓(Vgma,Gamma Correction 5 1278688The source circuit block 200 includes a timing control unit 2 1 0, a power supply unit 2 2 0, and a gamma correction voltage generation unit 2 30. The timing control unit 2 1 0 converts the video signal transmitted by the VGA (Video Graphic Adapter) to various signals, and transmits the timing control signal to the source drive system 100 and the gate drive system 300. The power supply unit 220 supplies the power supplied from the VGA port to the source drive system 100, the gate drive system 300 and the timing control unit 2 1 0. The gamma correction voltage generating unit 203 generates a gamma correction voltage by the power supply supplied from the power supply unit 220 (Vgma, Gamma Correction 5 1278688).

Voltage ),並供給至源極驅動電路系統1 00。 顯 路 板 路 板 含 輸 入 控 係 13 信 其 部 驅 L C D面板5 0 0係以未圖示之源極線、閘極線及像素 示晝面。 源極驅動系統 1 0 0係包含複數個源極驅動積體電 晶片1 1 0 - 1〜1 1 0 _ η,與源極電路方塊2 0 0以及L C D面 5 0 0電性連接,以驅動L C D面板5 0 0之源極線。 閘極驅動系統 3 0 0係包含複數個閘極驅動積體電 晶片300-1〜300-m,與閘極電路方塊400以及LCD面 500電性連接,以驅動LCD面板500之閘極線。 如第2圖所示,源極驅動積體電路晶片1 1 0 -1係包 一控制部1 1 1、一移位暫存器1 1 2、一資料暫存器1 1 3、 2線閂鎖1 1 4以及一電壓輸出部1 1 8。控制部1 1 1係以 入之資料起始信號EI01、EI02,極性控制信號POL、載 信號LOAD、資料鎖定信號DCLK以及方向信號Lb/R, 制源極驅動積體電路晶片1 1 0 -1全體。移位暫存器Π 2 於每一時序週期,將全位元位移一位數。資料暫存器1 係輸入反向(reverse)信號REV1、REV2與數位資料 號D 0 0〜D 5 5。2線閂鎖1 1 4係輸入數位資料信號並將 輸出。 如第3圖所示,電壓輸出部1 1 8係包含一伽瑪緩衝 1 17、一輸出D/A (數位/類比)轉換器1 1 5以及一輸出 動電路11 6。 伽瑪緩衝部 1 1 7係包含相同的伽瑪缓衝器 117a、 1 1 7 b、1 1 7 c,將伽瑪校正電壓產生部2 3 0供給之伽瑪校正 1278688 電壓(Vgma)進行緩衝,並輸出缓衝後之伽瑪校正電壓 (Vb-gma,Buffering Gamma Correction Voltage ) 〇Voltage ) and supplied to the source drive circuit system 100. The circuit board includes an input control system. 13 The L C D panel 500 is connected to the source line, the gate line and the pixel (not shown). The source driving system 100 includes a plurality of source-driven integrated circuit chips 1 1 0 - 1 to 1 1 0 _ η, and is electrically connected to the source circuit block 200 and the LCD surface 500 to drive The source line of the LCD panel 500. The gate driving system 300 includes a plurality of gate driving integrated circuits 300-1 to 300-m electrically connected to the gate circuit block 400 and the LCD surface 500 to drive the gate lines of the LCD panel 500. As shown in FIG. 2, the source drive integrated circuit chip 1 1 0 -1 is a control unit 1 1 1 , a shift register 1 1 2, a data register 1 1 3, 2 line latch The lock 1 1 4 and a voltage output unit 1 18 are provided. The control unit 1 1 1 is driven by the data start signals EI01 and EI02, the polarity control signal POL, the load signal LOAD, the data lock signal DCLK, and the direction signal Lb/R, and the source drive integrated circuit chip 1 1 0 -1 All. The shift register Π 2 shifts the full bit by one digit for each timing cycle. The data register 1 is an input reverse signal REV1, REV2 and a digital data number D 0 0 to D 5 5. The 2-wire latch 1 1 4 inputs a digital data signal and outputs it. As shown in Fig. 3, the voltage output unit 1 18 includes a gamma buffer 1 17 , an output D/A (digital/analog) converter 1 15 and an output circuit 116. The gamma buffer unit 1 1 7 includes the same gamma buffers 117a, 1 1 7 b, and 1 1 7 c, and buffers the gamma correction 1278688 voltage (Vgma) supplied from the gamma correction voltage generating unit 2300. And output the buffered gamma correction voltage (Vb-gma, Buffering Gamma Correction Voltage) 〇

輸出D/A轉換器1 1 5係包含一暫存器陣列1 1 5 a以及 一開關陣列部1 1 5 b。暫存器陣列1 1 5 a係以分配阻抗r 1〜 r 6 3將缓衝後之伽瑪校正電壓分配電壓,並輸出分配伽瑪 電壓V 0〜V 6 3。開關陣列部1 1 5 b係包含開關陣列1 1 5 b -1 〜1 1 5b-n,以分配伽瑪電壓切換開關,使數位資料信號變 換為類比資料信號。 與開關陣列 1 1 5 b _ 1〜1 1 5 b - η —對一相對應的,輸出 驅動電路1 1 6係包含複數個輸出緩衝器1 1 6-1〜1 1 6-η,輸 入類比資料信號並向LCD面板500輸出驅動電壓OUT 1 〜Ο U Τ η 〇The output D/A converter 1 1 5 includes a register array 1 1 5 a and a switch array unit 1 1 5 b. The register array 1 1 5 a distributes the voltage to the buffered gamma correction voltage by distributing the impedances r 1 to r 6 3 , and outputs the distributed gamma voltages V 0 V V 6 3 . The switch array unit 1 1 5 b includes a switch array 1 1 5 b -1 〜1 1 5b-n for distributing a gamma voltage switch to convert the digital data signal into an analog data signal. Corresponding to the switch array 1 1 5 b _ 1~1 1 5 b - η - corresponding to one, the output drive circuit 1 16 includes a plurality of output buffers 1 1 6-1~1 1 6-η, input analogy The data signal and the driving voltage OUT 1 ~ Ο U Τ η 〇 are output to the LCD panel 500

如第4圖所示,源極驅動系統1 0 0的外部之伽瑪校正 電壓產生部23 0以四個伽瑪校正阻抗Rl、R2、R3、R4, 將電源部220的第1與第2輸入電壓Vinl、Vin2分配電 壓,成為第1、第2以及第3伽瑪校正電壓Vgmal、Vgma2、 V g m a 3,分別輸出至源極驅動積體電路晶片 1 1 0 _ 1〜 1 10-n。亦即,第1伽瑪校正電壓Vgmal分別輸入第1源 極驅動積體電路晶片1 1 0 -1、第2源極驅動積體電路晶片 1 1 0 - 2、...以及第η源極驅動積體電路晶片1 1 0 - η的伽瑪緩 衝部117中之第1伽瑪缓衝器117a,其中η為大於2的自 然數。第2伽瑪校正電壓Vgma2分別輸入第1源極驅動 積體電路晶片1 1 〇 - :1、第2源極驅動積體電路晶片1 1 0 - 2、… 以及第η源極驅動積體電路晶片1 1 0-n的伽瑪緩衝部1 1 7 7 1278688 中之第2伽瑪缓衝器1 17b。第3伽瑪校正電壓Vgma3分 別輸入第1源極驅動積體電路晶片1 1 0 -1、第2源極驅動 積體電路晶片1 1 〇 - 2、…以及第η源極驅動積體電路晶片 1 1 0-η的伽瑪緩衝部1 1 7中之第3伽瑪缓衝器1 1 7c。 如此構成之習知LCD模組中,伽瑪校正電壓產生部 2 3 0係並列的供給源極驅動系統1 0 0之源極驅動積體電路 晶片 1 1 0 -1〜1 1 0 - η伽瑪校正電壓。此時,伽瑪校正電壓 產生部2 3 0的伽瑪校正阻抗值需適切的調整,以使伽瑪校 正電壓適於LCD面板500的固有特性。 伽瑪校正電壓係分別供給至源極驅動系統 1 〇 〇之源 極驅動積體電路晶片1 1 0 -1〜1 1 0 - η之伽瑪緩衝部1 1 7,伽 瑪緩衝部 117輸出之緩衝後之伽瑪校正電壓 Vb-gmal、 Vb-gma2、Vb-gma3係輸入暫存器陣歹1J 115a。暫存器陣列 1 15a如為η位元(bit )之輸出D/A轉換器1 1 5時,以輸 入之緩衝後之伽瑪校正電壓,將2n個的分配伽瑪電壓並 列的供給至開關陣列部Π 5 b。 如第3圖所示,開關陣列部1 1 5 b的開關陣列1 1 5 b -1 〜1 1 5b-n以分別輸入之數位資料信號,從暫存器陣列1 1 5 a 輸入之2n個的分配伽瑪電壓之中,選擇其一的分配伽瑪 電壓,亦即類比資料信號,傳達至輸出驅動電路Π 6。輸 出驅動電路1 1 6之輸出緩衝器1 1 6 -1〜1 1 6 - η分別將選擇之 分配伽瑪電壓,亦即將驅動電壓 Ο U Τ 1〜Ο U Τ η,輸出至 L C D面板5 0 0,驅動L C D面板5 0 0之源極線。 如第4圖所示,將伽瑪缓衝器1 1 7 a、1 1 7 b、1 1 7 c内 8 1278688 藏於源極驅動積體電路晶片 Π0-1〜110-n中,係為了防 止伽瑪校正電壓產生部2 3 0之伽瑪校正阻抗R 1、R2、R3、 R4,因受到源極驅動積體電路晶片110-1〜110-n的暫存 器陣列1 1 5 a之分配阻抗的影響,而改變伽瑪校正電壓。As shown in FIG. 4, the external gamma correction voltage generating unit 230 of the source drive system 100 outputs the first and second power supply units 220 with four gamma correction impedances R1, R2, R3, and R4. The input voltages Vin1 and Vin2 are distributed to the first, second, and third gamma correction voltages Vgmal, Vgma2, and Vgma 3, and are output to the source drive integrated circuit wafers 1 1 _ 1 to 1 10-n, respectively. In other words, the first gamma correction voltage Vgmal is input to the first source drive integrated circuit wafer 1 1 0 -1, the second source drive integrated circuit wafer 1 1 0 - 2, ..., and the nth source, respectively. The first gamma buffer 117a of the gamma buffer portion 117 of the integrated circuit wafer 1 1 0 - η is driven, where n is a natural number greater than 2. The second gamma correction voltage Vgma2 is input to the first source drive integrated circuit wafer 1 1 〇 - : 1, the second source drive integrated circuit wafer 1 1 0 - 2, ... and the nth source drive integrated circuit The second gamma buffer 1 17b of the gamma buffer portion 1 1 7 7 1278688 of the wafer 1 1 0-n. The third gamma correction voltage Vgma3 is input to the first source drive integrated circuit wafer 1 1 0 -1, the second source drive integrated circuit wafer 1 1 〇-2, ..., and the η source drive integrated circuit chip, respectively. The third gamma buffer 1 1 7c of the gamma buffer portion 1 1 7 of 1 1 0-n. In the conventional LCD module configured as described above, the gamma correction voltage generating unit 203 is provided in parallel with the source driving system 100. The source driving integrated circuit chip 1 1 0 -1 to 1 1 0 - η gamma Ma correction voltage. At this time, the gamma correction impedance value of the gamma correction voltage generating portion 203 is appropriately adjusted so that the gamma correction voltage is adapted to the inherent characteristics of the LCD panel 500. The gamma correction voltage is supplied to the source drive system 1 〇〇 source drive integrated circuit chip 1 1 0 -1 to 1 1 0 - η gamma buffer portion 1 1 7 , gamma buffer portion 117 output The buffered gamma correction voltages Vb-gmal, Vb-gma2, and Vb-gma3 are input to the register array 1J 115a. When the register array 1 15a is an output D/A converter 1 1 5 of n bits, the 2n distributed gamma voltages are supplied in parallel to the switch with the input buffered gamma correction voltage. Array section Π 5 b. As shown in FIG. 3, the switch arrays 1 1 5 b -1 to 1 1 5b-n of the switch array portion 1 1 5 b are input from the register array 1 1 5 a by the digital data signals respectively input. Among the distributed gamma voltages, one of the assigned gamma voltages, that is, the analog data signal, is transmitted to the output drive circuit Π 6. Output buffer circuit 1 1 6 output buffer 1 1 6 -1~1 1 6 - η respectively selects the assigned gamma voltage, that is, the driving voltage Ο U Τ 1~Ο U Τ η, and outputs it to the LCD panel 5 0 0, drive the source line of the LCD panel 500. As shown in FIG. 4, the gamma buffers 1 1 7 a, 1 1 7 b, and 1 1 7 c 8 1278688 are hidden in the source drive integrated circuit chips Π0-1 to 110-n. The gamma correction impedances R 1 , R2 , R3 , and R4 of the gamma correction voltage generating unit 203 are prevented from being subjected to the register array 1 1 5 a of the source driving integrated circuit chips 110-1 to 110-n. The effect of the impedance is assigned and the gamma correction voltage is changed.

亦即,為使伽瑪校正電壓產生部2 3 0所產生的伽瑪校 正電壓不受暫存器陣列1 1 5 a阻抗的影響,所以於伽瑪校 正電壓產生部230的輸出端與暫存器陣列115a的輸入端 之間,插入包含伽瑪緩衝器 11 7a、Π 7b、1 1 7c之伽瑪緩 衝部1 1 7。That is, the gamma correction voltage generated by the gamma correction voltage generating unit 203 is not affected by the impedance of the register array 1 15 a, so the output of the gamma correction voltage generating unit 230 is temporarily stored. Between the input terminals of the array 115a, a gamma buffer portion 1 17 including gamma buffers 11 7a, Π 7b, and 1 7 7c is inserted.

如以上所述,伽瑪緩衝部1 1 7内藏於個別的源極驅動 積體電路晶片1 1 0-1〜1 1 0-η中時,個別的伽瑪缓衝部1 1 7 的特性並不一致。亦即,第1源極驅動積體電路片1 1 0 -1 的伽瑪缓衝器1 1 7 a、第2源極驅動積體電路晶片1 1 0 - 2的 伽瑪緩衝器117a、…以及第η源極驅動積體電路晶片110-n 的伽瑪緩衝器11 7 a間的特性並不一致。因此,即使將伽 瑪校正電壓產生部 2 3 0產生之相同的伽瑪校正電壓輸入 第1源極驅動積體電路晶片110-1的伽瑪緩衝器U7a,與 第η源極驅動積體電路晶片1 1 0-n的伽瑪緩衝器1 1 7a,伽 瑪緩衝器 Π 7 a個別的輸出端之間亦會發生些許的電壓偏 差。因如此的偏差,第1源極驅動積體電路晶片1 1 0 -1的 分配伽瑪電壓如分別成為 VO、VI、V2、…V63,第 η源 極驅動積體電路晶片1 1 0 - η的分配伽瑪電壓可能分別成為 與 V0、VI、V2、...V63 相異之 VO’、VI’、V2’、...V63’。 其結果’源極驅動積體電路晶片110-1、110-n之間亦產 9 1278688 生驅動電壓的偏差,造成LCD的晝質不佳。 因此,為解決 LCD中,利用上述源極驅動系統 100 產生晝質不佳的問題,而有另一習知之源極驅動系統的提 案。 第5圖係例舉另一習知之LCD模組示意圖。As described above, when the gamma buffer portion 1 17 is included in the individual source-driven integrated circuit wafers 1 1 0-1 to 1 1 0-η, the characteristics of the individual gamma buffer portions 1 1 7 Not consistent. That is, the first source drives the integrated circuit chip 1 1 0 -1 gamma buffer 1 1 7 a, the second source drives the integrated circuit chip 1 1 0 - 2 gamma buffer 117a, ... And the characteristics of the gamma buffer 11 7 a of the nth source driving integrated circuit wafer 110-n do not match. Therefore, even the same gamma correction voltage generated by the gamma correction voltage generating unit 203 is input to the gamma buffer U7a of the first source driving integrated circuit wafer 110-1, and the nth source driving integrated circuit. A slight voltage deviation occurs between the individual outputs of the gamma buffer 1 1 7a of the chip 1 10-n and the individual outputs of the gamma buffer Π 7 a. Due to such a deviation, the distributed gamma voltages of the first source-driven integrated circuit wafer 1 1 0 -1 are VO, VI, V2, ..., V63, respectively, and the n-th source-driven integrated circuit wafer 1 1 0 - η The assigned gamma voltage may become VO', VI', V2', ... V63' which are different from V0, VI, V2, ..., V63, respectively. As a result, the deviation of the driving voltage of 9 1278688 between the source driving integrated circuit wafers 110-1 and 110-n also causes poor quality of the LCD. Therefore, in order to solve the problem of poor quality of the above-described source drive system 100 in the LCD, there is another proposal for the source drive system. Fig. 5 is a schematic view showing another conventional LCD module.

為了方便說明及避免說明的重複,在此僅對於第5圖 之源極驅動系統與第1圖〜第4圖中之源極驅動系統1 0 0 之間的相異點進行重點說明。 第5圖所示之L C D模組係一伽瑪緩衝部1 2 7與源極 驅動糸統1 2 0的源極驅動積體電路晶片1 2 0 - 1〜1 2 0 - η共 通連接,配置於源極驅動系統 1 2 0外部之源極電路方塊 2 0 0上,除了第1圖的伽瑪缓衝部1 1 7分別内藏配置於源 極驅動糸統 1 00的源極驅動積體電路晶片 110-1〜110-n 中之相異點之外,與第1圖的LCD模組係相同的構造。For convenience of explanation and avoiding repetition of the description, only the differences between the source drive system of Fig. 5 and the source drive system 100 of Figs. 1 to 4 will be mainly described. The LCD module shown in FIG. 5 is a gamma buffer portion 1 27 and is commonly connected to the source driving integrated circuit chip 1 2 0 - 1 to 1 2 0 - η of the source driving system 120. In the source circuit block 200 outside the source drive system 120, the source drive integrated body disposed in the source drive system 100 is included in the gamma buffer unit 1 1 7 of FIG. 1 . The difference from the circuit chips 110-1 to 110-n is the same as that of the LCD module of Fig. 1.

亦即,第 2圖所示之源極驅動積體電路晶片 110-1 中,伽瑪缓衝部1 1 7係配置於電壓輸出部1 1 8的内部。但 第6圖所示之源極驅動積體電路晶片1 2 0 -1中,伽瑪緩衝 部1 2 7係配置於電壓輸出部1 2 8的外部。 相同的,第3圖所示之電壓輸出部11 8的暫存器陣列 1 1 5 a,係從配置於電壓輸出部 1 1 8内部之伽瑪緩衝部 1 1 7,輸入缓衝後之伽瑪校正電壓。但第7圖所示之電壓 輸出部1 2 8的暫存器陣列1 1 5 a,係從配置於電壓輸出部 1 2 8外部之伽瑪緩衝部1 2 7,輸入緩衝後之伽瑪校正電壓。 以下,以第8圖所示之源極驅動系統1 2 0與第4圖所 10 1278688 示之源極驅動系統進行比較,對於相異點進行說明。That is, in the source drive integrated circuit wafer 110-1 shown in Fig. 2, the gamma buffer portion 1 17 is disposed inside the voltage output portion 1 1 8 . However, in the source drive integrated circuit wafer 1 2 0 -1 shown in Fig. 6, the gamma buffer portion 1 2 7 is disposed outside the voltage output portion 1 28 . Similarly, the register array 1 15 5 a of the voltage output unit 11 shown in FIG. 3 is input from the gamma buffer unit 1 1 7 disposed inside the voltage output unit 1 1 8 . Ma correction voltage. However, the register array 1 15 a of the voltage output unit 1 28 shown in FIG. 7 is gamma corrected after input buffering from the gamma buffer unit 1 2 7 disposed outside the voltage output unit 1 2 8 . Voltage. Hereinafter, the source drive system shown in Fig. 8 is compared with the source drive system shown in Fig. 4, 1 1278688, and the different points will be described.

源極驅動系統1 2 0外部之伽瑪校正電壓產生部2 3 0輸 出之伽瑪校正電壓Vgmal、Vgma2、Vgma3,分別輸入源 極驅動系統1 2 0外部之伽瑪緩衝部1 2 7,伽瑪緩衝部1 2 7 將緩衝後之伽瑪校正電壓Vb-gmal、Vb-gma2、Vb-gma3, 分別輸入源極驅動系統 1 2 0 的源極集積驅動電路晶片 1 2 Ο -1〜1 2 Ο _ η的暫存器陣列1 1 5 a。亦即,第1、第2以及 第3緩衝後之伽瑪校正電壓,分別輸入内藏於第1源極驅 動積體電路晶片 120-1、第 2源極驅動積體電路晶片 1 2 0 - 2、…以及第η源極驅動積體電路晶片1 2 0 - η的輸出 D/Α轉換器1 1 5内部的暫存器陣列1 1 5 a。The gamma correction voltages Vgmal, Vgma2, and Vgma3 output from the gamma correction voltage generating unit 2 3 0 of the source driving system 1 2 0 are respectively input to the gamma buffer portion 1 2 7 of the source driving system 1 2 0 The buffer portion 1 2 7 inputs the buffered gamma correction voltages Vb-gmal, Vb-gma2, and Vb-gma3 to the source-accumulation drive circuit chip 1 2 Ο -1 to 1 2 of the source drive system 1 2 0, respectively.暂 _ η of the register array 1 1 5 a. In other words, the gamma correction voltages after the first, second, and third buffers are respectively input to the first source-driven integrated circuit wafer 120-1 and the second source-driven integrated circuit wafer 1 2 0 - 2, ... and the nth source drive integrated circuit chip 1 2 0 - η output D / Α converter 1 1 5 internal register array 1 1 5 a.

第1圖、第2圖、第3圖以及第4圖中所示之源極驅 動系統1 0 0中,分別將包含複數個伽瑪緩衝器之伽瑪緩衝 部1 1 7内藏於源極驅動積體電路晶片1 1 0 -1〜1 1 0 - η内部 中,因伽瑪緩衝器個別的特性不一造成源極驅動積體電路 晶片 1 1 0 -1〜1 1 0 - η之間的輸出偏差,亦即,發生驅動電 壓偏差而產生晝質不佳的問題。為解決如此晝質不佳的問 題,如第5圖、第6圖、第7圖以及第8圖中所示之源極 驅動系統1 2 0,以其他零件構成包含複數伽瑪緩衝器之伽 瑪缓衝部 1 2 7,配置於源極驅動積體電路晶片 1 2 0 -1〜 1 20-η外部,習知技術之晝質不佳問題即獲得改善。亦即, 不受伽瑪緩衝器之間特性不一致的影響,第1源極驅動積 體電路晶片 120-1 中分配伽瑪電壓如為 VO、VI、 V 2、... V 6 3,第η源極驅動積體電路晶片1 2 0 - η中分配伽 11 1278688 瑪電壓亦為 VO、VI、V2、…V63而不會產生電壓偏差, 另外,個別的源極驅動積體電路晶片 1 2 0 -1〜1 2 0 -η之間 亦不會產生驅動電壓的偏差,造成晝質不佳。 但因追加其他的零件,會造成組裝製程的階段增加, 不良率提高,且有費用增加的問題。 【發明内容】 為解決上述問題,本發明之一目的,係對於一特定的 伽瑪校正電壓使用一伽瑪緩衝器,避免源極驅動積體電路 晶片之間產生驅動電壓偏差,以改善晝質不佳的問題。 本發明之另一目的,係將包含複數個伽瑪緩衝器之伽 瑪緩衝部内藏於源極驅動積體電路晶片中,以減少 LCD 模組的零件數目。 為達成上述目的,本發明之LCD模組源極驅動積體 電路,其係位於一源極驅動積體電路晶片中,該源極驅動 積體電路晶片包含一電壓輸出部,以輸出驅動L C D面板 源極線之驅動電壓。電壓輸出部係包含一伽瑪緩衝部、一 輸出D/A轉換器以及一輸出驅動電路。伽瑪緩衝部係分別 將伽瑪校正電壓產生部一側輸入之自我伽瑪校正電壓進 行緩衝,將緩衝後之自我伽瑪校正電壓輸出源極驅動積體 電路晶片外部。輸出D/A轉換器係藉由源極驅動積體電路 晶片外部輸入之緩衝後之另一伽瑪校正電壓,與緩衝後之 自我校正電壓,將資料暫存器輸入之數位信號變換為類比 信號,並將其輸出,其中缓衝後之另一伽瑪校正電壓,係 12 1278688 該當於從伽瑪校正電壓產生部另一側輸出之另一 正電壓。輸出驅動電路係將輸出D/A轉換器輸入之 料信號變換為驅動 L C D面板源極線的驅動電壓, 輸出。 伽瑪緩衝器係至少包含一伽瑪緩衝器。 輸出 D/A轉換器係至少包含一暫存器陣列以 關陣列部。暫存器陣列係將缓衝後之自我伽瑪校正 缓衝後之另一伽瑪校正電壓,藉由分配阻抗分配電 出分配伽瑪電壓。開關陣列部係至少包含一開關陣 以將分配伽瑪電壓輸入,切換開關,使數位資料信 變換為類比資料信號。 輸出驅動電路係至少包含與開關陣列一對一 的複數個輸出緩衝器,將開關陣列輸入類比資料信 為驅動電壓,並將其輸出。 利用本發明之L CD模組之源極驅動積體電路 驅動系統,係包含具有相同内部構造之一第1源極 體電路晶片以及一第η源極驅動積體電路晶片。 第1源極驅動積體電路晶片係包含一伽瑪缓律 輸出D/A轉換器以及一電壓輸出部。伽瑪緩衝部係 伽瑪校正電壓產生部一側輸入之自我伽瑪校正電 缓衝,將緩衝後之自我伽瑪校正電壓輸出第1源極 體電路晶片外部。輸出D/A轉換器係藉由第1源極 體電路晶片外部輸入之緩衝後之另一伽瑪校正電® 衝後之自我伽瑪校正電壓,將資料暫存器輸入之數 伽瑪校 類比資 並將其 及一開 電壓與 壓,輸 列,用 號分別 相對應 號變換 的源極 驅動積 部、一 分別將 壓進行 驅動積 驅動積 ,與緩 位資料In the source driving system 100 shown in FIG. 1 , FIG. 2 , FIG. 3 , and FIG. 4 , a gamma buffer unit 1 17 including a plurality of gamma buffers is respectively included in the source. Driving the integrated circuit chip 1 1 0 -1 to 1 1 0 - η inside, due to the individual characteristics of the gamma buffer, the source drives the integrated circuit chip 1 1 0 -1~1 1 0 - η The output deviation, that is, the drive voltage deviation occurs, causes a problem of poor quality. In order to solve such a problem of poor quality, the source driving system 1 2 0 shown in FIG. 5, FIG. 6, FIG. 7, and FIG. 8 constitutes a gamma containing a complex gamma buffer with other components. The imaginary buffer portion 1 27 is disposed outside the source-driven integrated circuit wafer 1 2 0 -1 to 1 20-η, and the problem of poor quality of the prior art is improved. That is, the gamma voltages assigned to the first source-driven integrated circuit chip 120-1 are VO, VI, V 2, ... V 6 3, which are not affected by the inconsistency in characteristics between the gamma buffers. η source drive integrated circuit wafer 1 2 0 - η distribution gamma 11 1278688 The mA voltage is also VO, VI, V2, ... V63 without voltage deviation, and the individual source drives the integrated circuit chip 1 2 There is no deviation of the driving voltage between 0 -1 and 1 2 0 -η, resulting in poor quality. However, the addition of other parts will increase the stage of the assembly process, increase the defect rate, and increase the cost. SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to use a gamma buffer for a specific gamma correction voltage to avoid a driving voltage deviation between source driving integrated circuit chips to improve enamel quality. Poor question. Another object of the present invention is to incorporate a gamma buffer portion including a plurality of gamma buffers into a source drive integrated circuit chip to reduce the number of parts of the LCD module. In order to achieve the above object, the LCD module source driving integrated circuit of the present invention is located in a source driving integrated circuit chip, and the source driving integrated circuit chip includes a voltage output portion for outputting and driving the LCD panel. The driving voltage of the source line. The voltage output unit includes a gamma buffer, an output D/A converter, and an output drive circuit. The gamma buffer unit buffers the self-gamma correction voltage input from the gamma correction voltage generating unit side, and drives the buffered self-gamma correction voltage output source to the outside of the integrated circuit chip. The output D/A converter converts the digital signal input from the data register into an analog signal by buffering another gamma correction voltage externally input from the source driving circuit chip and the buffered self-correcting voltage. And outputting it, wherein another gamma correction voltage after buffering is 12 1278688 which is another positive voltage outputted from the other side of the gamma correction voltage generating portion. The output drive circuit converts the input signal of the output D/A converter into a drive voltage for driving the source line of the L C D panel, and outputs it. The gamma buffer system includes at least one gamma buffer. The output D/A converter includes at least one register array to close the array. The register array is a gamma correction voltage buffered by the buffered self gamma correction, and the gamma voltage is distributed by distributing the impedance distribution. The switch array unit includes at least one switch array to input the distributed gamma voltage, and the switch is switched to convert the digital data signal into an analog data signal. The output drive circuit includes at least a plurality of output buffers one-to-one with the switch array, and the switch array input analog data is referred to as a drive voltage and output. The source driving integrated circuit driving system using the L CD module of the present invention includes a first source circuit chip having the same internal structure and an nth source driving integrated circuit chip. The first source drive integrated circuit chip includes a gamma slow law output D/A converter and a voltage output unit. The gamma buffer portion is a self gamma correction power buffer input to the gamma correction voltage generating portion, and outputs the buffered self gamma correction voltage to the outside of the first source circuit chip. The output D/A converter is a gamma calibration analogy input to the data register by a self-gamma correction voltage after buffering another gamma correction power input from the external input of the first source body circuit chip. And the voltage and pressure, the output, the source drive product, which is converted by the corresponding number, the drive product, and the slow data.

13 1278688 信號變換為類比資料信號,並將其輸出,其中,緩衝後之 另一伽瑪校正電壓,係該當於從伽瑪校正電壓產生部另一 側輸出之另一伽瑪校正電壓。電壓輸出部係包含一輸出驅 動電路,用以將輸出D/A轉換器輸入之類比資料信號變換 為驅動LCD面板源極線的驅動電壓,並將其輸出。13 1278688 The signal is converted into an analog data signal and outputted, wherein the buffered another gamma correction voltage is another gamma correction voltage outputted from the other side of the gamma correction voltage generating portion. The voltage output unit includes an output driving circuit for converting an analog data signal of the output D/A converter input into a driving voltage for driving the source line of the LCD panel, and outputting the same.

第η源極驅動積體電路晶片係包含一伽瑪缓衝部、一 輸出D/A轉換器以及一電壓輸出部。伽瑪緩衝部係將伽瑪 校正電壓產生部另一側輸出之另一伽瑪校正電壓進行缓 衝,將緩衝後之另一伽瑪校正電壓輸出至第1源極驅動積 體電路晶片。輸出D/A轉換器係藉由輸入第1源極驅動積 體電路晶片的緩衝後之自我伽瑪校正電壓,與向第η源極 驅動積體電路晶片外部輸出之緩衝後之另一伽瑪校正電 壓,將資料暫存器輸入之數位資料信號變換為類比資料信 號,並將其輸出。電壓輸出部係包含一輸出驅動電路,用 以將輸出 D/A轉換器輸入之類比資料信號變換為驅動 LCD面板源極線的驅動電壓,並將其輸出。The nth source driving integrated circuit chip includes a gamma buffer portion, an output D/A converter, and a voltage output portion. The gamma buffer unit buffers another gamma correction voltage outputted from the other side of the gamma correction voltage generating unit, and outputs the buffered another gamma correction voltage to the first source driving integrated circuit chip. The output D/A converter is a buffered self-gamma correction voltage input to the first source-driven integrated circuit chip, and another buffered gamma outputted to the outside of the n-th source driving integrated circuit chip. The voltage is corrected, and the digital data signal input from the data register is converted into an analog data signal and output. The voltage output unit includes an output driving circuit for converting an analog data signal input from the output D/A converter into a driving voltage for driving the source line of the LCD panel, and outputting the same.

第1源極驅動積體電路晶片之伽瑪缓衝部,係至少包 含一伽瑪緩衝器,伽瑪缓衝器係輸出緩衝後之自我伽瑪校 正電壓。 第η源極驅動積體電路晶片之伽瑪缓衝部,係至少包 含一伽瑪緩衝器,伽瑪緩衝器係輸出緩衝後之另一伽瑪校 正電壓。 另外,利用本發明之LCD模組之源極驅動積體電路 之源極驅動系統,係包含具有相同内部構造之一第1源極 14 1278688 驅動積體電路晶片、一第2源極驅動積體電路晶片以及一 第η源極驅動積體電路晶片。 第1源極驅動積體電路晶片係包含一伽瑪緩衝部、一 輸出D/A轉換器以及一輸出驅動電路。伽瑪緩衝部係將伽 瑪校正電壓產生部一側輸入之自我伽瑪校正電壓分別進 行緩衝,將緩衝後之自我伽瑪校正電壓輸出第1源極驅動 積體電路晶片外部。輸出D/A轉換器係藉由第1源極驅動 積體電路晶片外部輸入之緩衝後之另一伽瑪校正電壓,與 緩衝後之自我伽瑪校正電壓,將資料暫存器輸入之數位資 料信號變換為類比資料信號,並將其輸出,其中緩衝後之 另一伽瑪校正電壓,係該當於從伽瑪校正電壓產生部另一 側輸出之另一伽瑪校正電壓。輸出驅動電路係將輸出D/A 轉換器輸入之類比資料信號變換為驅動LCD面板源極線 的驅動電壓,並將其輸出。 第η源極驅動積體電路晶片係包含一伽瑪緩衝部、一 輸出D/A轉換器以及一電壓輸出部。伽瑪緩衝部係將伽瑪 校正電壓產生部另一側輸出之另一伽瑪校正電壓進行缓 衝,將緩衝後之另一伽瑪校正電壓輸出至第1與第2源極 驅動積體電路晶片。輸出D/A轉換器係藉由輸入第1源極 驅動積體電路晶片的緩衝後之自我伽瑪校正電壓,與向第 η源極驅動積體電路晶片外部輸出的緩衝後之另一伽瑪校 正電壓,將資料暫存器輸入之數位資料信號變換為類比資 料信號,並將其輸出。電壓輸出部係包含一輸出驅動電 路,用以將輸出D/A轉換器輸入之類比資料信號變換為驅 15 1278688 動LCD面板源極線的驅動電壓,並將其輸出。The gamma buffer portion of the first source-driven integrated circuit chip includes at least one gamma buffer, and the gamma buffer outputs the buffered self-gamma correction voltage. The gamma buffer portion of the nth source driving integrated circuit chip includes at least one gamma buffer, and the gamma buffer outputs another gamma correction voltage after buffering. In addition, the source driving system using the source driving integrated circuit of the LCD module of the present invention includes one of the same internal structures, the first source 14 1278688, the driving integrated circuit chip, and the second source driving integrated body. The circuit chip and an nth source drive integrated circuit chip. The first source driving integrated circuit chip includes a gamma buffer portion, an output D/A converter, and an output driving circuit. The gamma buffer unit buffers the self-gamma correction voltage input from the gamma correction voltage generating unit side, and outputs the buffered self gamma correction voltage to the outside of the first source driving integrated circuit chip. The output D/A converter is a digital gamma correction voltage that is buffered by the external input of the first source driving integrated circuit, and the self-gamma correction voltage after the buffer is used to input the digital data into the data register. The signal is converted into an analog data signal and outputted, wherein the buffered another gamma correction voltage is another gamma correction voltage outputted from the other side of the gamma correction voltage generating portion. The output drive circuit converts the analog data signal of the output D/A converter input into a drive voltage for driving the source line of the LCD panel, and outputs it. The nth source driving integrated circuit chip includes a gamma buffer portion, an output D/A converter, and a voltage output portion. The gamma buffer unit buffers another gamma correction voltage outputted from the other side of the gamma correction voltage generation unit, and outputs the buffered another gamma correction voltage to the first and second source drive integrated circuits. Wafer. The output D/A converter is a buffered self gamma correction voltage input to the first source driving integrated circuit chip, and another buffered gamma outputted to the outside of the nth source driving integrated circuit chip. The voltage is corrected, and the digital data signal input from the data register is converted into an analog data signal and output. The voltage output unit includes an output driving circuit for converting the analog data signal of the output D/A converter input into a driving voltage of the source line of the driving LCD panel and outputting the driving voltage.

第2源極驅動積體電路晶片係包含一輸出D/A轉換器 以及一電壓輸出部。輸出D/A轉換器係藉由輸入第1源極 驅動積體電路晶片的缓衝後之自我伽瑪校正電壓,與第η 源極驅動積體電路晶片的緩衝後之另一伽瑪校正電壓,將 資料暫存器輸入之數位資料信號變換為類比資料信號,並 將其輸出。電壓輸出部係包含一輸出驅動電路,用以將輸 出D/A轉換器輸入之類比資料信號變換為驅動LCD面板 源極線的驅動電壓,並將其輸出。 本發明中之第2源極驅動積體電路晶片,係至少包含 一個之第2源極驅動積體電路晶片。 【實施方式】 以下參考添附的圖式,以一較佳實施例詳細說明本發 明之LCD模組的源極驅動積體電路及其源極驅動系統。The second source drive integrated circuit chip includes an output D/A converter and a voltage output unit. The output D/A converter is a buffered self-gamma correction voltage input to the first source-driven integrated circuit chip, and another gamma correction voltage after buffering of the n-th source-driven integrated circuit chip. Converting the digital data signal input from the data register into an analog data signal and outputting it. The voltage output unit includes an output driving circuit for converting an analog data signal of the output D/A converter input into a driving voltage for driving the source line of the LCD panel, and outputting the same. In the second source-driven integrated circuit wafer of the present invention, at least one of the second source-driven integrated circuit wafers is included. [Embodiment] Hereinafter, a source driving integrated circuit of an LCD module of the present invention and a source driving system thereof will be described in detail with reference to the accompanying drawings.

如第 9圖所示,本發明之一較佳應用實施例之LCD 模組係包含一源極驅動系統1 3 0、一源择電路方塊2 0 0、 一閘極驅動系統3 0 0、一閘極電路方塊4 0 0以及一 L C D面 板 5 00。 源極電路方塊2 0 0係包含一時序控制部2 1 0、一電源 部2 2 0以及一伽瑪校正電壓產生部2 3 0。時序控制部2 1 0 係將VGA埠傳來的影像信號變換為各種信號,並傳送時 序控制信號至源極驅動系統1 3 0以及閘極驅動系統3 0 0。 電源部220係將VGA埠提供的電源,供給至源極驅動系 16 1278688 統1 3 Ο、閘極驅動系統3 Ο 0以及時序控制部2 1 0。伽瑪校 正電壓產生部2 3 0係以電源部2 2 0供給的電源產生伽瑪校 正電壓,供給源極驅動系統1 3 0。 L C D面板5 0 0係以未圖示之源極線、閘極線及像素顯 示晝面。As shown in FIG. 9, an LCD module according to a preferred embodiment of the present invention includes a source driving system 130, a source circuit block 200, a gate driving system 300, and a The gate circuit block 400 and an LCD panel 500. The source circuit block 200 includes a timing control unit 2 1 0, a power supply unit 2 2 0, and a gamma correction voltage generation unit 2 30. The timing control unit 2 1 0 converts the video signal transmitted from the VGA port into various signals, and transmits the timing control signal to the source drive system 130 and the gate drive system 300. The power supply unit 220 supplies the power supplied from the VGA port to the source drive system 16 1278 688, the gate drive system 3 Ο 0, and the timing control unit 2 1 0. The gamma correction voltage generating unit 203 generates a gamma correction voltage from the power supply supplied from the power supply unit 220, and supplies it to the source drive system 130. The L C D panel 500 is displayed on the source line, the gate line, and the pixel (not shown).

源極驅動系統 1 3 0係包含複數個具有相同内部構造 的源極驅動積體電路晶片1 3 Ο -1〜1 3 Ο - η,與源極電路方塊 200以及LCD面板5 00電性連接,以驅動LCD面板500 之源極線。閘極驅動系統3 0 0係包含複數個閘極驅動積體 電路晶片300-1〜300-m,與閘極電路方塊400以及LCD 面板5 00電性連接,以驅動LCD面板5 00之閘極線。The source driving system 130 includes a plurality of source driving integrated circuit chips 1 3 Ο -1 〜 1 3 Ο - η having the same internal structure, and is electrically connected to the source circuit block 200 and the LCD panel 500. To drive the source line of the LCD panel 500. The gate driving system 300 includes a plurality of gate driving integrated circuit chips 300-1 300-m, electrically connected to the gate circuit block 400 and the LCD panel 500 to drive the gate of the LCD panel 500 line.

如第1 2圖所示,源極驅動系統1 3 0包含具有相同内 部構造之一第1源極驅動積體電路晶片1 3 0 -1以及一第η 源極驅動積體電路晶片1 3 0 - η。或者,源極驅動系統1 3 0 亦可包含具有相同内部構造之一第1源極驅動積體電路 晶片1 3 0 -1,一第2源極驅動積體電路晶片1 3 0 - 2以及一 第η源極驅動積體電路晶片1 30-η。 第1源極驅動積體電路晶片1 3 0 -1係將伽瑪校正電 壓,亦即自我伽瑪校正電壓Vgma2、Vgma3,以及另一伽 瑪校正電壓Vgmal中之自我伽瑪校正電壓Vgma2、Vgma3 輸入,進行緩衝,並輸出缓衝後之自我伽瑪校正電壓 V b - g m a 2、V b - g m a 3,將此經由第1源極驅動積體電路晶 片1 3 0 -1的外部電路輸入的同時,傳達至第2源極驅動積 體電路晶片1 30-2〜第η源極驅動積體電路晶片1 30-η。 17 1278688 另外,第η源極驅動積體電路晶片1 3 O-n係輸入另一 伽瑪校正電壓 V g m a 1,輸出緩衝後之另一伽瑪校正電壓 Vb-gmal,將此經由第η源極驅動積體電路晶片的外部電 路輸入的同時’傳達至第1源極驅動積體電路晶片130-1 〜第2源極驅動積體電路晶片130-2。 第2源極驅動積體電路晶片1 3 0 - 2係輸入苐1源極驅 動積體電路 1 3 0 -1輸出之緩衝後之自我伽瑪校正電壓 Vb-gma2、Vb-gma3,與第η源極驅動積體電路晶片130-η 輸出之緩衝後之另一伽瑪較電壓V b - g m a 1。 源極驅動系統1 3 0内至少包含一個與第2源極驅動積 體電路晶片1 3 0 - 2具有相同内部構造與動作之源極驅動積 體電路晶片。 如第1 0圖所示,源極驅動積體電路晶片1 3 0 -1係包 含一控制部111、一移位暫存器1 1 2、一資料暫存器1 1 3、 一 2線閂鎖1 1 4以及一電壓輸出部1 3 8。 控制部1 1 1係以輸入之資料起始信號EI01、EI02,極 性控制信號POL,下載信號LOAD,資料鎖定信號DCLK 以及方向信號 Lb/R,控制源極驅動積體電路晶片 130-1 全體。 移位暫存器11 2係於每一時序週期,將全部的位元位 移一位數。 資料暫存器113係輸入反向信號REV1、REV2與數位 資料信號D00〜D55。 2線閂鎖1 1 4係輸入數位資料信號並將其輸出。 18 1278688 電壓輸出部1 3 8係輸入伽瑪校正電壓產生部2 3 0的自 我伽瑪校正電壓,並輸出緩衝後之自我伽瑪校正電壓,將 此經由第1源極驅動積體電路晶片1 3 Ο -1的外部電路輸入 輸出D/A轉換器1 1 5,同時傳達至第2源極驅動積體電路 晶片130-2〜第η源極驅動積體電路晶片130-η。另外, 電壓輸出部1 3 8係輸入第η源極驅動積體電路晶片1 3 0-η 之缓衝後之另一伽瑪校正電壓。 因此,電壓輸出部1 3 8係輸入緩衝後之自我伽瑪校正 電壓,與緩衝後之另一伽瑪校正電壓以及數位資料信號, 以輸出驅動電壓0UT1〜OUTn,驅動第9圖中之LCD面 板5 0 0的源極線(未圖示)。 如第11圖所示,電壓輸出部1 3 8係包含一伽瑪緩衝 部137' —輸出D/A轉換器115以及一輸出驅動電路116。 伽瑪缓衝部1 3 7係包含複數個伽瑪緩衝器1 1 7a、 117b, 將伽瑪校正電壓產生部 2 3 0供給之自我伽瑪校正電壓 Vgma2、Vgma3進行緩衝,將緩衝後之自我伽瑪校正電壓 Vb-gma2、Vb-gma3,輸出第1源極驅動積體電路晶片130-1 外部。第1 1圖中,以包含二個伽瑪緩衝器1 1 7a、1 1 7b之 伽瑪緩衝部1 3 7之一較佳實施例進行說明,但伽瑪緩衝部 1 3 7亦可使用至少包含一個伽瑪緩衝器之伽瑪緩衝部,所 包含的伽瑪緩衝器中亦可有未使用者。為了方便說明,第 1 1圖中並未圖示第1 0圖中的控制部 1 1 1、移位暫存器 1 1 2、資料暫存器1 1 3以及2線閂鎖1 1 4,但實際上亦配置 於第1源極驅動積體電路晶片130-1中。 19 1278688 第1 2圖中之第η源極驅動積體電路晶片1 3 O-n係將 缓衝後之另一伽瑪校正電壓Vb-gmal,輸出至第卜2、...n-1 源極驅動積體電路晶片。As shown in FIG. 2, the source driving system 130 includes one of the first internal driving integrated circuit wafers 1 3 0 -1 and an nth source driving integrated circuit wafer 1 3 0 having the same internal structure. - η. Alternatively, the source driving system 130 may also include a first source driving integrated circuit wafer 1 3 0 -1 having a same internal structure, a second source driving integrated circuit wafer 1 3 0 - 2 and a The nth source drives the integrated circuit wafer 1 30-n. The first source driving integrated circuit chip 1 3 0 -1 sets the gamma correction voltage, that is, the self gamma correction voltages Vgma2, Vgma3, and the self gamma correction voltages Vgma2, Vgma3 in the other gamma correction voltage Vgmal. Input, buffer, and output buffered self-gamma correction voltages V b - gma 2, V b - gma 3, which are input via an external circuit of the first source-driven integrated circuit chip 1 3 0 -1 At the same time, it is transmitted to the second source drive integrated circuit chip 1 30-2 to the nth source drive integrated circuit wafer 1 30-n. 17 1278688 In addition, the nth source driving integrated circuit chip 13 3 On inputs another gamma correction voltage V gma 1 and outputs another buffered gamma correction voltage Vb-gmal, which is driven via the nth source. The external circuit of the integrated circuit chip is input and transmitted to the first source drive integrated circuit chip 130-1 to the second source drive integrated circuit chip 130-2. The second source-driven integrated circuit wafer 1 3 0 - 2 is the input 苐 1 source-driven integrated circuit 1 3 0 -1 output buffered self-gamma correction voltages Vb-gma2, Vb-gma3, and η The source drives the integrated gamma circuit chip 130-n output buffered another gamma voltage V b - gma 1. The source drive system 130 includes at least one source drive integrated circuit wafer having the same internal structure and operation as the second source drive integrated circuit wafer 1 3 0 - 2 . As shown in FIG. 10, the source driving integrated circuit chip 1 3 0 -1 includes a control unit 111, a shift register 1 1 2, a data register 1 1 3, and a 2-wire latch. The lock 1 1 4 and a voltage output unit 1 3 8 are provided. The control unit 1 1 1 controls the source drive integrated circuit chip 130-1 by the input data start signals EI01 and EI02, the polarity control signal POL, the download signal LOAD, the data lock signal DCLK, and the direction signal Lb/R. The shift register 11 2 shifts all bits by one bit for each timing cycle. The data register 113 inputs the reverse signals REV1, REV2 and the digital data signals D00 to D55. 2-wire latch 1 1 4 Enter the digital data signal and output it. 18 1278688 The voltage output unit 1 3 8 inputs the self-gamma correction voltage of the gamma correction voltage generation unit 2 3 0, and outputs the buffered self-gamma correction voltage, and drives the integrated circuit wafer 1 via the first source. The external circuit input/output D/A converter 1 1 5 of Ο-1 is simultaneously transmitted to the second source drive integrated circuit chip 130-2 to the nth source drive integrated circuit wafer 130-n. Further, the voltage output unit 138 receives another gamma correction voltage buffered by the n-th source drive integrated circuit wafer 1 3 0-n. Therefore, the voltage output unit 138 inputs the buffered self gamma correction voltage, and the buffered another gamma correction voltage and the digital data signal to output the driving voltages OUT1 to OUTn to drive the LCD panel in FIG. Source line of 500 (not shown). As shown in Fig. 11, the voltage output unit 138 includes a gamma buffer unit 137', an output D/A converter 115, and an output drive circuit 116. The gamma buffer unit 1 3 7 includes a plurality of gamma buffers 1 1 7a and 117b, and buffers the self-gamma correction voltages Vgma2 and Vgma3 supplied from the gamma correction voltage generating unit 2300, and buffers the self. The gamma correction voltages Vb-gma2 and Vb-gma3 are output to the outside of the first source drive integrated circuit chip 130-1. In the first embodiment, a preferred embodiment of the gamma buffer portion 137 including two gamma buffers 1 1 7a and 1 1 7b is described, but the gamma buffer portion 137 may also be used. A gamma buffer containing a gamma buffer may be included in the gamma buffer included. For convenience of description, the control unit 1 1 1 , the shift register 1 1 2, the data register 1 1 3, and the 2-wire latch 1 1 4 in the FIG. 1 are not shown in FIG. However, it is actually disposed in the first source drive integrated circuit chip 130-1. 19 1278688 The nth source drive integrated circuit chip 1 in FIG. 2 3 On outputs another buffered gamma correction voltage Vb-gmal to the second, ..., n-1 source The integrated circuit chip is driven.

輸出D/A轉換器115係包含一暫存器陣列115a以及 一開關陣列部1 1 5 b。暫存器陣列1 1 5 a係將經由第1源極 驅動積體電路晶片1 3 0 _ 1外部電路輸入之緩衝後之伽瑪自 我校正電壓Vb-gma2、Vb-gma3,以及缓衝後之另一伽瑪 校正電壓Vb-gmal,以分配阻抗r 1〜r63分配電壓後,輸 出分配伽瑪電壓V 0〜V 6 3。開關陣列部1 1 5 b係包含開關 陣列115b-l〜115b-n,用以將輸入之分配伽瑪電壓 V0〜 V63切換開關,將2線閂鎖1 1 4之數位資料信號分別變換 為類比資料信號。第1 1圖與第1 2圖中之較佳實施例以 6 3個分配阻抗進行說明,但分配阻抗的個數亦可增減。The output D/A converter 115 includes a register array 115a and a switch array portion 1 15b. The buffer array 1 1 5 a is a buffered gamma self-correcting voltage Vb-gma2, Vb-gma3 input through the external circuit of the first source driving integrated circuit chip 1 3 0 _1, and after buffering The other gamma correction voltage Vb-gmal outputs the distribution gamma voltages V 0 V V 6 3 after the voltages are distributed by the distribution impedances r 1 to r63. The switch array unit 1 1 5 b includes switch arrays 115b-1 to 115b-n for switching the input distributed gamma voltages V0 V V63 to convert the digital data signals of the 2-wire latch 1 1 4 into analogies. Data signal. The preferred embodiment of Figures 1 1 and 2 is illustrated with 63 distribution impedances, but the number of distribution impedances may be increased or decreased.

與開關陣列 1 1 5b-l〜1 1 5b-n —對一相對應的,輸出 驅動電路1 1 6係包含複數個緩衝器1 1 6-1〜1 1 6-n,將開關 陣列115b-l〜115b-n輸入之類比資料信號變換為驅動電 壓OUT1〜OUTn,並輸出至LCD面板500的源極線。 以下,參考第1 2圖之較佳實施例,說明源極驅動系 統1 3 0的連接關係,以第1源極驅動積體電路晶片1 3 0 -1 與第η源極驅動積體電路晶片1 3 0 - η之間的連接關係為例 來說明。 為了方便說明,第12圖中並未圖示第10圖的控制部 1 1卜移位暫存器1 1 2、資料暫存器1 1 3以及2線閂鎖1 1 4 ’ 但實際上亦分別配置於第1、2、……η源極驅動積體電路 20 1278688 晶片130-1〜130·η中。 源極驅動系統1 3 0外部之伽瑪校正電壓產生部2 3 0係 將電源部220傳達的第1與第2輸入電壓Vinl、Vin2,經 由伽瑪校正阻抗R 1、R2、R3、R4分配電壓後,輸出第1、 第2以及第3伽瑪校正電壓Vgmal、Vgma2、Vgma3。此 一較佳實施例以4個伽瑪校正阻抗進行說明,但伽瑪校正 阻抗的個數亦可增減。 此時,第 1第 2以及第 3伽瑪校正電壓 V g m a 1、 V g m a 2、V g m a 3分別輸入源極驅動積體電路晶片1 3 0 -1〜 13 0-n。亦即,第1伽瑪校正電壓Vgmal輸入第η源極驅 動積體電路晶片1 3 0 -η的伽瑪緩衝部1 3 7中之第1伽瑪緩 衝器1 1 7a,第2伽瑪校正電壓Vgma2輸入第1源極驅動 驅動積體電路晶片1 3 0 -1的伽瑪緩衝部1 3 7中之第1伽瑪 緩衝器1 1 7a,第3伽瑪校正電壓Vgma3輸入第1源極驅 動積體電路晶片1 3 0 -1的伽瑪緩衝部1 3 7中之第2伽瑪緩 衝器1 1 7b。上述之第1伽瑪校正電壓V gma 1係另一伽瑪 校正電壓,而第 2與第3伽瑪校正電壓 Vgma2、Vgma3 係自我伽瑪校正電壓。 第η源極驅動積體電路片1 3 0-η之第1伽瑪缓衝器 1 17a將第1伽瑪校正電壓Vgmal進行緩衝,經由第η源 極驅動積體電路晶片1 3 0-η的外部電路,將第1緩衝後之 伽瑪校正電壓Vb-gmal,輸出至第1源極驅動積體電路晶 片1 3 0 -1的暫存器陣列1 1 5 a,與第η源極驅動積體電路晶 片1 3 0 - η的暫存器陣列1 1 5 a。另外,第1緩衝後之伽瑪校 21 1278688 正電壓Vb-gmal,輸出至第2源極驅動積體電路晶> 之暫存器陣列1 1 5 a,與第3〜第η-1源極驅動積體 片的暫存器陣列。 第1源極驅動積體電路晶片1 3 0 -1之第1伽瑪 1 1 7a將第2伽瑪校正電壓Vgma2進行緩衝,經由 極驅動積體電路晶片1 3 0 -1的外部電路,將第2缓 伽瑪校正電壓V b - g m a 2,輸出至第1源極驅動積體 片1 3 0 -1的暫存器陣列1 1 5 a,與第η源極驅動積體 片1 3 0-η的暫存器陣列1 1 5 a。另外,第2緩衝後之 正電壓Vb-gma2,輸出至第2源極驅動積體電路晶> 的暫存器陣列1 1 5 a,與第3〜第η-1源極驅動積體 片的暫存器陣列。 接著,第1源極驅動積體電路晶片1 3 0 -1之第 缓衝器1 1 7a將第3伽瑪校正電壓Vgma3進行緩衝 第1源極驅動積體電路晶片1 3 0 -1的外部電路’將 衝後之伽瑪校正電壓Vb-gma3,輸出至第1源極驅 電路晶片1 3 0 -1的暫存器陣列1 1 5 a,與第η源極驅 電路晶片1 3 Ο -η的暫存器陣歹|J 1 1 5 a。另外,第3缓 伽瑪校正電壓V b - g m a 3,輸出至第2源極驅動積體 片130-2的暫存器陣列115a,與第3〜第n-1源極 體電路晶片的暫存器陣列。 第 2源極驅動積體電路晶片1 3 0 - 2的暫存 1 1 5 a,係從第1源極驅動積體電路晶片1 3 0 -1的第 緩衝器1 1 7 a輸入第2緩衝後之伽瑪校正電壓V b- | 130-2 電路晶 緩衝器 第1源 衝後之 電路晶 電路晶 伽瑪校 ί 130-2 電路晶 2伽瑪 ,經由 第3緩 動積體 動積體 衝後之 電路晶 驅動積 器陣列 1仂口瑪 gma2, 22 1278688 從第1源極驅動積體電路晶片1 3 Ο -1之第2伽瑪缓衝器 117b輸入第3緩衝後之伽瑪校正電壓Vb-gma3,從第η 源極驅動積體電路晶片1 30-η之第1伽瑪緩衝器1 17a 輸 入第1緩衝後之伽瑪校正電壓V b - g m a 1。相同的,未圖示 之第3〜第η -1源極驅動積體電路晶片之暫存器陣列亦與 第2源極驅動積體電路晶片130-2的暫存器陣列115a相 同的,輸入第1、第2以及第3緩衝後之伽瑪校正電壓 Vb-gmal、Vb.gma2、Vb_gma3。第1緩衝後之伽瑪校正電 壓V b - g m a 1 ’係緩衝後之另一伽瑪校正電壓,第2與第3 緩衝後之伽瑪校正電壓Vb_gma2、Vb-gma3係緩衝後之自 我伽瑪校正電壓。 依此,第1〜第 η源極驅動積體電路晶片1 3 0 -1〜 1 3 0 - η的暫存器陣列π 5 a,係利用第1、第2以及第3緩 衝後之伽瑪校正電壓 Vb-gmal、Vb-gma2、Vb-gma3,將 分配伽瑪電壓並列的供給至開關陣列部1 1 5b。輸出 D/A 轉換器115如為n位元輸出d/Α轉換器時,將有2n個的 分配伽瑪電壓並列的供給至開關陣列部1 1 5 b。此時,從 第1源極驅動積體電路晶片1 3 0-1輸出之分配伽瑪電壓 V0〜V63與從第n源極驅動積體電路晶片13〇-11輸出之分 配伽瑪電壓V 0〜V 6 3相同。另外,從第2〜第η -1源極驅 動積體電路晶片輸出之分配伽瑪電壓亦相同。 開關陣列部115b的開關陣列115b-l〜115b-n,依2 線閂鎖1 1 4輸入之數位資料信號,從暫存器陣列1 1 5 a輸 入之伽瑪電壓V0〜V63之中,選擇其一分配電壓,亦即 23 1278688 類比資料信號,分別向輸出驅動電路 1 1 6的輸出緩衝器 116-1〜116-n輸出。接著,輸出緩衝器116-1〜116-n向 LCD 面板 500輸出分配伽瑪電壓之驅動電壓 OUT1〜 0 U Τ η,驅動L C D面板5 0 0的源極線。 另一方面,第1圖、第2圖、第3圖以及第4圖所示 習知之源極驅動系統之一例中,將伽瑪緩衝部内藏於個別 的源極驅動積體電路晶片時,對於一伽瑪校正電壓,利用 複數個源極驅動積體電路晶片中之每一個別的伽瑪緩衝 器,因伽瑪緩衝器個別的特性不一致,所以即使從伽瑪校 正電壓產生部輸入相同的伽瑪校正電壓,伽瑪缓衝器個別 的輸出端之間還是會產生些許的電壓偏差,因個別源極驅 動積體電路晶片之間產生驅動電壓的偏差’因此產生嚴重 的晝質不佳的問題。本發明之源極驅動系統,對於一特定 伽瑪校正電壓,利用一特定伽瑪緩衝器,避免源極驅動積 體電路晶片之間產生驅動電壓偏差,以改善晝質不佳的問 題。 上述之為了解決因驅動電壓偏差造成晝質不佳問題 而提案的習知之源極驅動系統之第5圖、第6圖、第7圖 以及第9圖中所示之習知之源極驅動系統之另一例,以另 外的零件構成包含複數個伽瑪緩衝器之伽瑪緩衝部,分別 包含於複數的源極驅動積體電路晶片外部,雖然改善了晝 質不佳的問題,但使用另外的零件時,將會產生組裝製程 的階段增多、不良率增加、成本提高等的問題。本發明之 源極驅動系統中,將包含複數個伽瑪緩衝器之伽瑪緩衝部 24 1278688 内藏於源極驅動積體電路晶片中,減少了 L C D面板的零 件數目。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作各種之更動與潤飾。 如以上所述,本發明係利用一伽瑪緩衝器來對應一特 定伽瑪校正電壓,避免源極驅動積體電路晶片之間產生驅 動電壓偏差,以改善晝質不佳的問題。另外,將包含複數 個伽瑪緩衝器之伽瑪緩衝部内藏於源極驅動積體電路晶 片中,以減少LCD模組的零件數目。 【圖式簡單說明】 第1圖係例舉一習知之LCD模組方塊示意圖; 第2圖係第1圖所示之LCD模組之源極驅動積體電 路晶片不意圖, 第3圖係第2圖所示之源極驅動積體電路晶片的電壓 輸出部之詳細電路圖; 第4圖係第1圖之伽瑪校正電壓產生部與一源極驅動 系統之連接關係詳細電路圖; 第5圖係例舉另一習知之LCD模組示意圖; 第6圖係第5圖所示之L C D模組之源極驅動積體電 路晶片不意圖, 第7圖係第6圖所示之源極驅動積體電路晶片的電壓 輸出部之詳細電路圖; 25 1278688 第8圖係第5圖之伽瑪校正電壓產生部與另一源極驅 動系統之連接關係詳細電路圖; 第 9圖係本發明之源極驅動系統之一較佳應用實施 例之LCD模組; 第10圖係第9圖所示之LCD模組中,本發明之一較 佳實施例之源極驅動積體電路晶片之詳細電路圖;Corresponding to the switch array 1 1 5b-1~1 1 5b-n - the corresponding one, the output drive circuit 1 16 includes a plurality of buffers 1 1 6-1~1 1 6-n, and the switch array 115b- The analog data signals of the l~115b-n input are converted into driving voltages OUT1 to OUTn, and are output to the source line of the LCD panel 500. Hereinafter, referring to the preferred embodiment of FIG. 2, the connection relationship of the source driving system 130 will be described, and the first source driving integrated circuit wafer 1 3 0 -1 and the nth source driving integrated circuit chip will be described. The connection relationship between 1 3 0 - η is taken as an example. For convenience of explanation, the control unit 1 of FIG. 10 is not shown in FIG. 12, and the shift register 1 1 2, the data register 1 1 3 and the 2 line latch 1 1 4 ' are actually They are respectively disposed in the first, second, ..., η source drive integrated circuit 20 1278688 wafers 130-1 to 130·n. The gamma correction voltage generating unit 2 3 0 of the source driving system 1 390 distributes the first and second input voltages Vin1 and Vin2 transmitted from the power supply unit 220 via the gamma correction impedances R 1 , R2 , R3 , and R4 . After the voltage, the first, second, and third gamma correction voltages Vgmal, Vgma2, and Vgma3 are output. This preferred embodiment is illustrated with four gamma correction impedances, but the number of gamma correction impedances can also be increased or decreased. At this time, the first and second gamma correction voltages V g m a 1 , V g m a 2 , V g m a 3 are input to the source drive integrated circuit wafers 1 3 0 -1 to 13 0-n, respectively. That is, the first gamma correction voltage Vgmal is input to the first gamma buffer 1 1 7a of the gamma buffer portion 1 3 7 of the n-th source-drive integrated circuit wafer 1 3 0 -n, and the second gamma correction The voltage Vgma2 is input to the first gamma buffer 1 1 7a of the gamma buffer unit 1 3 7 of the first source drive driving integrated circuit wafer 1 3 0 -1, and the third gamma correction voltage Vgma3 is input to the first source. The second gamma buffer 1 1 7b of the gamma buffer portion 1 3 7 of the integrated circuit chip 1 3 0 -1 is driven. The first gamma correction voltage V gma 1 described above is another gamma correction voltage, and the second and third gamma correction voltages Vgma2 and Vgma3 are self gamma correction voltages. The first gamma correction voltage Vgmal of the n-th source driving integrated circuit chip 1 3 0-n buffers the first gamma correction voltage Vgmal, and drives the integrated circuit wafer 1 3 0-η via the nth source. The external circuit outputs the gamma correction voltage Vb-gmal after the first buffer to the register array 1 1 5 a of the first source drive integrated circuit chip 1 3 0 -1, and the nth source drive The register array 1 1 5 a of the integrated circuit chip 1 3 0 - η. In addition, the gamma correction 21 1278688 positive voltage Vb-gmal after the first buffer is output to the second source driving integrated circuit crystal > the register array 1 1 5 a, and the 3rd to n-1th sources A register array of pole drive integrated sheets. The first gamma correction circuit Vgma2 of the first source-drive integrated circuit wafer 1 3 0 -1 buffers the second gamma correction voltage Vgma2 and drives the external circuit of the integrated circuit chip 1 3 0 -1 via the pole. The second slow gamma correction voltage V b - gma 2 is output to the register array 1 1 5 a of the first source driving integrated body sheet 1 3 0 -1, and the nth source driving integrated body sheet 1 3 0 -n register array 1 1 5 a. Further, the positive voltage Vb-gma2 after the second buffer is output to the register array 1 1 5 a of the second source drive integrated circuit crystal > and the third to n-1th source drive integrated sheets The array of scratchpads. Next, the first buffer 1 1 7a of the first source-driven integrated circuit wafer 1 3 0 -1 buffers the third gamma correction voltage Vgma3 to the outside of the first source-driven integrated circuit wafer 1 3 0 -1 The circuit 'outputs the washed gamma correction voltage Vb-gma3 to the register array 1 1 5 a of the first source driver circuit chip 1 3 0 -1, and the nth source driver circuit chip 1 3 Ο - η's register array | J 1 1 5 a. Further, the third slow gamma correction voltage V b - gma 3 is output to the register array 115a of the second source drive integrated product sheet 130-2, and the third to n-1th source body circuit wafers are temporarily suspended. Array of registers. The second source-drive integrated circuit wafer 1 3 0 - 2 is temporarily stored in the first buffer 1 1 7 a from the first source-driven integrated circuit wafer 1 3 0 -1 After the gamma correction voltage V b- | 130-2 circuit crystal buffer after the first source of the circuit crystal circuit gamma ί 130-2 circuit crystal 2 gamma, via the third easing complex After the rushed circuit crystal driver array 1 仂 g gma2, 22 1278688 gamma correction after the third buffer is input from the second gamma buffer 117b of the first source driving integrated circuit chip 1 3 Ο -1 The voltage Vb-gma3 inputs the first buffered gamma correction voltage V b - gma 1 from the first gamma buffer 1 17a of the n-th source driving integrated circuit chip 1 30-n. Similarly, the register array of the third to n-th source driving circuit chips (not shown) is the same as the register array 115a of the second source driving integrated circuit chip 130-2. The gamma correction voltages Vb-gmal, Vb.gma2, and Vb_gma3 after the first, second, and third buffers. The gamma correction voltage V b - gma 1 ' after the first buffer is another gamma correction voltage after buffering, and the gamma correction voltages Vb_gma2 and Vb-gma3 after the second and third buffers are buffered self gamma Correct the voltage. Accordingly, the first to nth source-driven integrated circuit wafers 1 3 0 -1 to 1 3 0 - η are stored in the register array π 5 a by the first, second, and third buffered gamma. The correction voltages Vb-gmal, Vb-gma2, and Vb-gma3 are supplied to the switch array unit 1 1 5b in parallel with the distributed gamma voltage. When the output D/A converter 115 is an n-bit output d/Α converter, 2n of the distributed gamma voltages are supplied in parallel to the switch array unit 1 1 5 b. At this time, the distributed gamma voltages V0 to V63 outputted from the first source-driven integrated circuit wafer 1 3 0-1 and the distributed gamma voltage V 0 outputted from the n-th source-driven integrated circuit wafer 13〇-11 are output. ~V 6 3 is the same. Further, the distribution gamma voltages outputted from the second to nth -1st source driving integrated circuit chips are also the same. The switch arrays 115b-1 to 115b-n of the switch array portion 115b are selected from the gamma voltages V0 to V63 input from the register array 1 1 5 a according to the digital data signals input from the 2-wire latch 1 1 4 A distribution voltage, that is, a 23 1278688 analog data signal, is output to the output buffers 116-1 to 116-n of the output drive circuit 1 16 , respectively. Next, the output buffers 116-1 to 116-n output the driving voltages OUT1 to 0 U Τ η for distributing the gamma voltage to the LCD panel 500, and drive the source lines of the L C D panel 500. On the other hand, in an example of the conventional source driving system shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, when the gamma buffer portion is built in an individual source-driven integrated circuit chip, a gamma correction voltage, using a plurality of sources to drive each individual gamma buffer in the integrated circuit chip, since the individual characteristics of the gamma buffer are inconsistent, even if the same gamma is input from the gamma correction voltage generating portion The correction voltage, a slight voltage deviation between the individual output terminals of the gamma buffer, due to the deviation of the driving voltage generated between the individual source driving integrated circuit chips, thus causing serious problem of poor quality. . The source driving system of the present invention utilizes a specific gamma buffer for a specific gamma correction voltage to avoid a driving voltage deviation between the source driving integrated circuit wafers to improve the problem of poor quality. The above-described source drive system of the conventional source drive system is proposed in the fifth, sixth, seventh, and ninth embodiments of the conventional source drive system proposed to solve the problem of poor quality of the drive voltage. In another example, a gamma buffer portion including a plurality of gamma buffers is formed by another component, which is respectively included outside the plurality of source-driven integrated circuit chips, and although the problem of poor quality is improved, additional parts are used. At the time, there will be problems such as an increase in the number of stages of the assembly process, an increase in the defective rate, and an increase in cost. In the source driving system of the present invention, the gamma buffer portion 24 1278688 including a plurality of gamma buffers is built in the source driving integrated circuit chip, and the number of parts of the L C D panel is reduced. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. As described above, the present invention utilizes a gamma buffer to correspond to a specific gamma correction voltage to avoid a drive voltage deviation between the source drive integrated circuit wafers to improve the problem of poor quality. In addition, a gamma buffer portion including a plurality of gamma buffers is built in the source driver integrated circuit chip to reduce the number of parts of the LCD module. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional LCD module; FIG. 2 is a schematic diagram of the source driving circuit of the LCD module shown in FIG. 1 , FIG. 2 is a detailed circuit diagram of the voltage output portion of the source-driven integrated circuit chip shown in FIG. 2; FIG. 4 is a detailed circuit diagram of the connection relationship between the gamma correction voltage generating portion and a source driving system of FIG. 1; A schematic diagram of another conventional LCD module is illustrated; FIG. 6 is a schematic diagram of the source driving integrated circuit of the LCD module shown in FIG. 5, and FIG. 7 is a source driving integrated body shown in FIG. Detailed circuit diagram of the voltage output portion of the circuit chip; 25 1278688 Fig. 8 is a detailed circuit diagram of the connection relationship between the gamma correction voltage generating portion and the other source driving system of Fig. 5; Fig. 9 is the source driving system of the present invention An LCD module of a preferred application embodiment; FIG. 10 is a detailed circuit diagram of a source driving integrated circuit chip in a preferred embodiment of the present invention;

第1 1圖係第1 0圖所示之源極驅動積體電路晶片的電 壓輸出部之詳細電路圖;以及 第1 2圖係第9圖所示之伽瑪校正電壓產生部與本發 明之較佳實施例之源極驅動系統的連接關係示意圖。 【主要元件符號說明】 1 0 0源極驅動系統 Π 0 · 1〜1 1 0 - η源極驅動積體電路晶片 1 1 1控制部 1 1 2移位暫存器 Π 3資料暫存器 1 1 4 2線閂鎖Fig. 1 is a detailed circuit diagram of a voltage output portion of the source drive integrated circuit wafer shown in Fig. 10; and a gamma correction voltage generating portion shown in Fig. 12 and Fig. 9 is compared with the present invention. Schematic diagram of the connection relationship of the source drive system of the preferred embodiment. [Main component symbol description] 1 0 0 source drive system Π 0 · 1~1 1 0 - η source drive integrated circuit chip 1 1 1 control unit 1 1 2 shift register Π 3 data register 1 1 4 2-wire latch

115輸出D/A轉換器 116輸出驅動電路 1 1 7伽瑪緩衝部 1 1 8電壓輸出部 2 0 0源極電路方塊 2 1 0時序控制部 2 2 0電源部 2 3 0伽瑪校正電壓產生部 3 0 0閘極驅動系統 3 00- 1〜300-m閘極驅動積體電路晶片 4 0 0閘極電路方塊 26 1278688 5 00 LCD面板 1 2 0源極驅動系統 120-1〜120-n源極驅動積體電路晶片 1 2 7伽瑪緩衝部 1 2 8電壓輸出部 1 3 0源極驅動電路115 output D/A converter 116 output drive circuit 1 1 7 gamma buffer unit 1 1 8 voltage output unit 2 0 source circuit block 2 1 0 timing control unit 2 2 power supply unit 2 3 0 gamma correction voltage generation Part 3 0 gate drive system 3 00- 1~300-m gate drive integrated circuit chip 4 0 0 gate circuit block 26 1278688 5 00 LCD panel 1 2 0 source drive system 120-1~120-n Source drive integrated circuit chip 1 2 7 gamma buffer 1 2 8 voltage output 1 3 0 source drive circuit

1 3 0 -1〜1 3 0 - η源極驅動積體電路晶片 1 3 7伽瑪緩衝部 1 3 8電壓輸出部 115輸出D/A轉換器 1 1 5 a暫存器陣列 11 5 b開關陣列部 1 1 6輸出驅動電路1 3 0 -1 to 1 3 0 - η source drive integrated circuit chip 1 3 7 gamma buffer unit 1 3 8 voltage output unit 115 output D/A converter 1 1 5 a register array 11 5 b switch Array unit 1 16 output drive circuit

2727

Claims (1)

1278688 拾、申請專利範圍: 1 . 一種 L C D (液晶顯示器)模組之源極驅動積體電 路,其係位於一源極驅動積體電路晶片中,該源極驅動積 體電路晶片至少包含一電壓輸出部,以輸出驅動LCD面 板源極線之驅動電壓,其中 該電壓輸出部至少包含: 一伽瑪缓衝部,係將自伽瑪校正電壓產生部一側 輸入之自我伽瑪校正電壓進行缓衝,將緩衝後之自我 伽瑪校正電壓輸出至該源極驅動積體電路晶片外部; 一輸出 D/A (數位/類比)轉換器,係藉由該源 極驅動積體電路片外部輸入之緩衝後之另一伽瑪校 正電壓,與該緩衝後之自我伽瑪校正電壓,將資料暫 存器輸入之數位資料信號變換為類比資料信號,其中 該缓衝後之另一伽瑪校正電壓,係該當於從該伽瑪校 正電壓產生部另一側輸出之另一伽瑪校正電壓;以及 一輸出驅動電路,係將該輸出D / A轉換器輸入之 類比資料信號變換為驅動該L C D面板源極線之驅動 電壓,並將其輸出。 2.如申請專利範圍第1項所述之L C D模組之源極驅動 積體電路,其中該伽瑪缓衝器係至少包含一個以上之伽瑪 緩衝器。 3 .如申請專利範圍第1項所述之L C D模組之源極驅動 28 1278688 積體電路,其中該輸出D/A轉換器至少包含: 一暫存器陣列,係將該緩衝後之自我伽瑪校正電壓, 與緩衝後之另一伽瑪校正電壓,藉由分配阻抗分配電壓, 輸出分配伽瑪電壓;以及 一開關陣列部,係至少包含一開關陣列,用以將該分 配伽瑪電壓輸入,切換開關,使該數位資料信號變換為該 類比資料信號。 4 ·如申請專利範圍第3項所述之L C D模組之源極驅動 積體電路,其中該輸出驅動電路係至少包含與開關陣列一 對一相對應的複數個輸出缓衝器,將該開關陣列輸入之類 比資料信號變換為該驅動電壓,並將其輸出。1278688 Pickup, patent application scope: 1. A source driving integrated circuit of an LCD (Liquid Crystal Display) module, which is located in a source driving integrated circuit chip, the source driving integrated circuit chip contains at least one voltage The output unit outputs a driving voltage for driving the source line of the LCD panel, wherein the voltage output unit includes at least: a gamma buffer portion for slowing the self-gamma correction voltage input from the gamma correction voltage generating unit side And outputting the buffered self-gamma correction voltage to the outside of the source driving integrated circuit chip; an output D/A (digital/analog ratio) converter driving the external input of the integrated circuit chip by the source The buffered another gamma correction voltage, and the buffered self-gamma correction voltage, converts the digital data signal input from the data register into an analog data signal, wherein the buffered another gamma correction voltage, Is another gamma correction voltage outputted from the other side of the gamma correction voltage generating portion; and an output driving circuit for inputting the output D/A converter or the like The specific data signal is converted into a driving voltage for driving the source line of the L C D panel, and is output. 2. The source drive integrated circuit of the L C D module of claim 1, wherein the gamma buffer comprises at least one gamma buffer. 3. The source drive 28 1278688 integrated circuit of the LCD module according to claim 1, wherein the output D/A converter comprises at least: a register array, and the buffered self-gamma a Ma calibration voltage, and another buffered gamma correction voltage, by distributing an impedance distribution voltage, outputting a distribution gamma voltage; and a switch array portion including at least one switch array for inputting the distributed gamma voltage And switching the switch to convert the digital data signal into the analog data signal. 4. The source driving integrated circuit of the LCD module according to claim 3, wherein the output driving circuit comprises at least a plurality of output buffers corresponding to one-to-one corresponding to the switch array, the switch The analog data signal of the array input is converted into the driving voltage and output. 5 . —種 L C D模組之源極驅動積體電路之源極驅動系 統,係至少包含具有相同内部構造之一第1源極驅動積體 電路晶片,以及一第2源極驅動積體電路晶片》其中 該第1源極驅動積體電路晶片至少包含: 一伽瑪緩衝部,係將伽瑪校正電壓產生部一側輸 入之自我伽瑪校正電壓進行緩衝,將緩衝之自我伽瑪 校正電壓輸出該第1源極驅動積體電路晶片外部; 一輸出D/A轉換器,係藉由該第1源極驅動積體 電路晶片外部輸入之緩衝後之另一伽瑪校正電壓,與 該緩衝後之自我伽瑪校正電壓,將資料暫存器輸入之 數位資料信號變換為類比資料信號,並將其輸出,其 29 1278688 一伽瑪緩衝部,係將該伽瑪校正電壓產生部另一 側輸出之另一伽瑪校正電壓進行緩衝,將缓衝後之另 一伽瑪校正電壓輸出至該第1與第2源極驅動積體電 路晶片 ; 一輸出D/A轉換器,係藉由輸入該第1源極驅動 積體電路晶片之緩衝後之自我伽瑪校正電壓,與向該 第 η源極驅動積體電路晶片外部輸出之緩衝後之另 一伽瑪校正電壓,將資料暫存器輸入之數位資料信號 變換為類比資料信號,並將其輸出;以及 一電壓輸出部,係包含一輸出驅動電路,將該輸 出 D/A轉換器輸入之類比資料信號變換為驅動該 LCD面板源極線之驅動電壓,並將其輸出;以及 該第2源極驅動積體電路晶片至少包含: 一輸出D/A轉換器,係藉由輸入第1源極驅動積 體電路晶片之緩衝後之自我伽瑪校正電壓,與該第η 源極驅動積體電路晶片之緩衝後之另一伽瑪校正電 壓,將資料暫存器輸入之數位資料信號變換為類比資 料信號,並將其輸出;以及 一電壓輸出部,係包含一輸出驅動電路,將該輸 出 D/A轉換器輸入之類比資料信號變換為驅動該 L C D面板源極線之驅動電壓,並將其輸出。 9.如申請專利範圍第8項所述之L C D模組之源極驅動 積體電路之源極驅動系統,其中該第2源極驅動積體電路 32 1278688 源極驅動積體電路晶片。 晶片,係至少包含一個之第2The source driving system of the source driving integrated circuit of the LCD module comprises at least one of the first source driving integrated circuit chip having the same internal structure, and a second source driving integrated circuit chip. The first source-driven integrated circuit chip includes at least: a gamma buffer portion that buffers a self-gamma correction voltage input from a side of the gamma correction voltage generating unit, and outputs a buffered self-gamma correction voltage The first source drives the outside of the integrated circuit chip; and an output D/A converter drives the other gamma correction voltage input from the external input of the integrated circuit chip by the first source, and after the buffering The self-gamma correction voltage converts the digital data signal input from the data register into an analog data signal, and outputs the same, and the 29 1278688-gamma buffer portion outputs the other side of the gamma correction voltage generating unit. The other gamma correction voltage is buffered, and the buffered another gamma correction voltage is output to the first and second source driving integrated circuit chips; an output D/A converter is driven by the input The self-gamma correction voltage after buffering of the first source-driven integrated circuit chip and another gamma correction voltage after buffering output to the outside of the n-th source driving integrated circuit chip, the data register The input digital data signal is converted into an analog data signal and outputted; and a voltage output portion includes an output driving circuit for converting the analog data signal of the output D/A converter input to drive the LCD panel source a driving voltage of the line and outputting the same; and the second source driving integrated circuit chip includes at least: an output D/A converter, which is a self-buffered self by driving the first source to drive the integrated circuit chip a gamma correction voltage, and another gamma correction voltage buffered by the η source driving integrated circuit chip, converting the digital data signal input from the data buffer into an analog data signal, and outputting the same; The voltage output unit includes an output driving circuit, and converts the analog data signal input from the output D/A converter into a driving voltage for driving the source line of the LCD panel, and Output. 9. The source drive system of the source drive integrated circuit of the L C D module according to claim 8, wherein the second source drive integrated circuit 32 1278688 source drives the integrated circuit chip. The wafer, which contains at least one of the second 3333
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