TWI275028B - Floating-point logarithmic calculation device and the method thereof - Google Patents

Abstract

A floating-point logarithmic calculation device is used to obtain a logarithmic calculation result of a floating point X used p as the base. The representation of the floating point X is (-1)Sx*2Ex*Mx, where Mx=(1+fx)=(1+Ax*2-K)+(Bx*2-N). Sx is the symbol number of the floating point. Ex is the exponent of the floating point. Mx is the mantissa of the floating point and 1 <= Mx < 2. fx is the fraction of the N bit. Ax is the number of the most marked K bit in fx. Bx is the number of the least marked (N-K) bit in fx and 0 <= K < N (K and N are natural numbers). The logarithmic operation device comprises a first multiplier, a logarithmic table, a first adder, a divider, a Taylor series operation circuit, a second multiplier and a second adder.

Description

1275028

__ Case No. 9111578R V. INSTRUCTION DESCRIPTION (1) The present invention relates to a method for logarithmic operation. A logarithmic operation method and apparatus for a floating point number. , In the current electronic computer,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, For the index of the Institute of Electrical and Electronics Engineers (Institute of P1. · and Electronic Engin. 〇f Electrical gineers, IEEE) for the floating point number of the dried cattle, four standard formats, the first two minutes - inflammation ... &amp; The table is not "Ding / . · The type Q is a single precise 3 2 bit format (single-precision 32-hit f, 玖 κι blt f〇rmat) and double-bit precise 64-bit format (d〇uble-Precision 6"it f〇〇ia" :::

The stretch format is used to indicate that the operation is the same as the L format representation, and the most important is I ^ . For single-precision 32-bit metrics, and only in order to get the exact 64-bit format representation of the f-floating point number, ^2::m' is used to store the floating-point collection double with double-bit memory space. Double length (D〇ubie Le_) storage, tea, Figure 1 'Figure 1 shows the above single - precise 32 - S · 2ε · Μ. "Going, base 2, floating point number F = (-η where Μ is the mantissa of the floating point number, using 23, E is the floating point number of the text The number of days of the day is represented by the 8-bit 70. The number of the floating number of the helmet number is expressed by 1 bit as the symbol 1275〇28 曰------- Case No. 9111578R No. 5, Invention Description (2) j忐. In the current practice, it is usually used to look up the table ΐ 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对瞀 ",, the number of cakes, seven arithmetic precision problems, an 8-bit logarithm table" has ^, will encounter - =, but use the 8-bit logarithm table to do the floating-point logarithm = quite large The accuracy of the two fruits is still insufficient, because usually one nose has 23 bits. The main purpose of the present invention is to provide a method of setting and calculating the method. 'Used to obtain the result of the calculation with the highest exact sound number. m哎>to the number of points ί To achieve the above object, the present invention provides a floating point The representation of the number of stains X for the pair of numbers used to obtain a floating point number χαρ is (-1)Sx ·2Εχ ·Μχ, where (10) ^, ^ fruit, the Τ of the Τ + (ΒΧ · 2Ν), &amp; is the number of symbols of the floating point number, Ε 2 index, Μχ is the mantissa of the floating point number, and 匕Mxd=number, and is the 4 兀 quantile of the highest κ bit in 匕The value of ΟΜ&lt;Ν and ρ, Κ, ΝΑ - Mickey takes the low position (Ν~Κ) ^ ^ ^ , llog ^ &quot; the number of the reference is multiplied by a round-multiplied result. a multiplier and a logarithmic table for adding the multiplication result to the result = an additive result; a divider 'for receiving the value &amp; and an additive value of 2 Κ + ΑΧ, 1 dividing the value by 2Ηα^2Ν' to output-division result r·-Taylor expansion operation circuit' is used to receive the division result to find the value of two equal to ln(l+Rd), and output the burgeon which is equal to inn+R). '

Z -------

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 5 1275〇28 曰 Amendment-----Case No. 9111573⁄4^ V. Invention Description (3) Second multiplier for calling a W The values are multiplied by the round value and the ''adder, coupled to the first-addition &quot;11^ fruit; and a second and a fourth turtle's I ϋ一一一 multiplier for The phases are added to output a logarithmic operation result γ. On the other hand, the present invention also provides a floating % disk dip, w #七, soil, used to obtain a floating point number X is 5, the logarithm of the number of different methods X is represented by (-1) SX · 2Εχ · Μ , 士 运 运 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The index is 缺, Μχ is the mantissa of the floating point and the second is, “the number of the floating point number is the most significant £= of fx; &lt;2, the fraction of N bits (NK) The least significant method of the value of the bit, 〇$κ&lt;Ν value 4, includes the following steps: a value equal to η Ν 9 is a natural number, and the logarithm operand is multiplied by a J2 in a first multiplier The exponent table of values and floating point numbers receives the value 4 and the lookup table produces two results; the use-of-results are added in a first adder; the multiplication result and the ruler divide the value Bx by a 2K + AX and 24 'j eye addition result, using a division result Rd; using a Taylor expansion equation to calculate the electric value to output - divide a value equal to ln (URd), and I find the value in the result of the subtraction method; First-class W/ln The value of the second round is multiplied by a number 2nd multiplier of 1n (1~) to output a second, symptom 11 (1 + Rd) value in a fruit and a second multiplication result in a second addition The result of the second result; and the result of the addition of the phase Y. The phase of the phase is added to the logarithm of the logarithm. The figure of the second embodiment shows the floating point number of the present invention. As shown in the figure, the pair of floating point numbers and the number arithmetic device Architecture display-丨乘' ----- $6页〇702-7517twf3(3.7) ; 90P131 ; CHEN.ptc 1275028 Revision曰----- 9111578R__年月五,发明说明(4)二一之The number table 120, the first adder 130, the divider 140, the Taylor expansion type transfer circuit 15A, the second multiplier 170, and the second addition cries 16 〇. The logarithmic arithmetic device 100 of the foreign point number is used to obtain a The result of the pairwise operation of the floating point number Xwp ^氐, the representation of the floating point number 为 is (—1 household·two: Λ” χ=(1+ίχ&gt;(1+Αχ ·2-κ)ΚΒχ ·2- Ν) is the number of the number of the floating number, Ex is the index of the floating point number, Μχ is the tail of the floating point number, and the score of 1 SMX, &lt;2, fx bit, Αχ is the highest position in the 匕The κ bit value Βχ is fx The value of the lower (ν-Κ) bit, 〇SK&lt;N and p, K, Ν are natural numbers. The first multiplier η〇 receives a value equal to 1〇gp2 and an exponent Ex of the floating point number, After multiplying the two, the multiplication result L is output. The logarithm table = 〇 receives the value Ax and the lookup table produces the result logp (1 + Αχ · 2 - κ) output. The first addition is 1 3 0 connected to the first multiplier 1 〇〇 and the logarithm table 1 2 〇, for the 1 multiplication result 11 and the result 1 〇gp, (1 + Αχ · 2_κ) are added to output a sum The result is 匕. The divider 140 receives the value βχ and an added value of 2Κ + ΑΧ, and divides the value by the 2Κ + ΑΧ and 2N-K to output a division result Rd. The Taylor expansion operation circuit 150 is coupled to the divider 140 for receiving the division result to find a value equal to ln(l+Rd) and outputting the value equal to ln(1 + Rd). The second multiplier 170 multiplies a value equal to ι/ιη(ρ) by the value equal to ln(l+Rd) to output a second multiplication result %. The second adder 160 is connected to the first adder 130 and the second multiplier 17A for adding the addition result Ra and the second multiplication result to output the representation of the floating point number X of the logarithm operation result. It is: X=(-1)SX · 2Ex · Mx (1) where Mx = (l + fx) = (l+Ax · 2-k) + (Bx · π), Sx is the number of symbols,

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc 1275028 —-----room statement 91115786 five 'invention description (5)^ ' ·-~, -1曰 __

Ex is the exponent, Mx is the mantissa and 1 is the value of the highest K bit in fx, and the second '&lt;2 is the fraction of N bits, A ' value, smashed and p, K, : is self-B It is wide. The lowest position in the middle (...the logarithm of the floating point number of the present invention) owes the tubular value of the p-based logarithm operation γ : disguise, used to obtain the floating point numberχ

Log2 logp X =1^,(2^)4-bgP: μΛ 2^) fi4;4 2;%λ ¢2)

- I l +,;:'2々~一 :£, · (2 ) + log^ (i +.4jt. 2*^ ]+ idllii] 'Hp) B, 1 + Ακ 2#

In order to obtain the logarithm operation result γ, first, an exponent 等于 equal to 1 〇 g value and a floating point number is multiplied in the first multiplier 110 to output p - y multiplied result Rml. The value Ax is sent to the logarithmic table 120 and the lookup table produces the result 1〇gP (1 + Ax · 2 κ) output. Next, the multiplication result ^ and the result} are exhausted (1 + Ax · 2 κ) and added to the first adder j 3 〇 to output the addition result &amp; and the divider 140 is used to divide the value by one phase. Add the value 2Κ + ΑΧ and 2Ν_Κ to ^ to divide the result Rd. Next, the result of the division is sent to the Taylor expansion operation circuit 150 to find a value equal to in(i + Rd), and a value equal to 1 η (1 + Rd) is output. A value equal to 1 / 1 n ( p) and equal to 丨 n (丨 + heart)

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 8 1275028

The f 3 diagram shows the logarithmic arithmetic device of the floating point number of the first embodiment of the present invention = a schematic diagram of the architecture. The floating-point logarithm computing device 20 0 includes a first multiplication method of 2 1 0, a logarithmic table 2 2 〇, a first adder 2 3 〇, a divider 2 4 0, a Taylor expansion-type transfer circuit 250, and a second adder. 260 and fixed pattern circuit 270. The logarithmic arithmetic device 2 of the floating point number is used to obtain a pair of numerical operation results in which a floating point number X is a natural number. Floating point number X is a floating point number in a single precision 32-bit format specified by the Institute of Electrical and Electronics Engineers (IEEE). It has 32 bits and is divided into XS1, X3Q, ..., XG. And since the floating point number X is larger than zero, the symbol number Sx (bit X31) of the floating point number must be zero. Therefore, the floating point number X can be expressed as 2 Εχ · Mx, and the exponent Ex of the floating point number has 8 bits, respectively X3Q, χ29..... Χ23 'The mantissa of the floating point number Μχ is expressed as (1 + fx ), and fχ has 2 3 bits, respectively Χ22, Χ2ι.....XG, fx will be divided into two parts #AX and Bx, Ax is

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 9 1275028 Case No. 91115786 V. Description of invention (7) The value of the highest octet in fx, 1 is the value of the lowest 15 bits in 4 That is, Ax is the value of &amp; 2115, and Βχ is the value of &amp;~&amp;. The first multiplication method is 21 〇 reception—the value equal to 1 n 2 and the exponent X of the floating point number, and the two are multiplied to output a multiplication result L. The logarithmic table 22 receives the value ^f and the lookup table produces the result ln(UAx · 2-8) output. The first adder 23 is connected = to the first multiplier 20 0 and the logarithm table 220 for adding the multiplication result t and the knot = (1 + AX · 2_Μ to output an addition result &amp; divider. 24〇 receives the value Bx and an added value of 28 + Ax, and divides the value by the 28 + a and 215 to output a division result &amp; Taylor expansion operation circuit 25 to the divider 240 for The division result is received to find a value equal to in, and the output is equal to 1 η (1 + Μ value. The second addition cry 260 is connected to the first adder 23 〇 and the Taylor expansion operation circuit 25 〇 to phase The addition result Ra and the values of the Kln(1+Rd) are added to the logarithm operation result Y. In this embodiment, the logarithm of the floating point number has been set: 20 0 includes the fixed pattern circuit 27(), fixed The type circuit 2 ^ clothing logarithm operation result Y and the logarithm operation result γ is expressed as (-丨) s to receive

My, where Sy is the number of symbols, Ey is the index, My is the mantissa, and 1 $%. The logarithmic arithmetic device 2 of the floating point number of this embodiment is used for ^&lt;~two points X to be based on natural numbers The logarithmic operation result γ : X is floating 41 Υ = 1η(Χ)

1275028 -----Case number V. Invention description (8) 91115786

ί*·Α^Τ^ 1. For - 黾蝶.咖也·2, 十岛2;] 黑·Ιη(2)牟· 24 )++ 马) m 其申~ hx U-Ax in order to find the logarithm The operation result γ, first, multiplies an exponent 丨 equal to the value of 丨n2 and the floating point number by the first multiplier 2 1 以 to output a multiplication result L. The value Αχ is sent to the logarithmic table 220 and the lookup table produces the result 1 = (1 + ΑΧ · 2-8) output. Next, the multiplication result Rmi and the result 1n (1 + Αχ · 2 - 8 ) are added together in a first adder 23 输出 to output an addition result ^. For reuse, the ruler 240 divides the value Bx by 28 + Ax and 215 to output the division result Rd. The division result Rd is then sent to the Taylor expansion operation circuit Mo to find a value of p equal to ln(l + Rd), and the value of Kln(1 + Rd) is output. Finally, the addition result Ra and the value equal to ln(1+Rd) are added to the second adder 220 to output the logarithm operation result γ. Fig. 4 is a block diagram showing an example of a Taylor expansion type operation circuit in Fig. 3. The Taylor expansion operation circuit 25 0 is a pre-established circuit which uses a three-time Taylor approximation to find the value equal to 111 (1 + 匕). As shown in the figure, the Taylor expansion expansion circuit 250 includes three multipliers 252a to 252c, a subtraction device 254, and an adder 256. The approximation of the value equal to ln(l+Rd) is:

Page 11 1275028 Amendment (4) Case No. 9111578^ V. Description of invention (9) ln Cl+ Rd: 3 2 3 Multiplication state 2 5 2 a Receive the input of two division results and rotate the first-order value. Then 'the value equal to Rd2 is shifted to the right _ bit to obtain a value equal to Rd2/2 and a division result 匕 is sent to the subtraction means 254. In addition, a division result Rd and a value equal to 1/3 are sent. Multiplying into the multiplier 25 2b and outputting a value equal to Rd/3, which is equal to

The value of Rd/3 and the value equal to 1^2 are sent to the multiplier 2 52. The middle phase outputs a value equal to Rd3/3. The adder 256 is connected to the multiplication crying/subtracting device 2 5 4, and receives the rounds from the class, the total crying 9 r; 9 r 0, 士, | 屮 face 丄 茱 25 25 25C and the subtraction device 254 The value output equal to ln(1+Rd) is obtained after the addition. Figure 5 shows the floating point of the second embodiment of the present invention.

Schematic diagram of &amp; The logarithmic arithmetic device of the floating point number = J 32 〇, the brother-adder 3 3 0, the divider 34 〇, the Taylor = number table 350, and the second adder 36. And the multiplier 37〇. 'The logarithmic operation device of the open-circuit different circuit number is used to obtain the one-to-one operation result of the -% bottom." The number of points X is the single-precision 32-bit specified by the power C with 2 as the association UEEE. The floating-point number of the meta-format electric and electronic engineer 32-bU f〇rmat), i and 32 兀, for others X31, χ30,···, χ〇, and because 八/, with floating point The number of symbols Sx (bit Χ 31) must be zero U U at zero

Can be expressed as 2Εχ · Μ , , , main wt rainbow This 'float number X

X, 22 ’ 21 ···, X°, fx will be divided into two parts Ax and 2 9 bits

0702-7517twf3(3.7);90Pl31; CHEN. Page 12 takes v soap, the index of the number of stains Ex has 8 bits, and 23, the mantissa of the floating point number is expressed as (丨2 30. respectively Yuan Hao χ V 'And χ χ 1275028 曰 Amendment _ Case No. 91115786 V. Invention Description (10) The value of the bit, that is, Αχ is the value of X22~Xi5, Βχ is the fork... 14 ' Αχ is the highest bit of 8 bits in fx Value, 1 is the lowest of the 匕 15 logarithm table 3 2 0 receiving the value Αχ and check the table production + gentleman ] 2-8) output. The first adder 3 3 0 receives the index of the floating point number Εχ § 2 and the knot + fruit 1 〇 g2 (1 + Αχ · 2-8), adds the two and outputs an additive result 匕. The divider 340 receives the value 匕 and the added value 2ΗΑχ, and divides the value &amp; by 2 + Αχ and 2 to output a division result 匕. The Taylor expansion operation circuit 3 $ 〇 is connected to the division method 3 4 0 for receiving the result of the division to find a value equal to ln(l+Rd), and outputting the value equal to 丨+^). The multiplier 3 70 multiplies a value equal to ι/ιη(2) by the value equal to ln(1+Rd) to output a second multiplication result U. The second adder 3 6 〇 is connected to the _th adder 3 3 0 and the multiplier 3 7 〇 for adding the addition result 匕 and the second multiplication result Rw to output the logarithm operation result γ. The logarithmic arithmetic device 300 of the floating point number of the present embodiment is used for obtaining the logarithmic operation of the floating point number X based on the base 2 纟 ·· Y - 1 〇g2 ( X) = bg plus + ' + Bx twenty two. j ^〇g 2(2^ j+1〇g3| (j+ A,, -2^). L A (four) + l〇g small γ

By . (4) h( 2) _

-B

Bx · 2 1 + Av . To obtain the logarithm operation result γ, first, the value Ax is sent to the logarithm table 3 2 0 and the lookup table produces the result l〇g2 (1+Ax · 2-8) output. then

0702-7517twf3(3.7) ; 90P131 ; CHEN •Ptc Page 13 1275028 Correction 曰-----_ Case No. 91115786 V. Description of invention (11) = Mesh multiplication, fruit Rml and result i 0g2 (1 + Αχ · 2-8) In a first adder 3 3 〇, to round up the addition result Ra. The divider I is used to divide the value I by the sum π of Α矣J to output the division result 1^. Next, the division result Rd is adapted to the equation circuit 3 50 to find a value equal to in(i+Rd) equal to the value of ln(1 + Rd). The value of -Cd) equal to &quot;In(1) is multiplied in multiplier 370 to output - Ϊ; 3 hearts. Finally, the result R is added, the second phase is multiplied by 2, and the adder 36&quot; is added to output a logarithm operation result γ. Fig. 6 shows a schematic diagram of the floating point process disclosed in the present invention. The following is a flow chart of the logarithmic operation method of the logarithmic method of the second and third embodiments of Fig. 2 and Fig. 3: What is the floating point number of the present invention? a base number; or ln2 is a logarithmic value of 2 (for example, the index Εχ is - multiplied in the first multiplier, 匕 is the bottom) and the floating point number (1) is S1); in step S2, the pair is used Table: a multiplication result U step out (logp(1+Ax2-K)wn(l; tooth production K-8), and multiplying the phase in the X phase diagram to output an addition result, ( ;;; fruit:, the first-adder S-S2 has no specific order a. This, it should be noted that Βχ divide by - add value 2HAX, to turn out '^ use divider The numerical value uses the Taylor expansion type operation circuit 2', and the result Rd (step S4). Then the ln(l+Rd) value is output. Then, according to the second tooth, the result is Rd, and the floating point number X is obtained. Decide whether to calculate 1 1 and logarithm to the bottom, and then perform step S7, and use the second multiplied J. If yes, no N0", 1/: Ln(p), to output a second phase. ;=(1+Rd) value multiplied by YES,,, then proceed to step S8 ... fruit U corresponds to the second figure);

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 14---- Pissing the second multiplier, directly to 1275028 _ case number 91115786_年月日__ V. Invention description (12) ln(l+ Rd) value output (may also be regarded as outputting the ln(l+Rd) value as a second multiplication result (corresponding to Fig. 3). Finally, the addition result 匕 and the second multiplex result ( The Rm2 or 1 η (1 + Rd ) value is added to the second adder to output a logarithmic operation result Y (step S9). Although the present invention has been disclosed above in the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will be able to make some modifications and refinements without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 15 1275028 _ Case No. 91115786 The following is a detailed description of the above and other objects of the present invention. Figure 1 shows a conventional single accurate 32-bit format diagram. Fig. 2 is a diagram showing the logarithmic operation of the floating point number of the present invention. Schematic diagram of the t-table configuration Fig. 3 is a block diagram showing the structure of the floating-point number of the first embodiment of the present invention. $Number Calculation Figure 4 shows a schematic diagram of the Taylor expansion operation circuit in Fig. 3. Fig. 5 is a schematic diagram showing the construction of a logarithmic arithmetic unit of a floating point number in the second embodiment of the present invention. Fig. 6 is a schematic diagram showing the flow of the logarithmic operation method of the floating point number disclosed in the present invention. Symbol Description: Year Month Day

Example, and with the accompanying; point can be shown, the architecture of the example 1 0 0, 2 0 0, 3 0 0 ~ floating-point logarithm operation device; 110, 210 ~ first multiplier; 1 2 0 , 2 2 0, 3 2 0~ logarithmic table; 130, 230, 330~ first adder; 140, 240, 340~ divider; 150, 250, 350~ Taylor expansion type operation circuit; 1 7 0~ second Multiplier; 254~subtraction device; 370, 252a, 252b, 252c~multiplication p;

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 16 1275028 Case No. 91115786 Correction Simple description 2 5 6~Adder; Second adder 160 &gt; 260 ^ 360 Εχ~Float index

Rml ~ the output of the first multiplier;

The output of Rm2~the second multiplier;

Ra~ the output of the first adder;

Rd~ divider output; K, N~bit number;

The value of the most significant K-bit among the scores of Ax~N bits; and the value of the least significant (N-K) bit among the scores of Bx~N bits

0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 17

Claims (1)

^tE 911157RR,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Mx = (l + fx)=(1 The representation of the number of points X is (-1) :;^&gt;Ex^^L Α*ΓΗ(Βχ *2'Ν) 5Sx^^ End=and l〇x&lt 2, UN bit = exponent, Mx is the width of the floating point: value 'Bx is the lowest bit in fx (Ν^ 乂 is the highest bit of fX in the K bit 2 from, 娄: 'the logarithm operation The value of the package: '〇$K&lt;N and' is 1e H: the mountain is used to multiply a value equal to 1 〇gp2 by the floating point number\ to output a multiplication result; The table is configured to receive the value AX and the look-up table generates a result to be input by the Jiang #f-adder, coupled to the first multiplier and the logarithmic table, multiplied by two, and summed with the result to output An addition result; the division is 'to receive the value Bx and an additive value of 2K + Ax, and divide the value Bx by the added value 2Κ + Αχ and to output a division result &amp;; Taylor An expansion operation circuit for receiving the division result ^ Find a value equal to ln(l+Rd) and output the value equal to ln(1+R); a second multiplier to set a value equal to 1 / 1 n ( p ) and the equal to ln Multiplying the value of (l+Rd) to output a second multiplication result; and a second adder coupled to the first adder and the second multiplier 'for adding the result and the first The two-multiplication results are added to output the logarithm operation result Y. 2 · The logarithmic operation of the floating-point number as described in the first application of the patent scope is im 〇 702-7517twf3 (3.7); 90P131; CHEN.ptc 18th Page 1275028 '申凊专利范围——________ ___, where the first multiplier is not needed when calculating the floating point number χ2. The logarithmic operation result, 3 · If the application of the patent scope is the third item The floating floating point number is calculated by the natural logarithm of 2 logarithmic operations, and the second multiplier is not needed. - The _logarithm operation 4 is as described in item 3 of the patent application scope. The floating point is set, and the logarithmic operation device of the fixed type circuit is further included, and the logarithm operation result γ is expressed as (1) sy · 2 Ε / 弋The operation result is the number of the joints, Ey is the exponent, is the mantissa, and 1 $ My&lt;2. 7 , Sy is the symbol set, where the logarithm of the floating point number described in the ^1 item is loaded with the value A, p is the base logarithm The logarithmic logarithmic table of the transport tube 4 is used to obtain the 6th patent application range, wherein the logarithmic calculation of the floating point number of the Taylor expander is loaded with a three-time Taylor approximation to find a pre-established circuit. The circuit has its advantage of a floating point number; Sx is a pair of 运-based method for obtaining a floating point number Χ Εχ · 2Εχ · Μ , where Μ 、 , , , 口 口 , The representation of the floating point number X is (~1) the number of symbols of the floating point number, XE1+fX): (1 + Ax · 2-Κ) + (Βχ·2-Ν), SX is the mantissa and 1 g Μχ &lt; 2, f ? horse exponent of the floating point number, Mx is the value of the element of the floating point number, Bx X is the fraction of the bit in fx, Ax is the highest bit of k in the fx K, N is a natural number The value of the lower (N - K ) bit, 0 $ K &lt; N and ρ, will be 1 in 1 'cardinal number = method includes the following steps: multiplying in the multiplier by the value and the floating point number Index Ex in a first out Multiplication results; Page 19! 275〇28 Amendment to the number of 9115,786, the patent application scope; use the logarithmic table to receive the value Αχ and look up the table to produce - the result of the transmission - the phase multiplication result and the result in the - the first addition The phase is added to the output and the divider divides the value by an additive value of 2 Κ + ΑΧ to rotate - the equal-expansion operation circuit receives the division result &amp; to find the value,; 'n(l + The value of Rd), and output the value equal to ln(i+Rj - the value of 2 ϋ1 2n(p) and the value equal to 1n(1+Rd) are multiplied in the same way to output one a second multiplication result; and the 4th addition result and the second multiplication result are in a second. The logarithm operation result γ is outputted. The dephasing middle phase method, the logarithmic operation of the floating point number described in the term When the result of the logarithmic operation is not required, the second multiplier is not required when the result of the logarithmic operation is the result of the logarithmic operation. The logarithm of the logarithm is not required. The floating point described in the item, 'more includes the steps of using a fixed type circuit, the d number operator: The type circuit receives the logarithm operation result γ and expresses the logarithm as (-1P · 2Ey · My, where is the number of symbols ^ two results Y is a mantissa and 1 - My &lt; 2. y horse heart number, My 1275028 _ Case No. 91115786_Yearly revision _ VI. Patent application scope 1 1. The logarithmic operation method of floating point number as described in claim 7 of the patent application scope, wherein the logarithmic table is a pre-established logarithmic logarithm table The result of the logarithmic operation of the 诙 value Ax with p as the base is obtained. 1 2. The logarithmic operation method of floating point number according to claim 7, wherein the Taylor expansion operation circuit is a pre-established circuit which uses a cubic Taylor approximation to find that the value is equal to 1 η (1 + Rd) The value. &lt;1 0702-7517twf3(3.7) ; 90P131 ; CHEN.ptc Page 21 No. revision page Revision date: 95/10/11 p year (one) month &quot;day correction