CN113885836A - Modulus operation method and device, electronic equipment and computer readable storage medium - Google Patents

Modulus operation method and device, electronic equipment and computer readable storage medium Download PDF

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CN113885836A
CN113885836A CN202111025864.5A CN202111025864A CN113885836A CN 113885836 A CN113885836 A CN 113885836A CN 202111025864 A CN202111025864 A CN 202111025864A CN 113885836 A CN113885836 A CN 113885836A
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divisor
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邓周
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Zeku Technology Beijing Corp Ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/727—Modulo N arithmetic, with N being either (2**n)-1,2**n or (2**n)+1, e.g. mod 3, mod 4 or mod 5

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Abstract

The embodiment of the application relates to the technical field of computers, and discloses a modular arithmetic method, a device, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: expressing the integer b as a first form of b ═ cd, where c and d are divisors of the integer b; and calculating a modulo result of the integer a modulo the integer b expressed as the first form. By implementing the embodiment of the application, the hardware calculation efficiency of the arithmetic device can be improved.

Description

Modulus operation method and device, electronic equipment and computer readable storage medium
Technical Field
The present application relates to the field of computer technologies, and in particular, to a modulo operation method, an apparatus, an electronic device, and a computer-readable storage medium.
Background
The modular operation is an operation for calculating the remainder of division of two numbers, and is widely applied to various fields such as digital signal processing, cryptography and the like.
In practice, it is found that most of the modulus operations adopted in the current computing devices are realized by operations of displacement, comparison and subtraction iteration, so that when the difference between the dividend and the divisor is too large, the number of iterations required is very large, which is not beneficial to improving the hardware computing efficiency of the computing devices.
Disclosure of Invention
The embodiment of the application discloses a modular arithmetic method, a modular arithmetic device, electronic equipment and a computer readable storage medium, which can improve the hardware calculation efficiency of arithmetic equipment.
A first aspect of the present embodiment discloses a modulo operation method, where the method includes:
expressing the integer b as a first form of b ═ cd, where c and d are divisors of the integer b; calculating a modulo result of the integer a modulo the integer b represented as said first form.
A second aspect of an embodiment of the present application discloses an arithmetic device, including: an arithmetic circuit for representing an integer b as a first form of b ═ cd, where c and d are divisors of the integer b; and calculating a modulo result of the integer a modulo the integer b expressed as said first form.
A third aspect of an embodiment of the present application discloses an arithmetic device, including: an arithmetic circuit for representing an integer b in the form of b ═ cd, where c and d are divisors of the integer b; dividing the integer a by the first divisor to obtain a first quotient and a first remainder, and dividing the first quotient by the second divisor to obtain a second remainder; wherein, if the first divisor is an integer c, the second divisor is an integer d, or if the first divisor is an integer d, the second divisor is an integer c; and determining a modulus result of the integer a to the integer b according to the first remainder and the second remainder.
A fourth aspect of the embodiments of the present application discloses an arithmetic device including the arithmetic circuit of any one of the second aspect or the third aspect of the embodiments of the present application, and a processor connected to the arithmetic circuit;
the processor is configured to configure the integer a and the integer b to the arithmetic circuit.
As an optional implementation manner, a fourth aspect of the embodiments of the present application discloses that the arithmetic device further includes: a register connected to the arithmetic circuit;
the register is used for triggering the operation circuit to operate, and the operation circuit is used for calculating the modulus result of the integer a and the integer b under the triggering of the register.
A fifth aspect of an embodiment of the present application discloses an electronic device, including:
a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing a method of modular arithmetic as disclosed in the first aspect of an embodiment of the present application or implementing a method of modular arithmetic as disclosed in the second aspect of an embodiment of the present application.
A sixth aspect of embodiments of the present application discloses a computer-readable storage medium storing a computer program, wherein the computer program causes a computer to execute the modulo arithmetic method disclosed in the first aspect of embodiments of the present application, or execute the modulo arithmetic method as disclosed in the second aspect of embodiments of the present application.
Compared with the related art, the embodiment of the application has the following beneficial effects:
in an embodiment of the present invention, the integer b may be expressed as a first form of b ═ cd, where c and d are divisors of b; a modulo result of integer a modulo integer b, represented as the first form, may then be computed. By the scheme, the integer b can be decomposed into two submultiples c and d, so when the integer a is divided by a plurality of different integers b, if the submultiples obtained by splitting a plurality of divisors b have the same submultiple, the calculation results of the same submultiple can be shared in the modulus operation process aiming at the divisors b without repeated calculation, so that the calculation of the integer a on the integer b can be simplified, the hardware calculation efficiency of the operation equipment is improved, and in addition, the calculation methods aiming at the same submultiple can be multiplexed in the modulus operation process aiming at the divisors b, so that the realization difficulty is reduced, and the realization cost is reduced.
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In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a modulo operation method disclosed in an embodiment of the present application;
FIG. 2 is a schematic flow chart diagram illustrating another modulo operation method disclosed in the embodiments of the present application;
FIG. 3 is a schematic flow chart diagram illustrating another modulo operation method disclosed in the embodiments of the present application;
FIG. 4 is a schematic flow chart illustrating another modulo operation method disclosed in the embodiments of the present application;
FIG. 5 is a schematic structural diagram of an arithmetic device according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another computing device disclosed in the embodiments of the present application;
fig. 7 is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first", "second", "third" and "fourth", etc. in the description and claims of the present application are used for distinguishing different objects, and are not used for describing a specific order. The terms "comprises," "comprising," and "having," and any variations thereof, of the embodiments of the present application, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the application discloses a modular arithmetic method, a modular arithmetic device, electronic equipment and a computer readable storage medium, which can improve the hardware calculation efficiency of arithmetic equipment.
The technical solution of the present application will be described in detail with reference to specific examples.
First, the related technical content of the embodiment of the invention is introduced:
the main difference between the modulo operation and the remainder operation is the rounding of the quotient value when dividing a negative integer. The result of either the modulo operation of integer a over integer b or the remainder operation can be expressed as r-a-b × q, where q is the integer quotient of a divided by b.
The modular operation and the remainder operation are different, in the remainder operation, the quotient value is rounded towards the 0 direction; in the modulo operation, the quotient is rounded to minus infinity. If both integer a and integer b are unsigned integers (i.e., non-negative integers), the modulo operation and the remainder operation result are the same and are equal to the remainder of dividend a divided by divisor b, which can be expressed as
Figure BDA0003243407140000041
In the hardware circuit implementation of the modulus operation, the modulus operation process is relatively complex, the traditional modulus method usually adopts a vertical division mode, and repeatedly subtracts the value of the shifted divisor from the dividend through iterative computation of multiple shifting, comparing and subtracting operations until the dividend is smaller than the divisor, and the obtained result is the remainder.
For example, an m-bit unsigned integer a is modulo an n-bit unsigned integer b, by first converting a to a' with the upper n bits being 0 and the lower m bits being a. B is converted into b' with the high n bits as b and the low m bits as 0. When each iteration starts, a 'is shifted to the left by one bit, 0 is supplemented at the end, then the comparison is carried out with b', if the result is larger than b ', a' subtracts b 'and adds 1, otherwise, the next iteration is carried out, wherein the iteration process needs to be carried out for m times, and the high n bits of a' are remainder after the iteration is finished.
The traditional modulus taking method adopts the iterative calculation of shifting, comparing and subtracting operations, when dividend is large but divisor is small, more iteration times are needed to obtain the modulus taking result, the calculation period is long, and the delay is large.
In an alternative implementation, the table lookup based method stores the result of the modulo operation in advance, so that the result can be quickly obtained, but more resources are required to store the corresponding remainder table.
In view of the above, the embodiment of the present application discloses a modulo operation method, which can decompose an integer b into two divisors c and d, so when an integer a is divided by a plurality of different integers b, if the same divisor exists in the divisors obtained by splitting a plurality of divisors b, the modulo process for b of the plurality of divisors can share the calculation result for the same divisor without repeated calculation, thereby simplifying the calculation of the integer a on the integer b, improving the hardware calculation efficiency of an operation device, and in addition, in the modulo operation process for the plurality of divisors b, multiplexing the calculation methods for the same divisor so as to reduce the implementation difficulty and further reduce the implementation cost.
Furthermore, the modulus operation method disclosed by the embodiment of the application does not need to occupy a large amount of resources to store the corresponding remainder table, so that the storage resources can be saved.
The modular arithmetic method provided by the embodiment of the application can be applied to various fields (such as digital signal processing and cryptography) and relates to the scenes of integer modular arithmetic.
For example: in a Communication system of 5G (5th Generation Mobile Communication Technology, fifth Generation Mobile Communication Technology) NR (New Radio interface) in the Communication field, LDPC (low density parity check) codes are adopted for data coding of a physical uplink shared channel and a physical downlink shared channel, and a check matrix of the LDPC codes includes a cyclic shift matrix, where a cyclic shift value P in the cyclic shift matrixi,jIs obtained by a modulo operation. The calculation formula is Pi,j＝Vi,jmod ZcWherein V isi,jIs a cyclic shift reference value of each cyclic shift matrix, and the value range is more than or equal to 0 and less than or equal to Vi,j≤383；ZcThe lifting value of the check matrix is shown in the following table 1:
aggregate number (i)LS) Lifting value set (Z)c)
0 {2,4,8,16,32,64,128,256}
1 {3,6,12,24,48,96,192,384}
2 {5,10,20,40,80,160,320}
3 {7,14,28,56,112,224}
4 {9,18,36,72,144,288}
5 {11,22,44,88,176,352}
6 {13,26,52,104,208}
7 {15,30,60,120,240}
TABLE 1
Can be seen, ZcHas a plurality of value ranges, so that the reference value V is circularly shifted in the encoding processi,jThe lifting value Z of the check matrix may need to be different from that of the check matrixcPerforming a modulo operation (i.e. any one of a set of lifting values) using the phaseIn the related art, the value Z is improved for different check matrixescIn time, different modulo arithmetic methods are often needed, which is not beneficial to reducing the complexity of implementation.
By adopting the modulo operation method provided by the embodiment of the application, the check matrix can be improved by the value ZcIs represented by ZcFirst form of cd, where c and d are check matrix lifting values ZcA divisor of (d); and then a cyclic shift reference value V can be calculatedi,jRaising the check matrix represented in the first form by a value ZcAnd (4) taking a modulus result.
Alternatively, the reference value V may be shifted cyclicallyi,jDividing the first divisor into a first quotient and a first remainder, and dividing the first quotient into a second divisor into a second remainder; wherein, if the first divisor is an integer c, the second divisor is an integer d, or if the first divisor is an integer d, the second divisor is an integer c.
Further, a cyclic shift reference value V can be determined according to the first remainder and the second remainderi,jLifting value Z of check matrixcAnd (5) taking a modulus result of the modulus.
For example, in combination with table 1, the lifting value Z of the check matrix corresponding to the set number 3cThe set {7, 14, 28, 56, 112, 224}, may be decomposed into {7 x 2 }0，7*21，7*22，7*23，7*24，7*25And further raising a value Z for the plurality of check matricescAssuming that the common divisor 7 is used as the first divisor, the cyclic shift reference value V is calculated only oncei,jDividing by the first divisor 7 to obtain a first quotient and a first remainder ", and then other modulus taking processes can directly use the first quotient and the first remainder obtained by the previous calculation without repeating the calculation, thereby improving the efficiency of operation checking. In addition, the value Z is raised for the received check matrixcThe calculation method for the common divisor 7 can be multiplexed, thereby reducing the implementation complexity.
The modulo operation method provided by the embodiment of the present invention may be executed by an operation device, or executed by a functional module or a functional entity in the operation device.
The computing device may be a computer, a chip, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, a Personal Digital Assistant (PDA), a wearable terminal device, and the like, and the embodiment of the present invention is not limited to a specific form of the computing device.
The functional entity may be a processor in an arithmetic device for implementing an integer modulo operation method, or may be a hardware circuit in an arithmetic device (referred to as an arithmetic circuit in the embodiment of the present invention) for implementing an integer modulo operation method.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a modulo operation method according to an embodiment of the present disclosure. The method may comprise the steps of:
102. the integer b is denoted as b ═ cd in the first form, and c and d are divisors of the integer b.
In the embodiment of the present application, the integer b may include an unsigned integer (i.e., a non-negative integer). Further, the integer b may be decomposed into an integer c multiplied by an integer d, i.e. the integer c and the integer d are divisors of the integer b, including the greatest common divisor.
104. The result of modulo the integer a modulo the integer b, which is represented as the first form, is computed.
It is to be understood that since the modulus operation is equivalent to performing a division operation, when calculating the modulus result of the integer a taking the modulus of the integer b expressed as the first form, the integer a may be calculated as the dividend and the integer b expressed as the first form may be calculated as the divisor. Let the quotient of integer a divided by integer b be
Figure BDA0003243407140000061
The remainder is r, then equation 1 can be obtained: a is qb + r, and r is more than or equal to 0 and less than or equal to b-1.
In one embodiment, integer b can be decomposed into integer c and integer d, then "integer a divided by integer b" equals "integer a divided by the product of integer c and integer d," and "integer a divided by the product of integer c and integer d" equals "first quotient divided by integer d, where the first quotient equals integer a divided by integer c", i.e.:
Figure BDA0003243407140000071
this can be given by equation 2: a is q ' c + r ', 0 is not less than r ' and not more than c-1, wherein q ' is a first quotient of integer a divided by integer b, and r ' is a first remainder of integer a divided by integer b;
and equation 3: q ' ═ q "d + r", 0 ≦ r ≦ d-1, where q "is the first quotient q ' of integer a divided by integer b, divided by the second quotient of integer d, and r" is the first quotient q ' of integer a divided by integer b, divided by the second remainder of integer d;
substituting equation 3 into equation 2 yields equation 4:
Figure BDA0003243407140000072
wherein r 'c + r' is not less than 0 and not more than (d-1) c + c-1 ═ b-1.
Further, comparing equation 1 and equation 4, one can obtain:
Figure BDA0003243407140000073
the result of comparing equation 1 with equation 4 can be obtained by taking the modulus of integer a to integer b, i.e. the remainder of integer a divided by integer b
Figure BDA0003243407140000074
Wherein the content of the first and second substances,
Figure BDA0003243407140000075
meaning that the integer a is divided by the first divisor to obtain a first quotient,
Figure BDA0003243407140000076
indicating that the integer a is divided by the first divisor to obtain a first remainder, and (a mod c) indicating that the first quotient is divided by the second divisor to obtain a second remainder.
As described above, in the embodiment of the present application, the operation of modulo the integer a with respect to the integer b expressed as the first form can be converted into the operation of dividing the integer a by the first divisor and the first remainder of the first divisor, and dividing the first quotient by the second remainder of the second divisor. Wherein, if the first divisor is an integer c, the second divisor can be an integer d; in another embodiment, if the first divisor is an integer d, the second divisor may be an integer c, which is not limited herein. In the embodiments of the present application, the first divisor is an integer c, and the second divisor is an integer d, which should not be construed as a limitation to the embodiments of the present application.
It should be noted that the first divisor is an integer c, and the second divisor is an integer d. In fact, the calculation process using the integer d as the first divisor and the integer c as the second divisor is similar to the above calculation process, and is not described herein again.
In the above method, the integer b may be decomposed into two divisors c and d, and if there is the same divisor among the divisors of the plurality of integers b in the modulo operation of the same integer a on different integers b, the calculation results for the same divisor may be shared in the modulo operation of the plurality of integers b, for example: the integer b can decompose the first divisor c, so that when the modulus result of the integer a to different integers b is calculated, the integer a can be used for dividing by the first divisor to obtain a first quotient and a first remainder without repeatedly calculating the integer a for dividing by the first divisor to obtain the first quotient and the first remainder, thereby simplifying the calculation of the integer a to the integer b, improving the hardware calculation efficiency of the arithmetic device, and in addition, in the modulus operation process aiming at the divisor b, the calculation method aiming at the same divisor can be multiplexed to reduce the realization difficulty, and further reduce the realization cost.
Referring to fig. 2, fig. 2 is a schematic flow chart of another modulo operation method disclosed in the embodiment of the present application, where the method may include the following steps:
202. the integer b is denoted as b ═ cd in the first form, and c and d are divisors of the integer b.
204. The integer a is divided by the first divisor to obtain a first quotient and a first remainder.
In practice, it has been found that arithmetic devices are less computationally efficient at computing division operations than computing multiplication, addition and displacement operations. Alternatively, the division operation of dividing the integer a by the first divisor can be converted into multiplication, addition or displacement operation with equal calculation results, so as to improve the hardware calculation efficiency of the arithmetic device.
In an embodiment, the first parameter N may be generated according to a value range of the integer a and the first divisor c1A second parameter M1And a third parameter L1. Wherein the first parameter N1A second parameter M1And a third parameter L1So that (M)1a+L1) Is divided by
Figure BDA0003243407140000091
Equal to the integer a divided by the first divisor c, i.e.:
Figure BDA0003243407140000092
further, (M) can be calculated1a+L1) Is divided by
Figure BDA0003243407140000093
A first quotient is obtained and taken as the first quotient of the integer a divided by the first divisor c.
Further, the first quotient may be multiplied by a first divisor c to obtain a first product, and the integer a is subtracted from the first product to obtain a first difference, which is a first remainder of the integer a divided by the first divisor c.
Illustratively, the cyclic shift value P of the LDPC code check matrix in a 5G NR communication systemi,jThe calculation of (b) is explained as an example. Cyclic displacement value Pi,jIs calculated by the formula Pi,j＝Vi,jmod ZcWherein V isi,jIs a cyclic shift reference value of each cyclic shift matrix, and the value range is more than or equal to 0 and less than or equal to Vi,j≤383；ZcIs the check matrix lifting value.
According to the modular operation method disclosed by the embodiment of the application, the check matrix can be improved by the value ZcDecomposed into a divisor c and a divisor d, and a cyclic shift reference value V is calculatedi,jWhen dividing by the first divisor c, the corresponding first parameter N may be generated according to different first divisors c1A second parameter M1And a third parameter L1。
Illustratively, the first parameter N is generated according to different first submultiples c1A second parameter M1And a third parameter L1As shown in table 2 below:
Figure BDA0003243407140000094
TABLE 2
For example, in conjunction with Table 2, assume cyclic shift reference value Vi,j368, check matrix lifting value ZcWhen the first divisor c is 7, N is obtained according to table 21＝11，M1＝292，L1124, further available are:
Figure BDA0003243407140000101
and the remainder r' 368-52 7-4.
It should be further noted that the data and the calculation process in table 2 are for convenience of describing the modulo operation method disclosed in the embodiment of the present application, but illustrate an implementation manner, and should not be limited to the embodiment of the present application.
By implementing the method, the division operation in the modulus operation can be converted into multiplication, addition or displacement operation, thereby improving the hardware calculation efficiency of the arithmetic device.
206. The first quotient is divided by the second divisor to obtain a second remainder.
In the embodiment of the present application, in the process of calculating the division of the first quotient by the second divisor, a method similar to the method for converting the division in the modulo operation into a multiplication, addition, or displacement operation described in step 204 may be adopted to convert the division of the first quotient by the second divisor into a multiplication, addition, or displacement operation, so as to improve the calculation efficiency of calculating the division of the first quotient by the second divisor. It is understood that the conversion method and the calculation method may be similar to those described in step 204, and are not described herein again.
In another embodiment, if the second divisor is equal to an nth power of 2, n being an integer, the method comprises: 21、22、24Etc., and are not limited thereto. The first quotient may be converted to binary form resulting in a binary-form first quotient. For example: the first quotient "52" in decimal form may be converted to a first quotient "000110100" in binary form.
Furthermore, the n numbers corresponding to the bit weights of the n-bit arranged later can be obtained from the first quotient of the binary form according to the order of the bit weights from high to low. For example, assume that the second divisor equals 23Then, the 3 digits corresponding to the weights arranged in the last 3 digits in the first quotient "000110100" in binary form are "100".
A second remainder of the first quotient divided by the second divisor can be determined based on the n digits and the corresponding weights of the digits. Optionally, each number may be multiplied by the corresponding bit weight to obtain a plurality of products, and then the plurality of products are added to obtain a decimal second remainder.
As mentioned above, the 3 digits corresponding to the last 3 bits are "100", and the last 3 bits are 2 from high to low2、21And 20Then the second remainder r' is 22*1+21*0+20*0＝4。
By implementing the method, if the second divisor is determined to be equal to the nth power of 2, the division operation of dividing the first quotient by the second divisor can be simplified into taking the binary bit corresponding to the first quotient, and operations such as multiplication, addition and subtraction are not needed, so that the hardware calculation efficiency of the arithmetic device can be improved.
Optionally, in the calculation process of dividing "integer a by first divisor", if it is determined that the first divisor is equal to m-th power of 2, and m is an integer, the above similar method may be adopted, and binary bits of m bits after the binary-form integer a are taken as remainder of dividing the integer a by the first divisor, without performing operations such as multiplication, addition, subtraction, and the like, so that hardware calculation efficiency of the calculation apparatus may be improved.
In one embodiment, the divisor of the integer b decomposition is such that it comprises a divisor that is equal to the nth power of 2 to facilitate subsequent operations. Alternatively, the integer b may be represented as a first form, the first form including b ═ c × 2nOr, b is 2nD, wherein c, d and n are integers.
By implementing the method, the divisor of the integer b decomposition can be made to include the divisor of the nth power which is equal to 2 as far as possible, and then when the divisor of the nth power which is equal to 2 is subjected to division operation, the division operation can be simplified into taking the binary bit corresponding to the first quotient without carrying out operations such as multiplication, addition and subtraction, and the like, so that the hardware calculation efficiency of the arithmetic device can be improved.
208. And determining a modulus result of the integer a to the integer b according to the first remainder and the second remainder.
In the embodiment of the application, after the first remainder and the second remainder are obtained through calculation, the second remainder can be multiplied by the first divisor to obtain a second product; and adding the second product and the first remainder to obtain a first sum, and taking the first sum as a modulus result of taking the integer a to the integer b. Namely:
r＝r″c+r′
where r represents the result of modulo integer a modulo integer b, r 'represents the second remainder, r' represents the first remainder, and c represents the first divisor.
By implementing the method, the modulus-taking result of the integer a for the integer b can be determined according to the first remainder and the second remainder, so that in the modulus-taking operation process for the same integer a for different integers b, the same remainder (including the first remainder and the second remainder) obtained by the same modulus-taking operation can be shared for different integers b with the same divisor in the split divisors, and repeated calculation is not needed, so that the calculation of the integer a for the integer b can be simplified, and the hardware calculation efficiency of the operation equipment can be improved.
By implementing the method disclosed by each embodiment, the calculation of the integer a to the integer b can be simplified, and the hardware calculation efficiency of the operation equipment is improved; the division operation in the modular operation method can be converted into multiplication, addition or displacement operation, so that the hardware calculation efficiency of the arithmetic device is improved; if the second divisor is equal to the nth power of 2, the division operation of dividing the first quotient by the second divisor can be simplified into taking the binary bit corresponding to the first quotient without operations such as multiplication, addition and subtraction, and the like, so that the hardware calculation efficiency of the arithmetic device can be improved; and, can make integer b decomposed divisor include divisor equal to 2 n power as far as possible, facilitate the subsequent calculation; and determining a modulus-taking result of the integer a for modulus of the integer b according to the first remainder and the second remainder, and further sharing the same remainder (including the first remainder and the second remainder) obtained by the modulus-taking operation for different integers b with the same divisor in the modulus-taking process of the same integer a for different integers b without repeated calculation, thereby simplifying the calculation of the integer a for the integer b and improving the hardware calculation efficiency of the operation equipment; in addition, in the process of modulus operation for a plurality of divisors b, calculation methods for the same divisor can be multiplexed to reduce the implementation difficulty and further reduce the implementation cost.
Referring to fig. 3, fig. 3 is a schematic flow chart of another modulo operation method disclosed in the present embodiment, where the method includes the following steps:
302. determining a set of integers biAnd f, common divisor c corresponding to a plurality of integers is included, wherein i is a positive integer.
In practical application, the market needs to calculate the modulus operation of the same integer a to different integers b, for example, the cyclic shift value P of the LDPC code check matrix in the 5G NR communication systemi,jIn the calculation of (2), it is necessary to calculate the same cyclic shift value Pi,jRaising the value Z for different check matricescAnd (4) taking a modulus result.
In contrast, the method aims at the problem that the composition is formed by a plurality of different integersSet of integers { b }iAnd determining common divisor c corresponding to a plurality of integers included in the set. In other alternative embodiments, the greatest common divisor, the least common divisor, or other divisors of the integers included in the set may also be determined, and are not limited herein.
304. The integer biIs denoted by biIn a first form of cd, c is a common divisor of a plurality of integers, and d is
Figure BDA0003243407140000121
Integer biIs a set of integers { biAny integer comprised.
After determining the integer set biAfter the common divisor c corresponding to the multiple integers included in the integer set is included, each integer b in the integer set can be divided into a plurality of integersiIs denoted by biIn a first form of cd, c is a common divisor corresponding to a plurality of integers,
Figure BDA0003243407140000122
it will be appreciated that since each integer b in the set of integers isiThe common divisor c can be decomposed, so that when the common divisor c is used as the first divisor in the calculation of the modulo operation method disclosed in the embodiment of the present application, the integer a is divided by the first divisor to obtain the first quotient and the first remainder only once, and for the other integer b, the integer a is divided by the first divisor to obtain the first quotient and the first remainderiThe modulus operation process can directly use 'integer a to divide the first divisor to obtain a first quotient and a first remainder', and repeated calculation is not needed, so that the hardware calculation efficiency of the operation equipment can be improved, and in addition, the calculation methods aiming at the same divisor can be multiplexed in the modulus operation process aiming at a plurality of divisors b, so that the realization difficulty is reduced, and the realization cost is reduced.
Illustratively, the check matrix lifting value Z in LDPC codecEach check matrix lifting value Z in any integer setcCan be decomposed into a common divisor c and a different divisor d, denoted "nth power of 2".
For this purpose, the cyclic displacement value P is calculated only oncei,jDividing by the first quotient and the first remainder of the common divisor c, the same cyclic shift value P is calculatedi,jRaising the value Z for different check matrices in the same integer setcThe calculation method for the common divisor c can be multiplexed during the modular operation, thereby reducing the complexity of realization.
For example: for the lifting value set with the common divisor c being 7, the lifting value Z of the check matrix in the lifting value set is aimed atcThe modulo process of (2) can multiplex the operation implementation method aiming at the common divisor 7.
Furthermore, since the other divisor d is equal to the nth power of 2, the first quotient can be directly converted into a binary form, resulting in the first quotient in the binary form, n being an integer; then according to the order of the bit weights from high to low, acquiring n numbers of codes corresponding to the bit weights of the n bits arranged at the back from the first quotient of the binary form; and determining a second remainder of the first quotient divided by the second divisor based on the n digits and the corresponding bit weights of the digits. That is, the division operation of dividing the first quotient by the second divisor can be simplified to the binary digit corresponding to the first quotient, and operations such as multiplication, addition and subtraction are not required, so that the hardware calculation efficiency of the arithmetic device can be improved.
306. Calculating the pair of integers a and b expressed as a first formiAnd (5) taking a modulus result of the modulus.
By implementing the methods disclosed in the above embodiments, common divisor corresponding to integer included in the set can be determined for the integer set, and further, each integer b in the integer setiThe common divisor c can be decomposed, so that when the common divisor c is used as the first divisor in the calculation of the modulo operation method disclosed in the embodiment of the present application, the integer a is divided by the first divisor to obtain the first quotient and the first remainder only once, and for the other integer b, the integer a is divided by the first divisor to obtain the first quotient and the first remainderiThe modulus operation process can directly use 'integer a is divided by first divisor to obtain first quotient and first remainder', without repeated calculation, thereby improving hardware calculation efficiency of operation equipment, in addition, the modulus operation process aiming at a plurality of divisors b can multiplex calculation methods aiming at the same divisor to reduce realization difficulty,thereby reducing the implementation cost.
Referring to fig. 4, fig. 4 is a schematic flow chart of another modulo operation method disclosed in the embodiment of the present application, where the method may include the following steps:
402. the integer b is denoted as b ═ cd in the first form, and c and d are divisors of the integer b.
404. If both the integer c and the integer d are not equal to the nth power of 2, a fourth parameter N is generated2The fifth parameter M2And a sixth parameter L2Fourth parameter N2The fifth parameter M2And a sixth parameter L2So that (M)2a+L2) Is divided by
Figure BDA0003243407140000141
Equal to the integer a divided by the integer b.
As described above, if a divisor equal to the nth power of 2 is present among the divisors of the integer b, the division operation for the divisor can be simplified to the binary bit corresponding to the dividend without operations such as multiplication and addition and subtraction, and the hardware calculation efficiency of the arithmetic device can be improved.
On the other hand, if both the integer c and the integer d decomposed from the integer b are not equal to the nth power of 2, the division operation for divisor cannot be simplified to the manner of taking the binary bit corresponding to the dividend, which is not favorable for improving the hardware calculation efficiency of the arithmetic device. Alternatively to this, a fourth parameter N may be generated2The fifth parameter M2And a sixth parameter L2Fourth parameter N2The fifth parameter M2And a sixth parameter L2So that (M)2a+L2) Is divided by
Figure BDA0003243407140000142
The integer a is divided by the integer b to convert the division operation into multiplication, addition and displacement operation, and the calculation efficiency of the calculation device in the calculation of the multiplication, addition and displacement operation is higher than that in the calculation of the division operation, so that the hardware calculation efficiency of the calculation device can be improved.
406. Calculating (M)2a+L2) Is divided by
Figure BDA0003243407140000143
And obtaining a second quotient, and multiplying the second quotient by the integer b to obtain a third product.
408. And subtracting the third product from the integer a to obtain a second difference, and taking the second difference as a modulus result of taking the modulus of the integer a to the integer b.
By implementing the methods disclosed in the above embodiments, when both the integer c and the integer d decomposed from the integer b are not equal to the nth power of 2, the division operation of the integer b by the integer a can be converted into multiplication, addition and displacement operations, and since the calculation efficiency of the arithmetic device in calculating the multiplication, addition and displacement operations is greater than that in calculating the division operation, the hardware calculation efficiency of the arithmetic device can be improved, and in addition, the calculation methods for the same divisor can be multiplexed in the modulo operation process for a plurality of divisors b, so as to reduce the implementation difficulty and further reduce the implementation cost.
The embodiment of the invention provides an arithmetic device, and a first optional implementation mode is as follows:
as shown in fig. 5, fig. 5 is a schematic structural diagram of an arithmetic device according to an embodiment of the present invention, the device including:
an arithmetic circuit 501 for expressing an integer b as a first form of b ═ cd, c and d being divisors of the integer b; and calculating a modulo result of the integer a modulo the integer b expressed as the first form.
Optionally, the operation circuit 501 is specifically configured to divide the integer a by the first divisor to obtain a first quotient and a first remainder, and divide the first quotient by the second divisor to obtain a second remainder; wherein, if the first divisor is an integer c, the second divisor is an integer d, or if the first divisor is an integer d, the second divisor is an integer c; and determining a modulus result of the integer a to the integer b according to the first remainder and the second remainder.
Optionally, the operation circuit 501 is specifically configured to generate the first parameter N1A second parameter M1And a third parameter L1First parameter N1A second parameter M1And a third parameter L1So that (M)1a+L1) Is divided by
Figure BDA0003243407140000151
Is equal to the integer a divided by the first divisor; and, calculating (M)1a+L1) Is divided by
Figure BDA0003243407140000152
Obtaining a first quotient of the integer a divided by the first divisor, and multiplying the first quotient by the first divisor to obtain a first product; and subtracting the first product from the integer a to obtain a first difference, and dividing the first difference into a first remainder of the first divisor and the integer a.
Optionally, the operation circuit 501 is specifically configured to convert the first quotient into a binary form when the second divisor is equal to the nth power of 2, so as to obtain the first quotient in the binary form, where n is an integer; acquiring n numbers of digits corresponding to the digit weights arranged at the last n digits from the first quotient in the binary form according to the order of the digit weights from high to low; and determining a second remainder of the first quotient divided by the second divisor according to the n digits and the corresponding bit weights of the digits.
Optionally, the operation circuit 501 is specifically configured to represent the integer b as a first form, where the first form includes b ═ c × 2nOr, b is 2nD, wherein c, d and n are integers.
Optionally, the operation circuit 501 is specifically configured to multiply the second remainder by the first divisor to obtain a second product; and adding the second product and the first remainder to obtain a first sum, and taking the first sum as a modulus result of taking the integer a to the integer b.
Optionally, the operation circuit 501 is specifically configured to determine the integer set { b }iCommon divisor c corresponding to a plurality of integers, wherein i is a positive integer; and, converting the integer biIs denoted by biIn a first form of cd, c is a common divisor of a plurality of integers, and d is biC, integer biIs a set of integers { biAny integer comprised.
Optionally, the operation circuit 501 is specifically configured to be unequal between the integer c and the integer dGenerating a fourth parameter N at the nth power of 22The fifth parameter M2And a sixth parameter L2Fourth parameter N2The fifth parameter M2And a sixth parameter L2So that (M)2a+L2) Is divided by
Figure BDA0003243407140000162
Is equal to the integer a divided by the integer b; and, calculating (M)2a+L2) Is divided by
Figure BDA0003243407140000161
Obtaining a second quotient, and multiplying the second quotient by the integer b to obtain a third product; and subtracting the third product from the integer a to obtain a second difference, and taking the second difference as a modulus result of modulus of the integer a to the integer b.
A second alternative implementation:
as shown in fig. 5, fig. 5 is a schematic structural diagram of an arithmetic device according to an embodiment of the present invention, the device including:
an arithmetic circuit 501 for expressing an integer b in the form of b ═ cd, c and d being divisors of the integer b; dividing the integer a by the first divisor to obtain a first quotient and a first remainder, and dividing the first quotient by the second divisor to obtain a second remainder; wherein, if the first divisor is an integer c, the second divisor is an integer d, or if the first divisor is an integer d, the second divisor is an integer c; and determining a modulus result of the integer a to the integer b according to the first remainder and the second remainder.
Referring to fig. 6, fig. 6 is a schematic structural diagram of another computing device disclosed in the embodiment of the present application. The arithmetic device may include: an arithmetic circuit 501, and a processor 502 connected to the arithmetic circuit 501.
In this embodiment of the present invention, the processor 502 is configured to configure the integer a and the integer b to the arithmetic circuit 501, and the arithmetic circuit 501 is configured to calculate the modulo result of the integer a and the integer b according to any one of the first optional implementation manner and the second optional implementation manner.
Referring to fig. 6 again, the computing device shown in fig. 6 further includes: and a register 503 connected to the arithmetic circuit 501.
The register 503 is configured to trigger the operation of the arithmetic circuit, and the arithmetic circuit 501 is configured to calculate the modulo result of the integer a and the integer b according to any one of the first optional implementation and the second optional implementation, under the trigger of the register 503.
The processor 502 may input the integer a and the integer b to an input end of the arithmetic circuit 501, and the arithmetic circuit 501 calculates a modulo result of the integer a and the integer b and outputs the modulo result from an output end of the arithmetic circuit 501.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application, where the electronic device may include: the processor 701, the memory 702, and a computer program stored on the memory 702 and capable of running on the processor 701, wherein when the computer program is executed by the processor 701, the modulo operation method disclosed in the above embodiments is implemented.
An embodiment of the present invention further provides a computer-readable storage medium, including: the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the modulo operation method disclosed in the above embodiments.
Embodiments of the present invention also provide a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform some or all of the steps of the method as in the above method embodiments.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also appreciate that the embodiments described in this specification are all alternative embodiments and that the acts and modules involved are not necessarily required for this application.
In various embodiments of the present application, it should be understood that the size of the serial number of each process described above does not mean that the execution sequence is necessarily sequential, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated units, if implemented as software functional units and sold or used as a stand-alone product, may be stored in a computer accessible memory. Based on such understanding, the technical solution of the present application, which is a part of or contributes to the prior art in essence, or all or part of the technical solution, may be embodied in the form of a software product, stored in a memory, including several requests for causing a computer device (which may be a personal computer, a server, a network device, or the like, and may specifically be a processor in the computer device) to execute part or all of the steps of the above-described method of the embodiments of the present application.
It will be understood by those skilled in the art that all or part of the steps in the methods of the embodiments described above may be implemented by hardware instructions of a program, and the program may be stored in a computer-readable storage medium, where the storage medium includes Read-Only Memory (ROM), Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), One-time Programmable Read-Only Memory (OTPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc Read-Only Memory (CD-ROM), or other Memory, such as a magnetic disk, or a combination thereof, A tape memory, or any other medium readable by a computer that can be used to carry or store data.
The modulus operation method, apparatus, electronic device and computer-readable storage medium disclosed in the embodiments of the present application are introduced in detail, and a specific example is applied in the disclosure to explain the principle and implementation manner of the present application, and the description of the embodiments is only used to help understand the method and core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A method of modular arithmetic, the method comprising:
expressing the integer b as a first form of b ═ cd, where c and d are divisors of the integer b;
calculating a modulo result of the integer a modulo the integer b represented as said first form.
2. The method of claim 1, wherein calculating a modulo result of the integer a modulo the integer b represented as the first form comprises:
dividing the integer a by the first divisor to obtain a first quotient and a first remainder, and dividing the first quotient by the second divisor to obtain a second remainder; wherein, if the first divisor is an integer c, the second divisor is an integer d, or if the first divisor is an integer d, the second divisor is an integer c;
and determining a modulus result of the integer a to the integer b according to the first remainder and the second remainder.
3. The method of claim 2, wherein dividing the integer a by the first divisor to obtain a first quotient and a first remainder comprises:
generating a first parameter N1A second parameter M1And a third parameter L1The first parameter N1A second parameter M1And a third parameter L1So that (M)1a+L1) Is divided by
Figure FDA0003243407130000011
Is equal to the integer a divided by the first divisor;
calculating (M)1a+L1) Is divided by
Figure FDA0003243407130000012
Obtaining a first quotient of an integer a divided by a first divisor, and multiplying the first quotient by the first divisor to obtain a first product;
subtracting the first product from the integer a to obtain a first difference, and dividing the first difference into a first remainder of the first divisor and the integer a.
4. The method of claim 2, wherein after dividing the integer a by the first divisor to obtain a first quotient and a first remainder, the method further comprises:
if the second divisor is equal to the nth power of 2, converting the first quotient into a binary form to obtain a first quotient of the binary form, wherein n is an integer;
acquiring n numbers of codes corresponding to the bit weights of the n bits arranged at the back from the first quotient of the binary form according to the sequence of the bit weights from high to low;
and determining a second remainder of the first quotient divided by the second divisor according to the n codes and the bit weights corresponding to the codes.
5. The method according to any one of claims 1 to 4, wherein determining a modulo result of the integer a modulo the integer b according to the first remainder and the second remainder comprises:
multiplying the second remainder by the first divisor to obtain a second product;
and adding the second product and the first remainder to obtain a first sum, and taking the first sum as a modulus result of the integer a taking a modulus of the integer b.
6. The method of claim 1, wherein the expressing the integer b as a first form of b ═ cd comprises:
determining a set of integers biCommon divisor c corresponding to a plurality of integers, wherein i is a positive integer;
the integer biIs denoted by biIn a first form of the present invention, c is a common divisor corresponding to the integers, and
Figure FDA0003243407130000021
the integer biIs the integer set biAny integer comprised.
7. The method of claim 1, wherein after the representing the integer b as a first form of b ═ cd, the method further comprises:
if both the integer c and the integer d are not equal to the nth power of 2, a fourth parameter N is generated2The fifth parameter M2And a sixth parameter L2Said fourth parameter N2The fifth parameter M2And a sixth parameter L2So that (M)2a+L2) Is divided by
Figure FDA0003243407130000022
Is equal to the integer a divided by the integer b;
calculating (M)2a+L2) Is divided by
Figure FDA0003243407130000023
Obtaining a second quotient, and multiplying the second quotient by the integer b to obtain a third product;
and subtracting the third product from the integer a to obtain a second difference, and taking the second difference as a modulus result of taking the integer a to the integer b.
8. An arithmetic device, comprising:
an arithmetic circuit for representing an integer b as a first form of b ═ cd, where c and d are divisors of the integer b; and calculating a modulo result of the integer a modulo the integer b expressed as said first form.
9. An arithmetic device, comprising:
an arithmetic circuit for representing an integer b in the form of b ═ cd, where c and d are divisors of the integer b; dividing the integer a by the first divisor to obtain a first quotient and a first remainder, and dividing the first quotient by the second divisor to obtain a second remainder; wherein, if the first divisor is an integer c, the second divisor is an integer d, or if the first divisor is an integer d, the second divisor is an integer c; and determining a modulus result of the integer a to the integer b according to the first remainder and the second remainder.
10. An electronic device, comprising:
a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing a method of modulo arithmetic according to any one of claims 1 to 7.
CN202111025864.5A 2021-09-02 2021-09-02 Modulus operation method and device, electronic equipment and computer readable storage medium Pending CN113885836A (en)

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