TWI273596B - MRAM arrays and methods for writing and reading magnetic memory device - Google Patents

Abstract

A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the selected memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the selected memory cells.

Description

1273596 / IX. Description of the invention: < [Technical field of invention] 4 The present invention relates to a magnetoresistive random access memory (magnetoresistive) containing a magnetic tunnel junction (MTJ) Random access memory, η MRAM), in particular, a read write circuit for a mram array that can reduce leakage current and a plurality of magnetic tunnel junction cells. [Prior Art] The memory device of the magnetic wear-through surface includes three basic layers: a free ferromagnetic layer (free

A ferromagnetic layer), an insulating tunneling barrier, and a pinned ferromagnetic layer. The magnetic moment of the free ferromagnetic layer is free to rotate in the applied magnetic field. The fixed ferromagnetic layer may include a ferromagnetic layer and an antiferromagnetic layer that fixes the magnetic moment of the ferromagnetic layer. Therefore, the direction of the magnetic moment of the fixed ferromagnetic layer is fixed. The tunnel barrier between the fixed ferromagnetic layer and the free ferromagnetic layer is formed by a very thin insulating layer.

The electrical properties of the magnetic tunneling junction memory element can be represented by resistance. The magnitude of the resistance is determined by the direction of the magnetic moment of the free-strength magnetic layer and the fixed ferromagnetic layer. When the magnetic moment is in the opposite direction, the resistance value of 70 pieces of magnetic tunneling surface memory is the highest, and when the magnetic moment is the same direction, the resistance value of the magnetic tunneling interface memory is the lowest. That is, the _ tunnel junction memory scale can store the information of the _ bit by virtue of the opposite direction of the free ferromagnetic layer and the solid ferromagnetic layer. In other words, at any time, the magnetic field of the magnetic memory element is stable. The _ 敎 magnetic moment square j is called "parallel" and "non-parallel" state, which can respectively represent the value of the logical "Q" and the logical "丨"... In order to write the domain tunnel junction memory element or change the _ meta-like A field name can be applied, the intensity of which is sufficient to change the direction of the magnetic moment of the free ferromagnetic layer. In order to detect the magnetic penetration of the Ltg piece, it is known that the current is applied to it. Since the magnetic reluctance will be based on the magnetic wear-following surface of the gas-recovery (four) movement, the dragon can be applied to both ends of the observation element, and the magnetic reading is performed, and the 7G-like logic is lost. _ contains the reduced face memory element -0503-A31218TWF 1273596 = often by applying a sense current on the selected magnetic _ surface element _ binary data. Read (4) View field settings _ components scattered. Switching elements can also be used to prevent write disturbances. Electric grabs such as the electric crystal thief two shop _ components through t used in the _ survey circuit leakage current, these jobs usually occur when the magnetic _ surface components are read. Material, the === line when the person moves _ people interfere. _, part of the non-interfering programming circuit § 10 on the mother-magnetic wear-synthesis component or memory unit using two transistors. Inadequately, since the switching elements occupy a large area in the magnetic wear-fed surface unit, the design of the circuit has a low component density (four) density. The design of the MRAM component density of these designs is not sufficient to meet today's market demand. DX ° in Wu Guosian Patent No. 6,606,263, Tang discloses an array-free interference-free programming circuit. Figure 1 shows the structure of the unit of 2T1R revealed by Tang. In order to write the data to the memory list 14A, the _tree and the side are selected, and the write current Iw above the programming line will generate a magnetic field to change the direction of the magnetic moment of the free ferromagnetic layer of the memory element 14A. When the switching element ioc is selected, the read current Ir flows through the bit, the line 12, the memory element 14B, the programming line 15B, and the switching element i 〇 C. Therefore, the data stored in the memory element 14B can be known by the voltage on the bit line 12. Although the memory cell structure of the first figure effectively eliminates write disturb, the MRAM of Figure 1 has a very low component density. In U.S. Patent No. 5,640,343, Gallaghe, the use of a magnetic wear-receiving surface element as an MRAM array for a memory unit. Figure 2 shows Gallagher's circuit 200, which uses a switching element in each cell to control the sense current and block the leakage current. The selected memory unit 20A can be written by applying a current 込 through the bit line 22A and applying a current Iw through the word line 24A. In addition, the magnetic field generated by 'current alone' or 1 is less than the magnetic field required to change the state of the memory cell, so only the memory cell 20B through which the current IB or Iw passes (herein referred to as a semi-selected memory cell) will not be Write. However, the magnetic field generated by the current IB*IW is combined with the strength of 0503-A31218TWF 6 1273596; the memory of the selected hybrid unit 2GA. = By taking the action 'by lowering the voltage on the word line and boosting the power on the bit line ★ [the forward bias can be generated on the delayed memory unit 20A. In addition, the unselected bit line 24B and the sub 70 line 22B remain at the standby voltage, so the repeated drop between the word line and the bit line of the half-selected memory unit is 〇, and therefore does not turn on. By the resistance value of the selected memory unit 20A, (4) stored in the memory unit can be obtained. According to the current level of the selected bit line flowing to the selected character cell, the resistance value of the selected memory cell can be reached. "In U.S. Patent No. 6,317,375, Pemer discloses a method and apparatus for reading a cross-point memory cell array using a two-stage read method and a specific voltage configuration to reduce, 4 packets & The parent fork point array 3 〇〇 includes a plurality of magnetic tunneling junction memory units 31 and a cross point array 3 〇〇 including a time line 32 (referred to as a word line replacement (5) column line item called a bit line), : The bit το line 33 is perpendicular to the word line 32 and intersects with each other. The magnetic tunneling interface memory element y is located at the mosquito point of the word 4 32 and the bit (4). The memory unit 31 is the word line % and the bit line 33 The magnetic tunneling junction element is connected in series. The 4th and 4th diagrams are the path of the sensing current and the leakage current flowing through the equivalent resistance of the array of intersections in Fig. 3. 4th _ _ _ _ _ _ _ _ Equivalent resistance. The memory unit of Xin is represented by resistor 42Α, and the unselected memory unit is represented by resistance, excellent and complete. Resistor 42B does not select the unselected memory unit along the selected bit line, and the resistance is from the indicated edge. The unselected memory unit of the selected word το line, and the resistance (four) indicates the rest of the memory list For example, if all memory cells have a nominal resistance value of about R and the array includes n rows and m columns, the size of the resistor 42B is about R/(n)), and the size of the resistor 42C is about... (4) ), and the magnitude of the resistance gamma is about R^n-lXm-^, by applying a voltage 乂8 to the bit line at the stagger, and grounding the word line at the interleaving, the resistor 42A can be selected. The current is flowing through the resistor 42A. However, the resistors 42B, 42C and 42D are also between the voltage sense and the ground voltage. To mitigate the leakage current effect during the read operation, the 0503-A31218TWF 7 1273596 operating voltage Vb = Vs can be applied. In the unselected bit line, if % = , the leakage current will not flow through the resistors 42B and 42D, and a leakage current S3 flows into the ground voltage through the resistor 52C, so it does not interfere with the sensing current Is. To mitigate leakage by applying a working voltage Vb = Vs to the unselected word line

The current effect is shown in Figure 4B. At this time, the leakage current does not flow through the resistor 42B. The leakage currents S3 and S4 flowing through the resistors 42C and 42D do not flow into the ground voltage, and thus do not interfere with the sense current Is. Therefore, applying a voltage to the unselected word line and bit line in the matrix can alleviate or eliminate the error of the sense current. Therefore, a reliable sensing current and a resistance value of the selected memory unit can be obtained. Since the transistor is not included in each of the memory cells, the circuit disclosed by pemer provides a high component density MRAM. However, the reading method disclosed by pemer requires a large amount of power to be consumed, and the circuit is also very complicated because an additional bias voltage must be applied to the unselected word lines and bit lines when performing the reading process. In US Patent No. 6,421,271, Gogl discloses an MRAM 500, depicted in Figure 5, which includes a bit line 50, and word lines 51A, 51B, wherein the word lines 51A, 5m and the bit line 50 The directions are approximately vertical and at a distance. The magnetic wear-receiving surface memory element 5 is located between the bit line 50 and the word line 51A, and the magnetic-penetration interface memory element 55_58 is located between the bit line % and the element line 51B. The other end of the memory cell 51_54 not connected to the bit line % is connected to the source or the drain of the _ transistor Tr1, and the other end of the memory cell 55-58 not connected to the bit line % is connected to the transistor Tr2. Source or bungee. The gate of the transistor Tr1 is connected to the word line 51, and the gate of the transistor ΤΓ2 is connected to the word line 51B. The other source and or the drain of the transistors Tr1 and Tr2 are grounded.时 When performing a read operation, a predetermined power of about lv to 2V is applied to the bit line %. == Wu Lin, the reading of the eye _ closed. Assuming that the sub-guar line 51A is on, the transistor Tr1 is turned on. At this time, if the magnetic wear-and-match surface memory element is in a low resistance state (the magnetic moment directions of the two ferromagnetic layers are parallel), and the magnetic wear-fed surface memory element 54 is in a high resistance state (the magnetic moment directions of the two ferromagnetic layers are not parallel) ), then on the word line MA

0503-A31218TWF 8 1273596] The signal is different from that when all the fresh elements are in a high resistance state. For the purpose of determining the memory unit 5!·54 in the low resistance state, then the self-referencing sensing method._ Bowling _ing SCheme). The reading method of the job is called “breaking reading”. (—ve(10)Φ, the data recovery procedure is still needed after the recording is completed. After the destructive reading, the original beetle writer must be read. In the memory unit, such programs must consume additional time and power. [Disclosed herein] The MRAM array and the non-destructive read and write magnetic wear interface are disclosed herein.

The method of memory components. In the implementation mode, the non-destructive method of reading the memory unit includes sampling the selected read line corresponding to the memory unit to give the first health, applying a temporary magnetic field fiber unit, and avoiding the sweet The reading line is used to perform the second signal, and the first scale is compared to the sugar of the memory unit (4). Then, the magnetic grain connected to the face-to-face electric thief can be changed, and the data of the magnetic wear-following component is used before and after the Yang magnetic field. - In another embodiment, the method of reading a magnetic memory unit includes providing a magnetic through-memory device. The magnetic tooth is read, the component includes a free ferromagnetic layer, a fixed ferromagnetic layer, and a free ferromagnetic layer. The secret edge between the layer and the fixed iron is worn through the wall. In this implementation, the magnetic moment of the free ferromagnetic layer can be freely changed, and the magnetic moment of the fixed ferromagnetic layer is fixed. Therefore, the resistance of the magnetic wear-fed surface memory component may be a first stable resistance or a second stable resistance, and when there is an external magnetic field application whose intensity exceeds a low magnetic field, the magnetic wear-through surface The resistance of the memory component will be apparent. The method also includes a view-self-referencing side meter to compare the difference between the two signals (which may be a sway or a current) before and after the application of the oscillating magnetic field, wherein the oscillating magnetic field can rotate the magnetic moment of the free ferromagnetic layer - no more than 9G degrees The limbs. After comparing the _th signal and the second signal, the data stored in the magnetic piercing junction memory element can be discerned. In addition, in the implementation of the other - the crane, the tender view _ circuit includes a gift reading program

0503-A31218TWF 9 1273596 r ' provides the data line of the selected signal and the bit line V used to apply the voltage in the data reading program. In addition, the array also includes a switching element, the gate of the switching element is coupled to the data line, the coupling is connected to the first end of the bit line, and the second end, wherein the switch is received when the selection signal is received, The component will be turned on. The array also includes a plurality of magnetic tunneling junction memory elements coupled between the second end point and the word line, wherein each of the magnetically worn interface memory elements includes a free ferromagnetic layer, a fixed ferromagnetic layer, And an insulating tunneling barrier between the free ferromagnetic layer and the fixed ferromagnetic layer, wherein the magnetic moment of the free ferromagnetic layer is freely variable, and the magnetic moment of the fixed ferromagnetic layer is fixed, and the magnetic tunneling junction The f resistance of the memory element may be a first stable resistance or a second stable resistance. In this embodiment, the array i includes a plurality of programming lines, each of which corresponds to a magnetic wear-through interface memory element, for providing a second write magnetic field and a wobble magnetic field, wherein the first write magnetic field and the first The combined magnetic field of the write magnetic field exceeds the low limit magnetic field, and the low limit magnetic field is required to convert the resistance of the magnetic wear-through surface memory member, and the cap should be written on the programming line of the magnetic tunneling interface memory element. The first-written human magnetic field is generated in the human private sequence. The programming line provides a oscillating magnetic field that is smaller than the low-limit magnetic field to change the magnetic moment of the free ferromagnetic layer of the magnetic-through surface memory element, and the magnetic field corresponding to the magnetic-wearing interface is provided in the data reading device . Further comprising: a sensing circuit for passing the first signal of the magnetic wear-through surface memory element on the front side without applying the swing magnetic field, and after the application of the swing magnetic field, passing the second signal of the magnetic-wearing interface memory element, The comparison of the singular-signal and the second signal distinguishes data in the magnetic tunneling junction memory element, wherein the magnetic tunneling interface element corresponds to a programming line that provides the oscillating magnetic field. In the other embodiment, the MRAM array circuit includes a data line for providing a word line of the first write magnetic field and a bit line spanning the word line. In addition, a switching element is also included, which is connected to the secret line, the first end to the word line, and the second end point, wherein the receiving signal is received. The magnetic flux-through surface memory element _ is interposed between the bit line of the second end lining, and the magnetic memory-connecting surface memory element includes a free ferromagnetic layer, a solid magnetic sound, and a self-magnetic The insulation between the layers of the amorphous ferromagnetic layer follows the barrier, wherein the magnetic moment of the free ferromagnetic layer can be freely changed, and the magnetic moment of the fixed ferromagnetic layer is fixed, and the magnetic wear is followed.

0503-A31218TWF 10 1273596 r : The resistance of the component can be the first stable resistance or the second stable resistance. The scale circuit further includes a number of programming lines individually corresponding to each of the magnetic tunneling junction memory elements for providing a second write magnetic '%, wherein the first write magnetic field and the second write magnetic field are combined When the magnetic field exceeds the low magnetic limit, the shaft is transferred to the secret memory, and the programming line of the cap listening to the memory element generates a second write magnetic field in the data writing program. <Embodiment> [Embodiment] The following will present a number of embodiments or variants of the various implementations of the present invention. In order to simplify the present invention, specific examples of components or configurations will be described below. These examples are intended to be illustrative only and not limiting of the invention. In addition, the present invention will recite numbers and letters in various examples; this is for the purpose of simplifying the examples, and the numbers and letters are not intended to be used in connection with the configuration of the thief. In addition, the following describes that the first feature is formed on the second feature, which may include a direct contact between the first feature and the second feature, and may include other features generated and interspersed. Between the first feature and the second feature, such that the first feature is not in direct contact with the second feature. $Test Fig. 6, which is a block diagram of an integrated circuit _(5) according to an embodiment of the present invention. The integrated circuit _ includes a memory cell array 61A, which is controlled by the interface (10), and the control circuit 62G can include various circuits, such as a cipher, a sense amplifier, and the interface 630 can include a A number of bit lines, gate lines (_ this kiss, digital line (Na U (10)), control lines (control lines), word lines, and other rail circuits connected to the logic circuit. Numerous lines or word lines may be used, and different communication lines may be used in different aspects of the present invention. The integrated circuit further includes other logic circuits such as counters, timers, and the like, and buffers such as buffers. Input/round circuit 650 of the driver circuit

$考图7 This is the complex magnetoresistance P«#^^m(magnetic random access memory, MRAM)^ 700^ MRAM included in the cell array (10) of Figure 6

0503-A31218TWF 11 1273596 r * The structure of the single 兀700 does not need to be identical, but for the sake of explanation, the structure of each mram unit is here considered to include one to several magnetic tunneling junction elements 71() and one to several Switching element 720. ^ Various implementations of the magnetic tunnel interface element 71 will be further discussed below, and examples of switching elements include MOS transistors, MOS diodes, and Polar transistor. The brother recalls that το 7GG can store 1, 2, 3, 4 or more bits. Furthermore, the present invention is applicable to a single or double junction magnetic tunneling junction element of different resistance change rates (MR rati〇), which may include four magnetoresistance change values. Different resistance change rates increase the ability to sense at least 4 magnetoresistance changes and store at least two bits in a single component. The MRAM unit 700 includes three endpoints, a first endpoint 73〇, a second endpoint 74〇, and a third endpoint 750. For example, the first endpoint 73 can be connected to one to several bit lines and the voltage is applied to the bit line during the read operation. The second endpoint is connected to one to several word lines, which initiates the read and write operations of the memory unit 7 . The third terminal 75 is similar to a control line, such as a gate line or a digit line, and the terminal can generate a current to provide a magnetic field to change the state of the magnetic tunneling (MTI) component. We must understand that the configuration of bit, word line, control, and other signal lines can vary from circuit to circuit, and is provided here for illustrative purposes only. Referring to Fig. 8, there is shown a partial circuit diagram of a memory cell array 8 (8) according to an embodiment of the present invention. The memory cell array 800 includes word lines WbW2, bit lines ΒμΒ4, wires A1_A4_ and A1'A4, read lines R1, 汜, switching elements 110a-110h, magnetic tunnel junction stacks 120a-120d, 125a-125d , 130a] 30d, 135a-135d. Each of the magnetic tunneling plane stacks 1^120d, 125a-125d, 130a-130d, 135a-135d may be a memory unit such as a memory unit (U). Of course, the memory cell array_ may still include more memory cells than those shown in Fig. 8. Each of the magnetic wear-fed surface stacks l2〇a_12〇d, 125a_125d, please a], n5a_i35d may include a free layer adjacent to the programming line, and a free layer of the adjacent limbs (on (4) yet 1_, ^ connected to the county The mosquito layer and the word line at the end. However, in other shells, the position of the m 'free layer and the fixed layer may be interchanged.

0503-A31218TWF 12 1273596 Only 120a-12()d, 125a_125d, 130a_13〇d, 135a-135d also have a long axis (herein referred to as an easy-magnetization axis, 6&37& also) and a short axis (this) Called the hard magnetization axis, 1 batch (1^3). ~ Each fixed layer may include a ferromagnetic material in which the magnetic poles are fixed in the direction of the magnetic moment. For example, adjacent or adjacent to the fixed layer Including an antiferromagnetic layer or an antiferromagnetic exchange layer (in an embodiment), the fixed layer includes NiFe,

NiFeCo, CoFe, Fe, Co, Ni, alloys or compounds of the above materials, and/or other ferromagnetic materials. The pinned layer can also include a plurality of laminates. For example, the pinned layer may include a Ru spacer layer interposed between two or more layers of ferromagnetic layers. Thus each fixed layer can be or include a synthetic anti-ferromagnetic layer. The fixed layer can be chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (pECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electrochemical deposition (eiectr〇). -chemical deposition), molecular manipulation, and/or other processes. The wear barrier may include SiOx, SiNx, SiOxNy, AlOx, TaOx, TiOx, AllSbc, and/or other non-conductor materials. In one embodiment, the tunneling barrier can be formed by CVD, PECVD, ALD, PVD, electrochemical deposition, molecular manipulation, and/or other processes. The material and process of the free layer are roughly similar to the fixed layer. For example, the free layer may include NiFe, NiFeC〇, CoFe, Fe, Co, Ni, alloys or compounds of the above materials, and/or other ferromagnetic materials, and the free layer may also pass CVD, PECVD, ALD, PVD. Formed by electrochemical deposition, molecular manipulation, and/or other processes. However, the free layer may not be connected to the antiferromagnetic material, so the direction of the magnetic moment of the free layer can be changed. For example, the magnetic moment of the free layer can refer to more than one direction. In one embodiment, the free layer may comprise a plurality of layers, such as a spacer layer interposed between two to several ferromagnetic layers. Thus the free layer can be or comprise a composite antiferromagnetic layer. Sub-line W1, W2, bit line B1-B4 'wire A1-A4 and A1 '-A4', read line R1, R2 can be conductive lines, including conductor body (four) conductor and ciadding layer ). The conductor body may be formed by CVD, pecvd, ALD, PVD, electrochemical deposition, molecular manipulation, and/or other processes, and may include Cu, Al, Ag, Au, W, the gold of the 0503-A31218TWF 13 1273596 / Chemical, or other materials. The conductor body may also include a diffusion barrier layer composed of Ti, Ta, TiN, D-A, or/, and other materials. The composition and system of the cladding layer can be roughly similar to the free layer. For example, the overlay can include

NiFe, NiFeCo, • C is an alloy or compound thereof, or other ferromagnetic material, and can be formed by CVD, + ALD PVD, Wei Xue deposition, molecular manipulation, and/or other processes. When t胄 people remember the fresh elements, the red magnetic field strength of the (4) line and the word line is enough to change the state of the memory unit. For example, in the case of performing a write operation on a memory single capture, a word line can be selected, and a write current is applied to the top of the wire, and the write current is captured by the Iw2 on the bit line (1). Up, while other lines can be grounded. To read a certain _memory unit, for example, the fiber unit (u), (4) the sinusoid line, and apply the read p νιΆ stomach above the line R1. The read current can then be sampled from the read line ri. When the reading operation is performed, the reading current Irl can be maintained for a while on the reading line. The current can be excited-adjusted on the wire AU and the read current μ of the read line is sampled. The current reading current η and the adjusted read current 可 can be tempered to determine the logic state of the memory cell (5). The adjustment current Iadj can then be eliminated. Referring to Fig. 9, here is a partial cross-sectional view of the embodiment of the memory cell array_ in Fig. 8. The memory cell array 800 can include a substrate 105, and one or more open/close elements UOa-llOh formed in the substrate. For example, the portion of the memory cell array _ in FIG. 9 includes switching elements 110a, 11b', wherein the switching element 110a, which is a transistor, includes a source 'no pole 115 formed in the base, 105, And an interpole 117 above the substrate. Although the second figure in Fig. 9 shows that the interpole 117 can be directly or indirectly connected to the word line w as shown in the eighth figure, the diode can be used instead of the switching element 11〇a_11〇h. Crystal. The material of the base material 105 may include Shi Xi, Kun Rong, gallium nitride, tension stone, crystal, stone, stone, diamond, diamond, and/or other materials. In one embodiment, the substrate 1〇5 comprises 矽^mM(SOl^ silicon-on-insulator)*#, 〇n sapphire), a silicon germanium on inSUlator substrate, or other In the insulating layer 0503-A31218TWF 14 1273596 • The substrate of the upper epitaxial semiconductor layer. Substrate 105 may also comprise a fully depleted tantalum insulating substrate having an active layer of 511δ in the range of 511111 to about 2 (10) nm. The substrate 105 can also include an air gap, such as an air gap formed in a silicon on nothing (SON) structure. The portion of the memory cell array 800 shown in Fig. 9 also includes bit lines B1, B2, wires A1-A4' and read line R1. Figure 9 also more clearly illustrates how the write line 19 can be used to program the tunnels 120a-124d, which may be applied to the conductor A1_A4 in the process. The memory cell array 800 can also include an interconnecting line 140 for connecting the magnetic tunneling junction stacks uoa-uod in parallel to the read line R1, and the interconnecting line 150 for connecting the write lines 19〇. a source/no-polar region 115 to the switching element 110a, 11b; and an interconnect 16 〇 for connecting the bit line, B2 to the source/drain region of the switching elements 11a, 11b Ip15. The interconnects 140, 150, 160 can extend across one to several dielectric layers to connect to switching elements 110a-110h, bit lines B1-B4, read lines Ri, R2, wires A1_A4, A1, _A4, characters Lines W1, W2' are written to line 190, or features in other memory cell arrays 8'. For example, the interconnects 150, 160 can connect the write line 190 to the bit lines B1, B2' via the switching elements i1a, 11b, where the write line 190 can be adjacent to the magnetic tunneling stack, so that The current between the bit lines B1 and B2 is programmable to stack the uoa-uod of the magnetic wear-fed surfaces. The material of the interconnecting wires 140, 150, and 0 160 may include copper, tungsten, gold, aluminum, and carbon nanotube transistors (Carb〇n Nan〇_Tube, ^^^, carbon cluster (four) out (10)^^ generation^ Refractory metal ~ or other material 'which may be formed by ^ ^, PECVD, ALD, PVD or other processes. The dielectric layer may include ruthenium dioxide, BLACK DIAMOND (product of Applies Material), or other materials, and may be Cvd, PECVD, ALD, PVD, spin-on coating, or other processes are formed. As in the above-mentioned implementation of the write-on unit (1, 1), the word line Wi can be selected. The conductive crystals 110a, 110b are electrically connected so that the write current Iw2 applied to the bit line B1 can flow to the write line 190 (in this operation, the bit line B2 can be grounded). The current lwl is above the wire A1, so the magnetic field generated by the current flowing on the wire A1 is sufficient to be 0503-A31218TWF 15 1273596: to program the memory cell (u). Since the wire A1_A4 can be used together with the write line 19 In order to change the magnetic wear-through surface and 120a-120d, the wire A1_A4 here may also be referred to as a write line. The incoming line A1_A4 and the write line 190 may also be referred to as a programming line. Refer to Figure 1 for a partial plan view of the memory cell array _ in Figure 9. Each of the wires A1-A4 may be substantially perpendicular to the write. The access line is 19 〇. Each of the magnetic wear-and-match surface stacking _ can have a substantially hard axis that is parallel to the write line 19G, and the line is parallel to the easy magnetization axis of the corresponding wire A1-A4. The arrangement direction of the wearable surface can be roughly parallel to the difficult Wei axis, such as the 1G K. The magnetic axis is perpendicular to the magnetic moment of the fixed layer. _ β *考第8-10, the memory cell array _ may include a plurality of stacked groups 17 〇. Each stack 170 may include a plurality of parallel magnetic tunnel junction stacks. For example, in the 9th and 1st drawings The stacking group 170 includes four magnetic tunneling junction stacks 12〇a]2〇d, at which time Ν = 4. However, ν may be any integer greater than the current riding and implementation crane. #Reading, reading The value of the current reflects the value of the parallel resistance in the selected stack 17〇, thus eliminating any leakage current (such as in a conventional form of cross-point memory array) The leakage current). Therefore, the component density of the early memory array in the fourth picture can be as high as the conventional cross-point array, but the leakage current problem in the intersection memory cell array can be avoided. Turning to Item 11 is illustrated as a flow diagram of a non-destructive method 1100 of a ratchet clock in accordance with the present invention. Method 1100 includes step 21, in which one or more word lines or bit lines are selected for selection. - Memory unit. The remaining lines can be grounded. In step 22 (), detecting and maintaining - reading current Ir in step 23, applying an adjustment current to the braided or smashed line of the memory unit read in the step, The magnetic field is generated by the direction of the hard axis of the recording element. In step 240, when the current is applied, the current M is _. Next, in step 250, the values of current ΐΓΐ and Ir2 are compared to identify the state of the memory cell being read. The vector 205 in Figure 11 illustrates the magnetic field along the hard-to-magnetize axis of the memory cell being read.

0503-A31218TWF 16 1273596 • Adjust the direction of the magnetic moment of the free layer. In step 260, if the value of the second current Ir2 exceeds the first current Irl, the original magnetic moment direction of the free ferromagnetic layer of the magnetic tunneling interface memory element is 4 and the magnetic of the fixed ferromagnetic layer. The opposite direction of the moment. Therefore, the direction of the magnetic moment of the original free layer and the fixed layer is not parallel, so the read magnetic tunneling plane bits are not parallel, as shown in step 27〇. If the value of the first current Irl exceeds the second current Ir2, the original magnetic moment direction of the free ferromagnetic layer of the magnetic tunneling interface memory element read is in the same direction as the magnetic moment of the fixed ferromagnetic layer. Therefore, the original free layer and the fixed layer have the same magnetic moment direction, so the read magnetic through-plane bits are parallel, as shown in step 275. In step 280, the adjustment current "can be eliminated." In an embodiment, the adjustment current Iadj can correct the magnetic moment of the free layer by an acute angle, such as 45 degrees, without changing its state. Figure I2 shows the eighth Another aspect of the memory cell array of the figure is referred to herein as a memory cell array. The memory cell _ 12 (8) of the fourth (fourth) is substantially similar to the memory array 800 of Figure 8. However, the stacked group of Figure 8 is The simplification is shown in Figure 12. Each stack 170 includes N magnetic tunnel junction stacks 120 that are connected in parallel to their corresponding read lines R1, R2. The number N can be an integer greater than 。. Each of the magnetic tunneling plane stacks 12 位于 in the stacked group 170 can be serially connected to a write line, such as the write line 190 in the ninth and first figures. For example, the write lines 190 connecting the magnetic tunnel-through stacks 4 120 in the stack 17 可能 may be connected adjacent to the fixed or free layers of each of the magnetic-through-side stacks 4 (10). Each of the magnetic tunneling junction stacks 12〇 may be only close to but corresponding to the write lines Α-Αη, ΑΓ - Αη, phase-separated, wherein the number η of the write line A1-An in each stack group 17 is the same as the number η of the magnetic tunnel junction stack 12 。. Each stack group can be regarded as a three-terminal one piece Wherein the -end is connected to the corresponding read line, and the other end is connected to the bit line (eg, Bl_) via the switching element 11〇, and the other end is connected to the other via the other switching element 110 One bit line (for example, B2 or m). The switching element i 1〇 can be: to a plurality of transistors, diodes, or elements. ^ Figure 13 is another memory cell array of Figure 8 Part of the circuit diagram of the embodiment, 0503-A31218TWF 17 1273596 _·here represented by memory cell array · memory cell array · roughly similar to memory cell; array discussion. For example, 'memory cell array · including bit lines m, B2, The word line ^, I W2, the wire such as "meal but the memory cell array touch also includes the reverse bit fine, B2' and the reverse word line wi,, W2, - memory _ _ may include the stacking group 17G, wherein the _end of each stack is connected to the 7G line or the reverse bit line via the switch 70, and the other end The point is connected to the same-bit line by the other_off element, and (4)-the end is recorded to the other line in the (four) line series. For example, the memory unit array is called the memory unit A stacking group 170 may be included, the terminal end of which is connected to the bit line m via the switching element m〇a, wherein the gate of the switching element is connected to the word line of the word line w and the other of the stacked group m of the memory unit An end point may be connected to the bit line m via the intestine element 13, wherein the switching element 13 is substantially connectable to the reverse word line W1. The other end of the stacked group 17G in the memory unit 13G5 may be connected to Reverse bit line Bl'. In the implementation of the write operation of the memory bank 7G 1305, the reverse word line W1 can be selected, and a write current Μ can be applied to the wire A1. Then another write current w can be applied to the bit line B1, and the other lines can be grounded. In the implementation of the read memory unit 13A5, the sub-element line w can be taken and the read voltage Vr applied to the bit line B1. Other lines can be connected to the ground. Then, a read current M is maintained on the bit το line B1, and the value is detected. In addition, the current Iadj can be excited-adjusted on the wire A1, and then the adjusted read current Ir2 on the bit line m is detected. Next, the values of the read currents Irl and fr2 are compared to discriminate that the memory unit 13 is still in a state. Then the adjustment current Iadj is eliminated. Fig. 14 is a partial circuit diagram showing another embodiment of the memory cell array 8A in Fig. 8, which is shown here by the memory cell array moo. The memory cell array 14 is substantially similar to the memory cell array 800. For example, the memory cell array includes a bit line B1_B4, and the word line W is W2' wire Α1-Αη, ΑΓ-Αη'. However, the memory cell array, j 14 〇〇 also includes the inverted bit line ΒΓ-Β4', the reverse word line W1', W2, and the line Α1,, -Αη,,.

0503-A31218TWF 18 1273596: m==rn4GG also includes stacking group 17G, where each - stack of 4 groups, connected, '3 line shot', its other - endpoint axis _ element, or reverse bit line The other _, while the other end of the axis - the component is connected to another $. 兀 line to f position. For example, the memory unit 14A of the memory unit P train 14g can include a stack a: a group 170 whose end point is connected to the reverse bit line B1. The other end of the stacking unit 170 can be connected to the bit line B1 via a switching element (4) 〇a, and the gate of the neutral switching element (4) 〇a can be connected to the reverse word line wi. The other end point of the stacking unit 170 of the memory unit can be connected to the bit line B2 via another switching element 14·, wherein the gate of the switching element 1410b can be connected to the reverse word line ^. Another memory cell array 1 can include a stacking group 17〇 with an end point connected to the reverse bit line pull. The stack in the memory cell το 1407, the other end of the group 170 can be connected to the bit line B2 via a switching element, wherein the gate of the switching element can be connected to the word line %b. The other end point can be connected to the bit line B3 via another switching element (4) 〇d, wherein the gate of the switching element 1410d can be connected to the word line W1. In the implementation of the write operation to the memory unit 1405, the reverse word line wi' may be selected and a write current Iw1 may be applied to the wire A1J1. Then another write current can be applied to bit το line B1, and other lines can be grounded. In the implementation of the read memory cell, _ may select the reverse word, line W1, and apply the read voltage Vr to the reverse bit line β1. Other lines can be grounded. Then, on the reverse bit line B1, it is possible to hold - the current Μ and its value. In addition, the current Iadj can be excited-adjusted on the wire A1, and then the adjusted read current 上 is detected on the reverse bit line β1. The values of the read current and M are then compared to identify the state of the cell 1405. Then the adjustment current I峋 is eliminated. Fig. 15 shows a partial circuit of another embodiment of the memory|element array 14A of the 14th, which is represented here by the memory cell array 1500. The memory cell array 15 is substantially similar to the memory cell array 1400. For example, memory cell array 1400 includes bit lines Bi_b4, B1, _B4, word lines W1, W2, W1, W2, and lines Al-An, AKAn, A1, _An". 0503-A31218TWF 19 1273596 The door closing 15GG also includes a stacking group 17G, which is connected to the end point of the arm-to-boot group via an anti-two-twist line and an inverted bit line, and the other end point is connected to the bit line ΐΐίΓΓ-bar. The other end point is connected to another bit spoon via the other switch element, and the unit 1505 can be connected to the reverse bit via the simple element 151Ga. Line B1,, the gate of the male 10a can be connected to the reverse character line wi. The other of the memory unit Nazhong = 7G can be connected to the bit line B1. The stack of fresh Yuan Na towel (10) 1510b One piece of 151Gb is connected to the recording element line B2, and the gate of the radiation switching element=〇b can be connected to the reverse word line W1. Another memory of the memory unit array is detected earlier! 5〇7 can include a stacking group 17〇, one end of which is connected to the reverse bit line B2 via the switching element, 'where the gate of the switching element can be connected to the character, please. Memory unit The other end point of the stack group no in the blue may be connected to the bit line B2. The other end point of the stack group no of the memory unit face towel may be connected to the bit line B3 via another switching element 151〇d, wherein the switching element The gate of 15HM can be connected to the word line W1. In the implementation of the writing operation to the memory unit 1505, the reverse word line wi' can be selected, and a write current 施加 can be applied to the wire A1. Then another write current (10) can be applied to the bit line B1, and other lines can be grounded. In the implementation of the read memory unit 15〇5, the reverse word line W1 can be selected and applied. Take the voltage Vr to the reverse bit line m, above. Other lines can lie down. When riding the reverse bit line B1, the current W can be read __ and its value can be side-by-side. Excitation of an adjustment current ^, and then on the reverse bit line βι, the adjusted read current Μ side. Then compare the read current w with the value to distinguish the state of the Lv memory unit 1505. Then eliminate the adjustment current j峋. Fig. 16 is a partial circuit diagram of the memory cell in the nth diagram _ just another embodiment. The memory cell array 1600. The memory cell array 16 is substantially similar to the memory cell array 1400. For example, the memory cell array 16A includes bit lines m, B2, and word lines W1, W2, W1, and W2. ,, and the wires Al-An, Al, -An,.

0503-A31218TWF 20 1273596 The memory surface is also covered with 17G, each shot - private n: off:: even! to the bit line, the other end point is connected to the word line or w. Via the other-switching element connected to the word line or the other of the reverse word lines, the number of openings in the array face of the Sense 70 can be a diode rather than a transistor. 22, the memory unit 1605 in the array 1600 can include a "stack group 170,1, wherein the open position can be or line W1, and the stack group 17G (four)-end point in the ice can be connected to the reverse The character is connected to the heap of the unit. Her 17G (four)-end point can be connected via the other-switching element sub-wi, where the switch member 16 is a transistor and its gate can be connected to the bit 7G line B1. You can choose the implementation of the person's action, you can choose the bit line B1, apply a write current Iw on the sub-A1, then apply another write current (four) to the word, other lines can be Ground. In the implementation of the memory unit, the sub-clause lines W1 and W1, ground, and the ink on all other word lines are added. Connect = Apply - Read % on bit line m and the other lines are off ground. Then, the motor Irl can be taken in the bit, , and the temple D, and the value is detected. In addition, an adjustment current can be excited on the wire A1! adj, and the adjustment on the bit line B1 is performed on the side of the line M. Then compare the value of _ electric ship and Ir2 to distinguish the state of the memory unit. Then, the adjustment current is eliminated. !adj ° The figure is a partial circuit diagram of another embodiment of the cell array 16A in Fig. 16, which is here a fresh element array 17GG. Memory unit _ New her in the memory unit array function. For example, memory cell array 17 (8) includes bit thin, B2, word line W1 W2 W1 W2 ', and conductors such as Ar-. The memory cell array (8) also includes 3 stacks s: group HG' where each - stack group - the endpoint is connected to the - in the word line or the reverse word line via the off element, and the other end is connected to the bit One of the line or reverse bit lines, and the other H is connected by the $switch element to the other of the bit line or the inverted bit line. memory

0503-A31218TWF 21 1273596 Several switch trees in a cell array can be diodes rather than transistors. For example, the memory unit 17 170 in the memory cell array 1700 has an end point that is connected via the switching element 1710c, and may or may include a minus (10) towel profile 1 element line m. The material 17 in the memory unit 17.5. The other end point of = 17° can be connected to the bit m〇d is connected to the reverse bit line B1, and the end point can be connected to the reverse word line w via the other switching element. The turn-off surface is a transistor, and the gate can be connected to the 17G5 for writing the field for a bribe. The bit line m can be selected, and the write-write current is 1W1. Then another write-on-write can be applied to the word :wi, and other lines can be grounded. In the implementation of reading the simple element, all the reverse words are read, for example, W1, and W2, and the light without words (such as w and W2) is increased to Vdd. Then apply - read the cage force on the bit line, 1 and the line including the word line W1 is grounded. Then, it is possible to hold - read · IH on the bit line Bi and gamma it. In addition, the current can be sensed on the wire A1, and the adjusted read current M on the line B1 is detected. Then compare the read current plus the value to distinguish the state of Shixianit 17G5. However, the adjustment current τ (four) is eliminated. Fig. 18 is a partial circuit diagram of another embodiment of the memory cell array 17A in Fig. 17, which is referred to herein as a memory cell array 18A. The memory cell array face is roughly similar to the memory array 1700. For example, the memory cell array 18A includes bit lines m, Β2, and word lines Wb'' wires Α1-Αη, ΑΓ-Αη'. However, the memory cell array 18A also includes bit lines Β3, Β4, reverse word lines wl, _〇, W1, _e, number, _〇, W2, _e, wires αι, ▲". Each word line (e.g., W1) in array 1800 may correspond to two reverse word lines (e.g., Wl '-o, Wl'-e). For example, an odd number connected to word line W1 The memory unit can be connected to the reverse word line W1,-0, and the even number of memory cells connected to the word line W1 are connected to the reverse sub-line W1'-e. However, connected to a character The memory cells of the line do not need to be equally connected to the corresponding different reverse bit lines, so the equal distribution shown in Figure 18

0503-A31218TWF 22 1273596, the shape (each reverse bit line is reduced with 5G% of memory cells) is not necessary. In addition, each sub 7L line may have more than two corresponding reverse bit lines (eg, wi, 丨, wi, _2, wi, _3). The memory cell array surface also includes a stacked group 17〇, wherein one end of each stacked group is connected to the strip of the word line to the word line via the off 7L piece, and the other end point is connected to the bit element. Another H is connected by another switching element to another bit line. The plurality of switching elements in the memory cell array 1800 can be diodes rather than transistors. For example, the memory unit touched by the memory cell array may include a stacked group whose end point is connected to the word line wi via the switching element 181A, wherein the switching element 1810a

: Includes - polar body. The other end of the stack group i7G in the memory unit 18G5 can be connected to the bit = B1 ' and the other end point can be connected to the bit line via the other - switching element · b to pull the component into a transistor, which The gate can be connected to the reverse character _, _. . The memory unit ^Q in the memory unit 18Q7t includes a stacking group i7Q, which is connected to the sub-element W1 via the switch m_, wherein the off element (8) 〇e can be or include a diode. The other end of the stacking group η〇 of the remembering το(10)7+ can be connected to the bit line Μ, and the other side is connected to the bit line Β3 via the other-off element surface, wherein the closing element surface is an electric body 'The gate can be connected to the reverse word line Wl, _e. ;,,? In the implementation of the write operation of the hidden unit 18〇5, the bit line can be selected.

, a ': a write current Iwl is applied to the wire A1. Then another write current can be applied - up to the word ^W1, and other lines can be grounded. In the implementation of the read memory unit, the ^ word line (eg, W1, _., W1, _e, W2, _, w2, _e) is grounded, and all of them are: The voltage on W1 and W2) is increased to. Then, a read voltage % ώΛ ^ Β 1 is applied to the other line including the word line W1 to be grounded. Then, the current Irl can be read and read on the bit line, and the value is detected. In addition, the read current 1!"2 after the machine is activated on the lead 激发, and the two are given the B1 on the machine. Next, compare the values of BET ~ 'IL Irl and lr2 to distinguish the state of the memory cell (10) 5. Then, the adjustment current is eliminated. 0503-A31218TWF 23 1273596 FIG. L is a partial circuit of another embodiment of the hexadecimal cell array 17GG in FIG. 17 = again a memory cell array 1900. The memory cell array 1900 is generally similar to the singular array trace. For example, the memory cell array includes bits $w, W1, W2, W2, _ ΔΊ Λ 兀 ^ line ^ line A; UAn, Α 1, - Αη,. However, the memory cell array also includes a few lines Β3, Β4, and a wire A1 "▲,,. ΗΜ^Γ"] 1900 170 5 IΓ1 ? 1900 彳 彳 end age is connected by another - 1% piece to another - A bit line. The next switch reading of the fresh element array can be a diode instead of a transistor. Some of the switching elements can be connected to the moon b. For example, the memory cell in the memory cell array 1900 can be Including a bunch of groups =, its - the endpoint is connected to the word line wi via the _ component, its _ element 19 and the version can or include the second return. The other unit can be connected to the pile of the m. In place = B1 ' and the other end point can be connected to the bit line B2 via another switching element (9)%, the surface of the switching element is a transistor, and the _ is connected to the material of the switching element, _ ^ The component is hidden from the stack of magnetic tunneling planes in the stacking group (7). The other memory unit in the HN early 7L array measurement may include a stacking group 17〇, one end of which is connected to the character via the switching component Line W1, in which the switching element can be = including a 2-pole body. The stacked group in the memory unit is _ the other end point can be connected to the bit Line one, and /, another end point may be connected to bit line B3 via another switching element 1910d, wherein switch read 1910d is a transistor with a pole connected to the end of the switching element, wherein the end point is at the switch The component 丨赃 is connected to the other end of the end point of the magnetic wear surface stack in the stack group 17G. In the implementation of the write operation to the memory cell Na, the reverse word line W1 can be selected and applied on the wire A1. A write current Iw can then apply another write current _ to the line 70 on line m. 'Other lines are grounded. In the implementation of the read memory unit (10) 5,

0503-A31218TWF 24 1273596 .= Bit 70, B1 and B2 are grounded and the voltage on all other bit lines is increased to ·. Then, a read voltage Vr is applied to access eπ ground. The other character axis reverse character line is connected. The receiver maintains a read current w on the reverse sub-element W1 and sets its value. In addition, the 'reading current W can be detected on the reverse word line W1 on the line A1 & send-adjust current ladj'. Then compare the states of the read currents M and M. Then the adjustment current Iadj is eliminated. L' Early The above embodiments provide various types of can arrays comprising a plurality of stacked groups and a plurality of wires. Each-stacking group includes N magnetic-piercing non-connecting surface stacks in parallel, and N is an integer greater than}. Each of the magnetic wear-receiving surface stacks includes a hard-to-magnetize axis whose direction is substantially parallel to the direction in which the N magnetic-piercing surface stacks are stacked. The plurality of wires are electrically non-positively subtracted from their corresponding or all of the N magnetic-piercing splicing surface stacks, and the extending directions of the wires are substantially perpendicular to the hard-to-magnetization axis of the f-magnetic tunneling junction stack. Embodiments of such MRAM arrays can include a plurality of stacks of panels, the stacks of which include, in addition to the above-described stack of magnetic wear-and-match surfaces, two electrical components that are electrically coupled to the scale-surface stack. One or both of the two elements may be a transistor or a diode. However, the array described in the following embodiments applies only one switching element to the plurality of magnetic tunnel junction stacks. Figure 20 is a schematic diagram of an electrical circuit of an array of magnetic tunneling junction memory elements in accordance with an embodiment of the present invention. The MRAM array 2000 includes data lines m, D2, bit lines m, B2, word line modulation, W2. The magnetic tunneling junction memory elements 61A, 61B, 61C, 6m are connected in parallel between the word line Wi and the node 63. Each of the magnetic wear-fed memory elements includes a free ferromagnetic layer 2〇2〇' fixed ferromagnetic layer 2040, and an insulating through between the free ferromagnetic layer 2〇2〇 and the fixed ferromagnetic layer 2〇4〇 Tunnel barrier 2030. The direction of the magnetic moment of the free ferromagnetic layer 2020 can be freely changed, the direction of the magnetic moment of the fixed ferromagnetic layer 2040 is fixed, and the insulating tunneling barrier 2 〇 3 〇 is an extremely thin insulating layer. The NMOS transistor of switching element 65 is connected between bit line B1 and node 63, which is controlled by the selected signal on the data line. In the embodiment of FIG. 2, the four magnetic tunneling junction elements 61A to 61D are all connected to the node 63. In addition to a one-node configuration (10) 0503-A31218TWF 25 1273596 magnetic wear-through surface elements can also be configured with one or three magnetic wear-through surface memory elements in one node. The programming lines A!, A2, A3, and A4 are respectively located in the corresponding magnetic wear-and-match surface memory elements 6ia, 6ib,

In order to write or change the state of the magnetic wear-receiving surface memory element 61A, an external magnetic field must be applied. This magnetic field size is the steady-state magnetic moment direction of the free ferromagnetic layer in the full-transfer magnetic wear-through surface-tracking member 6iA. The 21st part shows a partial cross-sectional view of the 2G financial circuit 2_. Section 22 is not a partial plan view of circuit 2_ in Figure 20. The circuit in Fig. 21 is formed on the substrate 70. In order to (4) write the person to the magnetic wear interface memory element 6u, select the word line - the I programming line A then apply the first write current Iwl on the selected word line (4), and apply the second writer The current Iw2 is above the selected programming line A1. The first _ writeer current μ produces a first-write human magnetic field near the selected character line W1. Second write current - produces a second write magnetic field near the selected programming line A1. As a result, the first and second write magnetic fields generated by the currents Iw1 and (10) form a combined magnetic field at the magnetic f-tunnel surface memory element ό1Α. In addition, the illustrated MRAM array circuit is provided on the substrate 70 to form an example of the layer to be applied. This method can be implemented purely several times to form a multi-layer structure of MRAM. For example, the two circuit arrays of Fig. 21 can be superimposed on the substrate 70. Therefore, the memory capacity of the chip can be increased by nearly two times.稳定 The direction of the stable magnetic moment of the free ferromagnetic layer is parallel to the axis of easy magnetization and perpendicular to the axis of hard magnetization. In Fig. 22, the hard magnetization axis is perpendicular to the extending direction of the program line A1. In another embodiment, the angle between the hard magnetization axis and the direction in which the programming line A1 extends is about 45 degrees, as shown in the Figure 23 of the Figure 236. The combined magnetic field of the first and second write magnetic fields has an intensity exceeding a low limit magnetic field sufficient to convert the direction of the free-form layer in the magnetic tunneling interface memory element of the written person. Then, the selected magnetic tunneling junction memory element 61 is stored in the "% towel J. The reading procedure of the MRAM array embodiment shown in Fig. 20_23 can refer to the process in the nth figure. First, in step 210, a bit line 对应1 corresponding to the magnetic flux-following surface element VIII to be read is selected, and a read voltage Vread is applied thereto. At this time, the data line D1 of the magnetic memory 0503-A31218TWF 26 1273596 - 胄 胄 面 memory element 61A is selected, and the word line corresponding to the read magnetic memory surface memory element 2, 61A is selected. W1 is grounded. Then, the switching element 65 is turned on, and the first read current w • μ is over the tl line, and the parallel arm arm element is finally turned to the grounded word line W1.羲 Next, in step 22, the first read current Irl is held and the read Μ is sampled by the sensing circuit 2〇1〇. Next, in step 23G, an adjustment current ^ is applied to the programming line A1 to generate a "wobble magnetic field" (the direction is along the direction of the hard magnetization axis of the magnetic wear-fitting surface element) to temporarily change the correspondence. The direction of the magnetic moment of the free ferromagnetic layer of the read magnetic miscellaneous surface of the programming line A1 = 61A. The oscillating magnetic field is smaller than the low-limit magnetic field, so the magnetic moment direction of the magnetic ray memory element 61A does not change permanently. In addition, the oscillating magnetic field has a non-zero component along the hard magnetization axis, so that the direction of the magnetic moment of the ferromagnetic free layer of the read magnetic flux-through memory element temporarily changes from an angle of 〇 to 如. Then, a second read current Ir2 is applied, which flows through the bit line m, the switching element 65, the parallel magnetic flux-passing surface memory, and finally flows to the grounded word line W in step 24, When the swinging magnetic field still exists, the sensing circuit 2010 holds and samples the second read current Ir2. It must be noted that in all of the embodiments disclosed herein, the adjustment signal (current or voltage) applied to generate the wobble magnetic field may permanently change the magnetic moment of the selected memory cell, depending on the circuit design and application. Party _ direction, rather than just providing alternative changes. In these implementations, the reading (and writing) of the memory unit can be considered "destructive" and additional steps must be taken to restore the read unit to the original magnetic moment. The sensing circuit 2010 then compares the first and second read currents, b, b2, in step 250. In step 260, if the second read current Ir2 is found to exceed the first read current rainbow, the direction of the magnetic moment of the free ferromagnetic layer of the read magnetic tunneling interface memory element before the swing current is converted is The direction of the magnetic moment of the fixed ferromagnetic layer is not parallel. Therefore, the direction of the magnetic moment of the original free ferromagnetic layer is not parallel to the fixed ferromagnetic layer, so that the original state of the magnetic tunneling surface memory element read is non-parallel, as shown in step 270. If the oscillating current is applied, the first is found.

0503-A31218TWF 27 1273596 \ 2 Take the current irl over the second read current Ir2, then the direction of the self-ferromagnetic layer of the read-to-connect memory device before the transition of the oscillating current is the same as the @定铁分层The direction of the magnetic moment. Level 2. Thus, the direction of the magnetic moment of the original free ferromagnetic layer is parallel to the fixed i magnetic layer, because the original state of the magnetic wear-fed memory element is parallel, as shown in step 275. = The resistance value (Rpresent) of the memory pocket of the real-purpose wipes under the application of the oscillating magnetic field can be expressed by the following formula (1): ^present = H ~~ (1 COS Θ) (1) Rl is a low resistance value of 70 pieces of magnetic teeth accompanying surface when the magnetic moment directions of the free ferromagnetic layer and the fixed ferromagnetic layer are parallel to each other; and ^ is the noisy direction of the free ferromagnetic layer and the fixed ferromagnetic layer Inequality (4), the magnetic perforation surface memory elementary high residual value, Θ is the angular change caused by the swinging magnetic field of the applied force. Then, in step 28, the adjustment current Iadj is removed, and the wobble magnetic field is removed. Since the oscillating magnetic field is smaller than the low-limit magnetic field of the stabilizing resistance of the magnetic flux-transforming surface memory element, the magnetic field of the free ferromagnetic layer is bribed to the state where the original magnetic field is applied by the crane. Therefore, after removing the oscillating magnetic field, the reading of the magnetic _ surface recording element (4) before the application of the stagnation of the sputum is not necessary. In the unit, this is not a "destructive" read. The Fig. 24 is a circuit diagram of an array 24 of magnetic flux-fed surface memory elements using only a single switching element in accordance with an embodiment of the present invention. The array 〇 includes a data line, a bit 7G line B1, and a B2 ′ word line W2. The magnetic tunneling junction memory elements 71A, 71B, and 7iD are connected in parallel between the bit line B1 and the node 73. Each of the magnetic wear-fed memory elements includes a free ferromagnetic layer 2420, a fixed ferromagnetic layer, and an insulating through barrier 243 between the free ferrosilicon and the fixed ferromagnetic layer 2440. The direction of the magnetic moment of the free ferromagnetic layer 242 can be freely changed, the direction of the magnetic moment of the ferromagnetic layer 244 is 眺, and the insulating wear is extremely thin with the barrier layer. The NM〇s transistor connection of the switching element 2450 is between the word line wi and the node.

0503-A31218TWF 28 1273596. The NMOS transistor is controlled by the selected signal on the data line D1. In the embodiment of Fig. 24, the four magnetic tunneling junction elements 71A to WD are all connected to the node? 3. In addition to - node matching =, 4 magnetic wear-through components, can also be configured - 2 or 3 magnetic wear-through memory elements. The programming lines A, A2, A3, and A4 are respectively located in the vicinity of the corresponding magnetic wear-and-match surface memory elements 7ia, 71B, 71C, 71D. In addition, the sensing circuit 241 detects current flowing through the bit lines B1 and B2 when performing a read operation. In order to apply the first write current Iw1 to the selected character line and apply the second write The current Iw2 is above the selected L programming line A1. The first write current 产生 produces a first-write magnetic field near the selected word line W1. The second write current Iw2 produces a second write magnetic field near the selected programming line A1. As a result, the first and second write magnetic fields generated by the currents Iw1 and 〖^^ are at the interface of the tunneling surface memory element 71A, and the combined magnetic field is sufficient to free the magnetic tunneling interface memory element 71A. The direction of the stable magnetic moment of the ferromagnetic layer is completely changed. (Refer to Figure 22) The free iron-like shape of the Weifang is solved in (4) the axis of the axis is perpendicular to the axis of hard magnetization. In some implementation of the rags, it is difficult to extend the direction of the __A1. In other embodiments, the angle between the hard magnetization axis and the direction in which the programming line A1 extends may be 45 degrees. The combined magnetic field of the first and second written magnetic field has a strength exceeding a low-limit magnetic field, and the low-limit magnetic field strength is sufficient to convert the stable magnetic force of the free ferromagnetic layer in the magnetic-wearing interface memory element to be written Moment direction. The binary data stored in the selected tunneling interface memory element 71A is then stored. The reading procedure of the MRAM array embodiment shown in Figure 24 still follows the steps described in Figure u. f first selects the bit line B which is believed to be read by the magnetic wear-fed surface element 7 and applies the read voltage Vread thereto (step training). Next, the data line corresponding to the read magnetic via lands 116A is selected, and the word line W1 corresponding to the read magnetic tunnel junction memory element 71A is grounded. Then the switching element is turned on, and the first read current flows through the bit line, and the parallel magnetic flux-engaging surface memory element and the switching element are the most

0503-A31218TWF 29 1273596 The word line w after flowing to the ground is then held by the first read current Irl and sampled by the sensing circuit to sample the read current Irl (step 22G). Then, a biliary current is applied to the wire A1 to generate a lion magnetic field to temporarily change the direction of the magnetic moment of the ferromagnetic layer of the read magnetic tunneling interface memory element 71A corresponding to the programming line (step 23). 〇). Here the swing magnetic field strength is less than the strength of the low limit magnetic field. Moreover, the wobble magnetic field has a non-zero component along the hard magnetization axis, and thus the direction of the magnetic moment of the iron free layer of the magnetically abutting memory element being read temporarily transitions from an angle of 0 to 90 degrees. Then, the second reading of the cake, the flow line m, the magnetic parallel connection of the memory element, the switching element 2450, and finally to the grounded word line. Then, there is still a stalk in the oscillating magnetic field, and the sensing circuit 241 〇 holds and samples the second reading current step. The first and second read currents .Ir2 are then compared by the sensing circuit 24H) (step 25A). In step 260, if the second read power and the current Ir2 are found to exceed the first read power and the flow fri, the read magnetic tooth tunneling surface 6 has been converted to the swing current, and the original The direction of the magnetic moment of the free ferromagnetic layer is not parallel to the direction of the magnetic moment of the fixed ferromagnetic layer (step 27A). If it is found that the first read current Irl exceeds the second read current Ir2, the magnetic moment direction of the original free ferromagnetic layer is the fixed iron before the read magnetic tunneling interface memory element 81A is transformed by the swing current. The magnetic moment directions of the magnetic layers are parallel (step 275). Since the second read current Ir2 can reflect the overall resistance value between the node 63 and the word line W1 Lu, and the overall resistance value has changed due to the influence of the swinging magnetic field on the magnetic tunneling interface memory element, it is stored in the received The data of the read magnetic tunneling interface memory element can be obtained by comparing the values of the first read current Irl and the second read current Ir2. The swing magnetic % is then removed (step 280). Since the wobble magnetic field is smaller than the low-limit magnetic field of the stabilizing resistance of the switching magnetic tunneling interface memory element 71A, the magnetic field direction of the free ferromagnetic layer returns to the state where the wobble magnetic field was not originally applied. Then, after the wobble magnetic field is removed, the resistance value of the magnetic tunneling interface memory element 71A to be read is the same as the resistance value before the application of the wobble magnetic field. Therefore, it is not necessary to separately write the original data into the memory unit to be read after reading the program.

Figure 25 is a circuit diagram of an array 2500 of magnetic tunneling junction memory 0503-A31218TWF 30 1273596 using only a single switching element in accordance with an embodiment of the present invention. The mram array 25A includes a data line Db D2, bit lines B1, B2, and a word line w. The magnetic tunneling junction memory elements 81A, 81B are connected in parallel between the node 82 and the node 83, while the magnetic tunneling interface memory elements 81C, 81D are connected in parallel between the node 82 and the bit 70 line B1. Here, the parallel magnetic tunneling junction memory elements form a magnetic tunneling junction memory component group, and the plurality of magnetic tunneling junction memory component groups are connected in parallel. For example, the magnetic tunneling interface memory element 81 and the 813 form a first magnetic tunneling junction memory element group, and the magnetic tunneling interface memory elements 81C and 81D form a second magnetic tunneling junction memory element group. The first magnetic tunneling junction memory element group is in series with the second magnetic tunneling junction memory element group. In another embodiment, the magnetic tunneling interface memory elements 81A and 81B are connected in series to form a first magnetically modified f-tunnel surface memory element group, and the magnetic tunneling interface memory elements S1C and S1D are connected in series to form a second magnetic field. The tunneling interface memory element group is tunneled, and the first magnetic tunneling surface memory element group is connected in parallel with the second magnetic tunneling surface memory element group, as shown in the array 26 of FIG. However, in this different mode, the connection mode of other signal lines is still the same as that shown in Fig. 25, for example, the lean line D1, the bit line Β1, the word line w, the programming line Α1~Α4 . In the embodiment of Fig. 25, the magnetic tunneling interface memory elements 8a and 81]3 are disposed below the node 83 and the magnetic tunneling interface memory elements 81C and 81D are disposed below the node 82. Although each of the magnetic tunneling interface memory element groups includes only two magnetic tunneling interface memory elements in the present embodiment, each magnetic tunneling interface memory element group may also include more than two magnetic tunneling. Junction memory element. Each of the magnetically worn compliant surface memory elements includes a free ferromagnetic layer 2520, a fixed ferromagnetic layer 2540, and an insulating tunneling barrier 253 介于 between the free ferromagnetic layer 2520 and the fixed ferromagnetic layer 2540. The direction of the magnetic moment of the free ferromagnetic layer 2520 is freely variable, the direction of the magnetic moment of the fixed ferromagnetic layer 254 is fixed, and the insulating tunneling barrier 253 is an extremely thin insulating layer. The switching element 255 〇 电 8 transistor connection is between the word line W1 and the node 83, and the NMOS transistor is controlled by the selected signal on the data line ! The programming lines A1, A2, A3, and A4 are respectively located on the corresponding magnetic tunneling planes. It is near k, the vicinity of the elements 81A, 81B, 81C, 81D. In addition, the sensing circuit 2510 can detect the current flowing through the bit lines B1 and B2.

0503-A31218TWF 31 1273596 • In order to write data to the magnetic wear-and-match surface memory element 81A, the word line and the line Ar must be selected. The first write current Iw1 is then applied over the selected word line and the write current 1w2 is applied over the selected programming line Ai. The first-write current Iw1 produces a first write magnetic field near the selected sub-element W1. The second write current Iw2 produces a first write magnetic field near the selected programming line A1. As a result, a combined magnetic field is formed by the current and the generated first and second write magnetic fields at the magnetic f-connecting surface memory element 81A, the combined magnetic field having an intensity sufficient to magnetically penetrate the free ferromagnetic layer in the interface memory element 81A. The direction of the stable magnetic moment is completely changed. The direction of the stable magnetic moment of the free ferromagnetic layer is parallel to the axis of easy magnetization and perpendicular to the axis of hard magnetization. In this case, the hard magnetization axis is perpendicular to the extending direction of the programming line A1. In other implementations t, the angle between the hard magnetization axis and the direction in which the programming line A1 extends may be 45 degrees. The combined magnetic field of the first and second write fields has a strength exceeding a low limit magnetic field, the low magnetic field strength being sufficient to convert the stable magnetic moment of the free ferromagnetic layer in the magnetic tunneling interface memory element being written direction. Therefore, binary magnetic data is stored in the selected magnetic tunneling interface memory element 81. The reading procedure of the MRAM array embodiment shown in Figure 25 still follows the steps described in Figure n. First, the bit line Β1 corresponding to the read magnetic tunnel junction memory element 81 is selected and the read voltage Vread is applied thereto (step 21A). Next, the data line D1 corresponding to the read magnetic tunneling interface memory element 81A is selected, and the sub-element W1 corresponding to the read magnetic tunneling interface memory element 81A is grounded. The switching element 2550 is then turned on, and the first read current Irl flows through the bit line B1, the parallel magnetic tunneling interface memory elements 81A_81D, and the switching element 2550, and finally to the grounded word line wi. The first read current Irl is then held and the read current lri is sampled by the sense circuit 2510 (step 220). Then, an adjustment current Iadj is applied to the programming line A1 to generate a wobble magnetic field for temporarily changing the direction of the magnetic moment of the free ferromagnetic layer of the read magnetic tunneling interface memory element 81A corresponding to the programming line gossip (step 23). 〇). Here the swing magnetic field strength is less than the strength of the low limit magnetic field. In addition, the oscillating magnetic field has a non-zero component along the hard magnetization axis, and thus the direction of the magnetic moment of the ferromagnetic free layer of the magnetic tunneling interface memory element to be read is temporarily 0503-A31218TWF 32.1273596. 〇 to an angle of 90 degrees. A second read current Ir2 is then applied, which flows through the bit line Β1, the magnetic tunneling junction memory element, 81A-81D, the switching element 2550, and finally to the grounded word line wi. Next, when the wobble magnetic field is still present, the sensing circuit 2510 holds and samples the second read current Ir2 (step 24A). The sensing circuit 2510 then compares the first and second read currents Irl, ir2 (step 250). In step 260, if the second read current Ir2 is found to exceed the first read current, the direction of the magnetic moment of the original free ferromagnetic layer before the read magnetic tunneling interface memory element 81A is converted by the wobble current. It is not parallel to the direction of the magnetic moment of the fixed ferromagnetic layer (step 270). If the first read current Irl is found to exceed the second read current Ir2, the direction of the magnetic moment of the original free ferromagnetic layer is fixed and fixed before the read magnetic tunneling interface memory element 81A is converted by the wobble current®. The magnetic moment directions of the ferromagnetic layers are parallel (step 275). Since the second read current ir2 can reflect the overall resistance value between the node 83 and the word line wi, and the overall resistance value has been changed to k due to the shadow of the magnetic tunneling interface memory element being subjected to the swing magnetic field, it is stored in The data of the read magnetic tunneling junction memory element can be obtained by comparing the values of the first read current Irl and the second read current Ir2. The wobble magnetic field is then removed (step 280). Since the oscillating magnetic field is smaller than the low-limit magnetic field of the stabilizing resistance of the magnetically oscillating surface symmetry element 81A, the magnetic field direction of the free ferromagnetic layer returns to the state where the oscillating magnetic field is not applied. Then, after the wobble magnetic field is removed, the magnetic resistance of the read magnetic tunneling junction surface element 81A is the same as the resistance value before the application of the wobble magnetic field. Therefore, it is not necessary to separately write the original data into the memory unit to be read after reading the program. It should be noted that in all of the above embodiments, a sensing circuit is used to compare the values of the first current M and the second current Ir2 to obtain the data stored in the target magnetic access interface memory element. However, it is also possible to obtain the data stored therein by measuring the voltage of the target magnetic tunneling surface memory element before and after the application of the oscillating magnetic field. The present invention, by way of example, introduces a method for writing and reading a memory unit in a non-destructive manner, including: (1) sampling and maintaining a first signal on a selected bit line; (2) along each complex # A magnetic field is applied to the hard magnetization axis of the memory unit of the interface, wherein the magnetic field is sufficient for selection

0503-A31218TWF 33 1273596 The lion in the direction of the Wei - between the G and the 9G degree, but the magnetic field is not enough; (3) in the __ position on the free ferromagnetic = 4' _ fine - bit line The second letter is sampled; (the first and the first are compared to identify the state of the selected bit. /, as above, it is necessary to understand that the embodiments are for illustrative purposes only and the scope of the invention is not The limitations of any of the above embodiments should be determined by the impediment or all of these ===:=:r:r and the technical field, 11_' although the title is "the invented sentence." In addition, Γ "I used to describe the so-called technical field in the title paragraph, and the heading of the 'cutting' heading was judged to be the conventional technology that has been accepted as = month. The description of the present invention should not be taken as a description. In addition, in the description of the present invention, =:=: contains a single:: quantity of the object. The invention is defined by the one-to-four item system. Value, to protect 1 too

Invention = scope. In all cases, the scope of such claims shall be determined in accordance with their own legal know- ‘not subject to the headings in the specification.思0503-A31218TWF 34 .1273596 ·· [Simple diagram of the diagram] Figure 1 shows the structure of the array of magnetic (4) junction elements of 2T1 disclosed by Tang's invention; • Figure 2 shows the circuit disclosed by the invention of Gallagher Figure 3 is a cross-point array disclosed by Pemer's hair, which contains a plurality of magnetic wear-and-match surface memory cells; Figures 4A and 4B are the resistive cross-point arrays flowing through the chemical system in Figure 3. Sensing and leakage current path; FIG. 5 is a mram configuration disclosed by Gogl's invention; FIG. 6 is a functional block diagram of an integrated circuit component including a memory cell array according to an embodiment of the present invention; FIG. 8 is a partial circuit diagram of a memory cell array according to an embodiment of the present invention; FIG. 9 is a memory diagram of FIG. 8 is a functional block diagram of a memory cell used in the memory cell array of FIG. 6; a partial cross-sectional view of a cell array; FIG. 10 is a partial plan view of the memory cell array in FIG. 8; FIG. 11 is a flow chart of a method of reading a memory cell according to an embodiment of the present invention; Another of the memory cell arrays FIG. 13 is a partial circuit diagram of another embodiment of the memory cell array in FIG. 8; FIG. 14 is a partial circuit diagram of another embodiment of the memory cell array in FIG. 8; FIG. 16 is a partial circuit diagram of still another embodiment of the memory cell array in FIG. 14; FIG. 17 is a memory cell in FIG. a partial circuit diagram of another embodiment of the array; FIG. 18 is a partial circuit diagram of another embodiment of the memory cell array in the πth diagram; FIG. 19 is another embodiment of the memory cell array in FIG. Part of the circuit diagram;

2 is a circuit diagram of a memory array of a magnetic tunneling interface memory element 0503-A31218TWF 35 .1273596 arranging a single switching element according to an embodiment of the present invention; FIG. 21 is a partial cross-sectional view of the circuit in FIG. Figure 22 is a partial plan view of the circuit of Figure 20; Figure 23 is a plan view of another portion of the circuit of Figure 20; 忆 = 24 Figure, according to the present invention (four) - the configuration of the single-off component of the magnetic Circuit diagram of the § 丨 阵列 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Figure 26 is a view for the twenty-fifth embodiment. Another group coupling of the magnetic tunneling interface memory element in the figure [Main component symbol description] 100~Tang 2T1R MRAM cell; 12~bit line; 15A, 15B~ programming line; 20A, 20B~memory Unit; 24A, 24B~word line; 300~Pemer cross point memory cell array; 31~ magnetic tunneling junction memory unit; 33~bit line; 10A, 10B, l〇C~ switching element; 14A, 14B ~ memory unit; 200~Gallagher circuit; 22A, 22B~bit line; 32~word line; 42A, 42B, 42C, 42D~ memory unit resistance Is~ sense current; 500~GogliMRAM; 51A, 51B~ Word line; S3, S4~ leakage current; 50~bit line; 51, 52, 53, 54, and 56, 57, 58~ magnetic tunneling interface memory elements;

Tr Tr2 ~ transistor; 600 ~ integrated circuit; 0503-A31218TWF 36 1273596

610~memory cell array; 630~interface; 650~input/output circuit; 710~magnetic wear-and-match surface element; 730, 740, 750~end point; (1,1)~memory unit; Β1·Β4~bit line;

Rl, R2~ read line; 620~array logic circuit; 640~other logic circuit; 700~MRAM memory unit 720~switch element; 800~memory cell array; Wl, W2~word line; Α1-Α4, ΑΓ- Α4, ~ wires 110a-110h~ switching elements; 120a-120d, 125a-125d, 130a-130d, 135a-135d~ magnetic tunneling junction stack;

105~substrate; 110a, nob~transistor; 115~source/no pole; 117~gate; 140, 150, 160~ interconnect; 190~ write line; 170~ stack group; 1100~read Non-destructive method of memory; 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900~ memory cell array; 110~ switching element; 120~ magnetic tunneling junction stack; 170~ stacking group; RJ, R2 ~ Read line; Α1-Αη, Α1'·Αη', ΑΓ-Αη~~ write line; Β卜Β2, Β3, Β4~bit line; Β1', Β2', Β3', Β4'~reverse Bit line; W Bu W2 ~ word line;

Wl', W2', Wl'-o, Wl'-e, W2'-o, W2'-e~ reverse word line; 1305, 1405, 1407, 1505, 1507, 1605, 1705, 1805, 1807, 1905, 1907~memory unit; 1310a, 1310b, 1410a-1410d, 1510a-1510d~ switching element; 1610a, 1710c, 1810a, 1810c, 1910a, 1910c~diode; 1610b, 1710d, 1810b, 1810d, 1910b, 1910d~ Transistor; 2000, 2400, 2500, 2600~MRAM array; 0503-A31218TWF 37 1273596 '2010, 2410, 2510~ sensing circuit; 2020, 2420, 2520~ free ferromagnetic layer; 2030, 2430, 2530~ insulation tunneling Barrier; 2040, 2440, 2540~ fixed ferromagnetic layer;

Dl, D2 ~ data line;

Bl, B2~bit line; W1, W2~word line; 61A, 61B, 61C, 61D, 71A, 71B, 71C, 71D, 81A, 81B, 81C, 81D magnetic tunneling interface memory element; φ A Bu A2, A3, A4~ programming line; 63, 73, 82, 83, 84~ node; 65, 2450~ switching element; 70~ substrate;

Iwl~first write current;

Iw2~second write current; ladj~ adjust current,

Irl ~ first read current; _ Ir2 ~ second read current. 0503-A31218TWF 38

Claims (1)

.1273596 X. Application for Patent Park: A kind of magnetic memory unit, in which each magnetic memory unit includes a stack of free iron cores, a layer of hiding between the first two, and a wall. And the magnetic field generated at the selected magnetic memory unit is greater than the intensity of the combined magnetic field. The array of the magnetic ray is used to: the magnetic memory unit of the flat complex number, and the dance is joined together. a plurality of first conductors respectively corresponding to each of the plurality of magnetic memory units for applying an adjustment signal adjacent to the selected magnetic memory unit during the reading operation, the adjustment signal generating a magnetic field The intensity is sufficient to change the magnetic moment of the magnetic memory unit of the county; the second wire is perpendicular to each of the plurality of first wires for applying the first read signal to, and the like, and the plurality of miscellaneous elements, and a magnetic memory unit for applying a second read signal to the plurality of magnetic memory units when the machine is applied to the selected memory unit; and the sensing circuit is coupled to the second wire for comparison The first read signal and the second read signal to distinguish the logic state of the selected memory cell. 2. The array of magnetic memory cells as described in the application specification, further including a switching element, The magnetic memory unit of the plurality can prevent the leakage current problem of the magnetic § 忆 早 早 70 when the switching element is turned off. ', 3. The magnetic memory single red _, as described in the second item of the patent, Wherein the switching element is a transistor 'including a gate, a first source/drain, and a second source/drain. 4. The array of magnetic memory cells according to claim 3, wherein the transistor is used The array of magnetic memory cells of claim 4, wherein the transistor is configured to provide the first signal when the selected signal is received. And a second read signal to the plurality of = magnetic = memory cells, and the third wire is used to provide a ground voltage to the plurality of magnetic memory cells to read the logic state of each of the magnetic memory cells. 0503-A31218TW The array of the magnetic memory unit of claim 4, wherein the transistor is used to provide a magnetic recording unit grounded to the fresh and plural number via the second wire when the transistor is used for the payment of miscellaneous money. The first line is used to provide a write signal to the plurality of magnetic memory cells to write a logic state to each of the magnetic memory cells. [7] The magnetic properties described in claim 3 of claim 4 An array of memory cells, wherein the transistor is used, fetched, or written to a logic state of a magnetic memory cell selected from the parent, wherein the polarity is coupled to apply a select signal to the transistor feed line, the first source level The second source stage is connected to the third wire, and the second end of the plurality of magnetic memory cells is coupled to the second wire. I 8· In the case of the female memory unit of the seventh item, the second wire is used to provide the first and second read signals to the selected signal. The magnetic memory of the plurality is early, and the transistor is configured to provide a ground voltage to the plurality of magnetic cells via the third wire to read the logic state of each of the magnetic memory cells. 9. The array of magnetic memory cells of claim 7, wherein the transistor provides a magnetic memory unit to the plurality of magnetic memory cells via the third wire when the selection signal is received by the transistor 2; The two wires are used to provide a grounding voltage to the scalar magnetic memory unit to write a logic state to each of the magnetic memory cells. _10. The array of magnetic memory units according to claim 1, further comprising two switches τ, respectively reduced to the two ends of the plurality of magnetic memory units, wherein the plurality of magnetic memory units are connected in parallel Between the switching elements. An array of magnetic memory cells as described in claim 1 wherein the switching elements are transistors. 12. The array of magnetic memory cells of claim 11, wherein the transistor is adapted to read or write a logic state of each of the selected magnetic memory cells, wherein the transistors The gate is coupled to a data line for applying a selection signal to the transistors, and the first source of the transistors is reduced to a third conductor corresponding thereto, and the second source/no pole of the transistors </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> In order to write a logic state to each of the magnetic memory cells. 2? The method for discriminating the logical state of the selected magnetic memory unit in the array as described in the scope of claim Z3, the towel can be used for the electric conduction, the current magnetic memory can be used for each of the selected magnetic memories. Extracting the logic state, the towel is the _ to the fox line, the first source/bungee face is connected to the first end point of the plurality of coma, and the second job is reduced to the word line, and the And a second end_to-bit line of the plurality of magnetic memory materials, wherein the bit line is connected to a comparison circuit that provides a comparison function. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; And a memory unit, wherein the second terminals are grounded through the transistor via the word to obtain a logic state of each of the magnetic memory cells. The method of selecting a magnetic memory unit according to the method of claim 27, wherein the write signal is applied to the memory unit via the word line through the transistor, and the second endpoint passes the bit tree Grounding to write logic complaints to the parent magnetic memory unit. m such as application for special _ u 卿 触 选 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The method of discriminating the logic state in the array described in the 30th item of the magnetic memory single μ patent range, the scale element is (4), the logic of the wedging and early =1=1=the 31th of the valve Memory unit 2:= When the transistor is turned on, it can read/write each of the selected magnetic logics (4), shoot the (four) tender __ to (10), and the crystal crystals 0503-A31218TWF 43 1273596 Two U, /; and extremely connected to the first - and second bit line, the second source level of the transistor is connected to the number of materials of the number of materials - the end point, the number of materials The first-known point of the unit is reduced by green, and t is taken, and the touch line is connected to the comparison circuit of the ship. ,. A method for discriminating the logical sorrow of a selected magnetic memory unit in an array as described in claim 32 of the patent scope, wherein the write signal is applied through the equipotential line through the isoelectric line, the plurality of magnetic memory sheets S, and the two-end series of the scaled crystals are read and lie by the first and second positions, and the reading and translating are separated from the fresh sugar state. 34. Shishin (7) is a method of selecting the logic state of the magnetic memory unit of the 32nd job of the 32nd job, wherein the person writes the magnetic force of the magnetic circuit through the scale line through the scale line. The memory unit, and the second end of the crane is grounded via the read line to write a logic state to each of the magnetic memory units. 35. A method of applying a logic state of a memory cell of the __Technology, wherein the first and second signals comprise a current or a voltage. 36. A method of identifying a logical state of a selected magnetic memory cell in an array as described in claim 21, wherein the magnetic memory cells are subtracted together in parallel. 37. A method of identifying a logical state of a selected magnetic memory cell in an array as described in claim 21, wherein the magnetic memory cells are subtracted together by φ wherein the first group of the plurality The magnetic memory cells are connected in series, and the second set of the plurality of magnetic memory cells are connected in series, and then the first group is connected in parallel with the second group of the plurality of magnetic memory cells. 3 port 8 · The method for discriminating the logical state of the selected magnetic memory unit in the array as described in claim 21, the step of applying the towel to the recording includes the near-frequently selected magnetic memory unit The strength of the money, the shot _ the whole money is only enough to temporarily change the direction of the magnetic moment of the selected fresh-keeping element, and after the adjustment record is removed, the Wei return line of the selected magnetic memory unit is applied before the adjustment number The original state. 39. A method of discriminating a logic state of a selected magnetic memory unit 0503-A31218TWF 44 1273596 in an array as described in claim 21, wherein the step of applying the adjustment signal comprises placing 40. If the scope of the patent application is 39 - / Qing ~ pillow plus ‘plus one is enough to adjust the signal of the selection. The method of logic state, wherein the acute angle is about 45 degrees. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A magnetic random access memory (MRAM) unit includes a magnetic tunneling junction (MTJ) stack having a plurality of stacked layers, and the adjustment signal is along a hard magnetic axis of the selected magnetic memory unit Apply a magnetic field. 0503-A31218TWF 45