4 1272531 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一參數可程式化之多位元真實亂數產生器，使用一平均器4 1272531 玖, invention description: [Technical field of invention] The present invention relates to a parameter programmable multi-bit real random number generator, using an averager
UormalizeO平均化渾_算法之參數，即可免於輸岐斂或錄，因此對於製 程飄移及工作環境具有高容許度，提升可靠度，並進一步使產生之亂數通過亂數測 試0 【先前技術】 近年來，麟及無線通訊的發展使得通訊的安全性格外地受㈣視，細其所慣用 之叙隨機IL數產生器(Pseudo Random Number Generator，PRNG)所輸出的序列雖然 很長，但仍是可制性和職性的。因此如何產生不可酬，無週期性的真實亂數 的數位序列成為密碼學的研究重點。不僅如此，在許多的科學及卫程領域中，亂數 產生器也應用於許乡的制儀n和模朗題上，例如SPICE之蒙地卡羅法。隨著 SOC的發展越來越普及，以频電路實_真實亂數產生^便大量的需要在通訊 晶片以及王程科學的應用P其中常用之手段為採用離散時間㈣演算法 (discrete-time chaos algorithm)^t^lL^±H^, (switch-capacitance)^^ M f ^(switch-current)^ft ^ ^ f ^ 較於開關f流主要的缺點在於面積大、雜辨纽速度鮮缺點，且電容受到製 程的飄移，常導致嚴重的錯誤。而先前提出的_電流電路，主要的問題在於取樣 與保持電路的偏壓（offset VGltage)及聽由於製程飄移紅作環境惡劣導致進入 發散或收斂的區間。 【發明内容】 本發明之-目的為-參數可程式化之纽元真實亂數產生器，使用—平均器 (normalizer)平均化渾沌演算法之參數，即可免於輸出收斂或發散，因此對於製 程飄移及王作環境具有高容忍度，錢—步可使產生之亂數通過亂數測試。 108268-950209.doc 1272531 為了達成上述之發明目的’本發明包括—平均器（n。—），其作料將輸入之 複數個位元數位亂數訊號平均化，其中平均化指輸出多個位元訊號之位元為高電位 的個數〜和之事件’其發生之機率相等；複數個線性取樣與保持電路（触肛 track and hold eircuit，LTH) ’翻以取樣輸人電流，並輸出參數倍電流魏入一下 級之非線性決定t路（nanlmeaf diseriminatiGneircuit，ND)，此參數倍❸電流藉由 複數個電晶谓控制；複數組雜性蚊，接收來自線性取樣與保持電路之 f出電流並據以判斷其正負，輸出多位^真實數位亂數，另一輸出藉由判斷輸入電 机之正負’輸出加上或減去參數倍H其巾此參數倍的糕藉由複數個電晶體 開關控制；-雜產以、（elQekge_tOT)，產生兩個互不重疊且互為反相的時脈 仏號，其作用系供應給線性取樣與保持電路使用。 為了達成本發明所揭示之產生亂數目的，前述平均器更進一步包括複數個反閘及複 數個反及閘，其全部没什為數位電路，其中時脈訊號控制複數組閂鎖器， 使輸出之多位元訊號與線性取樣與保持電路同步，其中輸出之多位元訊號其一目的 係用以控制線性取樣與保持電路的參數倍電流輸出，而多位元訊號之反相係用以控 制非線性決定電路的參數倍電流，提供非線性決定電路做加上或減去的動作。 為了達成本發明所揭示之一產生亂數目的，前述線性取樣與保持電路進一步包括複 數個電流源，其中包含三個電晶體構成之開關，二個取樣電容，目的係輸出電流為 輸入電流之參數倍，並根據開關決定參數。 因此’在一後文中所示之較佳實施例中，本發明所揭示之可程式化之多位元真實亂 數產生器由下列各組件所組成： - 一平均器（nomalizer ); 複數個線性取樣與保持電路（linear track—and-hold circuit，LTH); 複數個非線性決定電路（n〇nlinear discriminati〇n circuit，Nd); 日T脈產生器（clock generator )。 108268-950209.doc 1272531 【實施方式】 第一圖為本發明之一較佳實施例，其中可程式化之3位元真實亂數產生器1〇〇包 括：一平均器（normalizer) 101，三組1位元真實亂數產生器102, 103, 1〇4，其中 三組1位元真實亂數產生器102, 1〇3, 104分別包含了一組線性取樣與保持電路 (LTH)與一組非線性決定電路（nd)，因此共包含了三組線性取樣與保持電路 (LTH) 111，112, 113與三組非線性決定電路（ND) 121、122、123。一時脈產生 器（clock generator) 105。其中clock generator 105與習知技術並無不同，因此不 予贅述。在製造方法上，該真實亂數產生器100是由半導體製程所製造。 該平均器101係用以將輸入之複數個位元數位亂數訊號平均化，其中平均化指輸出 多個位元訊號之位元為高電位的個數總和之事件，其發生之機率相等。該等線性取 樣與保持電路111，112, 113用以取樣輸人電流，並輸出參數倍電流餽入—下級之非 線性決定電路，該參數倍的電流藉由複數個電晶體關控制。鱗雜性決定電路 12卜122、123用以接收來自該等線性取樣與保持電路lu，112, 113之輸出電流並 據以判斷其正負，輸出多位元真實數位亂數，另—輸出藉由判斷輸人電流之正負， 輸出加上或減去參數倍之電流，該參數倍的電流藉由複數個電晶體開關控制。該時 脈產生器105用以產生兩個互不重疊且互為反相的時脈信號，供應該等線性取樣鱼 保持電路使用111，112, 113。 〜 第-圖為說明！位元真實亂數產生器·，其中包含_線性取樣與保持電路⑽ 定電路⑽）2G2，並構成—鱗。公式⑴為之特性方程 ttr，參數5及參數福可程式化之參數，1衫二圖中線加 m η表7’哪(減為觸正負之縫。輸人訊細，D2, D3 鱗持電及參心，以職CLK1及CLK2躲性取樣 /、保持·(LT_之取樣時脈，輸_助τ為丨位元數位真魏數輸出 Ι(η+1) = 5·Ι(η) —isgn(I(n))..............公式⑴ 第一圖所示為第二圖之1位元直實數吝斗哭 25%, 八、 生2〇0之四條特性曲線，發生機率各為 圖-中參數歸本較佳實施例中為2,1J5, u，⑵。參數2在本實施例中為 108268-950209.doc 1272531 為相對於參數β調整之參數，並使電流χ在下—次離散時間㈣)為平均分佈在水 平轴之上下並符合合理之亂數。第一圖之平均器（n〇rmaiizer) 丨之輸出di，d2, /01，/〇2,/D3 ’其目的係使參數乂及万能等機率的發生，使輸出不致於收斂或 發散，達成本發明之機率均等分佈效果。UormalizeO averaging the parameters of the 浑 algorithm, can be free from transfer or recording, so it has high tolerance for process drift and working environment, improve reliability, and further make the random number generated by random number test 0 [Previous technology In recent years, the development of Lin and wireless communication has made the security of communication exceptionally subject to (4) view. The sequence output by the Pseudo Random Number Generator (PRNG) is still very long, but it is still Mandatory and professional. Therefore, how to generate an unrequitable, non-periodic, real random number sequence becomes the focus of cryptography. Not only that, but in many fields of science and defense, the chaotic generator is also applied to Xuxiang's instrumentation and model, such as the Monte Carlo method of SPICE. With the development of SOC becoming more and more popular, the frequency circuit is generated by the actual number of random numbers. In the communication chip and the application of Wang Cheng Science, the commonly used means is to use discrete-time chaos (discrete-time chaos). Algorithm)^t^lL^±H^, (switch-capacitance)^^ M f ^(switch-current)^ft ^ ^ f ^ The main disadvantage of the switch f flow is the large area and the shortcomings of the hybrid speed And the capacitance is drifted by the process, often leading to serious errors. The main problem of the previously proposed _ current circuit is the bias voltage of the sample and hold circuit (offset VGltage) and the interval of entering the divergence or convergence due to the harsh environment of the process drifting red. SUMMARY OF THE INVENTION The present invention is directed to a parameter-programmable neutron real random number generator that uses a normalizer to average the parameters of the hacking algorithm to avoid output convergence or divergence, thus The process drift and the Wang Zuo environment have high tolerance, and the money-step can make the random number generated by the random number test. 108268-950209.doc 1272531 In order to achieve the above object of the invention, the present invention includes an averager (n.-) which averages the input plurality of bit-number random signals, wherein averaging refers to outputting a plurality of bits. The number of bits of the signal is the number of high potentials ~ and the event 'is equal to the probability of occurrence; a plurality of linear sampling and holding circuits (acoustic track and hold eircuit, LTH) 'turned to sample the input current, and output the parameter times The nonlinearity of the current into the lower stage determines the t-way (nanlmeaf diseriminati Gneircuit, ND). This parameter is controlled by a plurality of electro-crystals. The complex array of mosquitoes receives the output current from the linear sampling and holding circuit. According to the judgment of its positive and negative, the output of the multi-bit ^ real number random number, the other output by judging the input motor's positive and negative 'output plus or minus the parameter times H, the towel times this parameter times by a plurality of transistor switches Control; - Miscellaneous, (elQekge_tOT), generates two mutually overlapping and mutually inverted clock nicks, the role of which is supplied to the linear sample and hold circuit. In order to achieve the random number disclosed by the present invention, the foregoing averager further includes a plurality of inverse gates and a plurality of inverse gates, all of which are not digital circuits, wherein the clock signal controls the complex array latch to make the output The multi-bit signal is synchronized with the linear sampling and holding circuit, wherein the output of the multi-bit signal is used to control the parameter multi-current output of the linear sampling and holding circuit, and the inversion of the multi-bit signal is used to control The nonlinearity determines the parameter's multiple of the circuit, providing a non-linear decision circuit to add or subtract. In order to achieve the random number of one of the disclosed inventions, the linear sampling and holding circuit further includes a plurality of current sources, wherein the switch comprises three transistors, two sampling capacitors, and the output current is a parameter of the input current. Times and determines the parameters according to the switch. Thus, in a preferred embodiment shown hereinafter, the programmable multi-bit real random number generator disclosed by the present invention consists of the following components: - a nomalizer; a plurality of linearities A linear track-and-hold circuit (LTH); a plurality of nonlinear discriminating circuits (Nd); a day-to-day clock generator. 108268-950209.doc 1272531 [Embodiment] The first figure is a preferred embodiment of the present invention, wherein the programmable 3-bit real random number generator 1 includes: a normalizer 101, three A set of 1-bit real random number generators 102, 103, 1〇4, wherein three sets of 1-bit real random number generators 102, 1〇3, 104 respectively comprise a set of linear sample and hold circuits (LTH) and one The group nonlinear decision circuit (nd) thus includes three sets of linear sample and hold circuits (LTH) 111, 112, 113 and three sets of nonlinear decision circuits (ND) 121, 122, 123. A clock generator 105 is provided. The clock generator 105 is not different from the prior art, and therefore will not be described. In the manufacturing method, the real random number generator 100 is manufactured by a semiconductor process. The averager 101 is configured to average the input plurality of bit-number random signals, wherein the averaging refers to an event of outputting a sum of a plurality of bit signals to a high potential, and the probability of occurrence is equal. The linear sampling and holding circuits 111, 112, 113 are used to sample the input current, and output the parameter multiple current feeding-lower nonlinear determining circuit. The current of the parameter multiple is controlled by a plurality of transistors. The scaly decision circuit 12 122, 123 is configured to receive the output currents from the linear sample and hold circuits lu, 112, 113 and determine the positive and negative, and output the multi-bit real digital random number, and the other output Judging the positive and negative of the input current, the output adds or subtracts the current of the parameter multiple, and the current of the parameter is controlled by a plurality of transistor switches. The clock generator 105 is operative to generate two clock signals that are non-overlapping and mutually inverted, and are supplied to the linear sample fish holding circuits 111, 112, 113. ~ The first picture is for explanation! The bit real random number generator, which contains the _ linear sample and hold circuit (10) fixed circuit (10)) 2G2, and constitutes a scale. Equation (1) is the characteristic equation ttr, parameter 5 and the parameter of the parameter Foucault, 1 line in the middle of the figure and m η in the table 7' which is reduced to the positive and negative seam. The input signal is fine, D2, D3 scale Electrical and reference, CLK1 and CLK2 evasive sampling /, hold · (LT_ sampling clock, input _ help τ is the 元 bit digits true Wei number output Ι (η +1) = 5 · Ι (η ) —isgn(I(n))..............Formula (1) The first figure shows the 1st digit of the second figure, the real number, the bucket, crying 25%, 八, 生2 The four characteristic curves of 〇0, the probability of occurrence are each of the graph-middle parameters, which are 2,1J5, u, (2) in the preferred embodiment. The parameter 2 in this embodiment is 108268-950209.doc 1272531 is relative to the parameter β Adjust the parameters and make the current 下 in the next-discrete time (four)) as the average distribution above the horizontal axis and meet the reasonable random number. The average of the first graph (n〇rmaiizer) 丨 output di, d2, /01 , /〇2, /D3 'The purpose is to make the occurrence of parameters such as parameters and omnipotent, so that the output does not converge or diverge, achieving the equal probability distribution effect of the present invention.
第四圖為線性取樣與保持電路圖（Uneartrack-and七〇ldcireuit，LTH),包括複數個 電流源、複數個電晶體構成之開關及二個取樣電容，該輸出電流為該輸入電流之參 數倍’並根據該等電晶體構成之開關決定該參數，此電路主要的功能是輸出 為參數倍的輸入Ιί>ί7)·。電流源4〇2為電流源4〇1的2倍，電流源403為電流源4〇1 的0.25倍’電流源404為電流源401的0.25倍，電流源405為電流源401的0.25 倍’電流源406為電流源4〇1的1.75倍。電晶體ΜΝ1與電晶體ΜΝ2大小為1:：1， 電晶體ΜΝ1與電晶體_3大小為1 : 1，電晶體ΜΝ1與電晶體ΜΝ4大小為1 : 0.25,電晶體ΜΝ1與電晶體ΜΝ5大小為1 :0.25,電晶體ΜΝ1與電晶體ΜΝ6大 小為1 : 0.25，電晶體ΜΝ1與電晶體ΜΝ7大小為丨：125。電晶體ΜΝΐ目的係感 測輸入電流Ur/，並改變電晶體ΜΝ1之閘源極電壓，CLK1訊號控制開關ΜΝ8， 進而取樣電晶體ΜΝ1之閘源極電壓，C1電容目的為取樣電容，進而改變電晶體 _2之閘源極電壓，並改變ΜΝ2之電流為Iq + Iw,·，因此ΜΝ3流過之電流改變為 ，進而在經過CLK2、C2電容與MN9取樣，同時改變MN4與MN5與MN6 與ΜΝ7之閘源極電壓，使流經ΜΝ4電流改變為0.25 (Iq-U)，流經_5電流改 變為0,25 (Iq-Im)，流經MN6電流改變為0·25 (IqU，流經MN7電流改變為 1.25 (Iq-Iw/)。其中時脈CLK1與CLK2為互不重疊且互為反相之時脈訊號，其輸 入來源由時脈產生器輸出饋入。 電晶體MN10與電晶體MN11與電晶體MNL2係作為開關之用，D1，D2，D3為控 制訊號，由平均器的輸出饋入，此三個電晶體開關控制輸出的電流為參數倍 的輸入電流，在本較佳實施例中，輸出的電流I⑽m可為1.25或1.50或1.75或 2倍的輸入電流Ι〜7ϊ。當電晶體MN10與電晶體MN11與電晶體MN12全部打開並 輸出電流Um·為2倍的輸入電流。當電晶體MN10與電晶體MN11與電晶體 MN12關閉其中任一個，並輸出的電流1⑽⑺為丨·75倍的輸入電流1/心。當電晶體 MN10與電晶體MN11與電晶體_12關閉其中任二個，並輸出的電流Um·為1.50 倍的輸入電流h心。當電晶體_10與電晶體MN11與電晶體MN12全部關閉’並 108268-950209.doc 4 41272531 輸出的電流Um為1·25倍的輸入電流Ι/ζιτ?。 ’ 第五圖所示為非線性決定電路（nonlinear discrimination circuit，ND) ’包括複數個 電流源及複數個電晶體構成之開關，此電路之目的係判斷輸入Ud/電流之正負，輸 出數位之真實亂數訊號，並進一步將輸入電流1/«/^作加上或減去參數倍電流的動 作，其中加或減的判斷是根據輸入電流1_的正負。當輸入電流Ι/Λ/)ί·為正，電晶體 ΜΡ21導通，電晶體ΜΝ22關閉，電晶體ΜΝ23導通，電晶體ΜΡ24關閉，節點 501為低電位，電晶體ΜΡ26導通，輸出DOUT；♦為高電位，進而電晶體ΜΝ27導 通’輸出電流為電流。當輸入電流Ι/ΤίΖ)/·為負，電晶體ΜΡ21關閉， 電晶體MN22導通，電晶體MP24導通，電晶體MN23關閉，節點501為高電位， 電晶體MN25導通，輸出DOUT,·為低電位，進而電晶體MP28導通，輸出電流U似 為電流I/w+(L-l6)。其中電晶體MP40, MN35與R構成一電流源502，其目的係供 應一參考電流I α。電晶體MP41，MP42, MP43, MP44構成一組電流鏡，其中電晶體 ΜΡ41，ΜΡ42, ΜΡ43為相同的大小，電晶體ΜΡ44的大小為ΜΡ41的8倍。流經 ΜΡ41，ΜΡ42, ΜΡ43的電流同為0.125倍的I α，流經ΜΡ44的電流為I α。其中電晶 體_36, ΜΝ37, _38, _39構成一組電流鏡。在本較佳實施例中，電晶體ΜΝ36, ΜΝ37，ΜΝ38為完全相同的電晶體，電晶體_39的大小為ΜΝ36的8倍。流經 _36，_37，ΜΝ38的電流同為0.125倍的Ια，流經_39的電流為Ifl。 電晶體廳29，讀30，臟31，画32，丽33，画34構成三組開關，其中續29與 _32以訊號/D1控制，MN30與_33以訊號/D2控制，MN31與_34以訊號 /D3控制。其中訊號/^,/02,/03為平均器之輸出。當/0^/02,/03任一訊號為高 電位其餘為低電位，則為〇·125Ια。當/Dl，/D2，/D3任二訊號為高電位其餘為低‘ 電位’則16為〇.25込。當/Dl，/D2，/D3訊號皆為高電位，則l為0.3751。 第六圖所示為平均器之架構，其中包含一數位邏輯601 ;同步開關602 ;三組栓鎖 态603。3位元真實數位亂數輸入D〇UTi，d〇UT2, d〇UT3分別為第一圖之121，122, 123的輸出，由於3位元真實數位亂數d〇UTi，d〇Ut2，d〇UT3為高電位的位元個 數的事件，其發生機率並非是等機率的發生^因此，平均器的架構係使輸出訊號 D1，D2，D3為高電位的位元個數的事件等機率的發生。其最終目的係使1；111之參 數倍電流為等機率的發生。同理，輸出訊號/Dl，/D2，/D3為高電位的位元個數的事 108268-950209.doc 1272531 件也會有賴率的發生，其最終目的雜之參數倍電料等鮮的發生。同^ p_0^係使平均li之輸出與三組LTH lu，112,113同步，並使用三組栓鎖器6〇3 輸出磁01，〇2,〇3，/〇1，/〇2，/〇3。事件等機率的發生。其最終目的係使則之 參數倍電流為等機率的發生。同理，輸出訊號肌鸣必為㈣位的位元個數的 事件也會有等機率的發生，其最終目的係使耶之參數倍電流為等機率的發生。同 步開關602係使平均器之輸出與三、组咖m，112,113同步，並使用三組检鎖器 6〇3 輸出訊號 Dl，D2, D3, /01，/02, /03。 為顯示此發明之優越性，本較佳實施例以台灣積體電路公司提供之㈣啤讀 製。程來實作。第七圖所示為3位元真實數位亂數輸出（tt_L2.5v， 25 C)，輸入時脈為10MHz。第一表列出輸出之亂數經由鹏刚·^的驗證結果， 並進一步列出角落（comer)的驗證結果。 工業上之摘用性 ^發明可適用於··無線通信系統之加解密晶片、電玩遊戲機、防盜裝置、樂透機器 择本發明可能分職不同、齡之實施方式職述、修改或實現，但仍不超出 本發明所提出之申請專利範圍。 【圖式簡單說明】 第1圖：本發明之較佳實施例； 第2圖：1位元真實亂數產生器； 第3圖：1位元真實亂數產生器之特性曲線； 第4圖：線性取樣與保持電路圖； - 第5圖：非線性決定電路圖； 第6圖：平均器電路圖；及 第7圖：較佳實施例之3位元真實數位亂數輪出。 【主要元件符號說明】 100 平均器 101 線性取樣與保持電路 108268-950209.doc •10- 1272531 102 > 103 > 104 1位元真實亂數產生器 105 時脈產生器 121 、 122 、 123 非線性決定電路 200 平均器 201 線性取樣與保持電路 202 非線性決定電路 203 線 401 電流源 402 電流源 403 電流源 404 電流源 405 電流源 406 電流源 501 節點 502 電流源 601 數位邏輯 602 同步開關電流源 603 栓鎖器 108268-950209.doc -11 -The fourth picture is a linear sampling and holding circuit diagram (Uneartrack-and seven-inch ldcireuit, LTH), including a plurality of current sources, a plurality of transistors formed by the switch and two sampling capacitors, the output current is a parameter multiple of the input current The parameter is determined according to the switch formed by the transistors. The main function of the circuit is to input the input parameter Ιί>ί7)·. The current source 4〇2 is twice the current source 4〇1, the current source 403 is 0.25 times the current source 4〇1, the current source 404 is 0.25 times the current source 401, and the current source 405 is 0.25 times the current source 401. Current source 406 is 1.75 times the current source 4〇1. The size of the transistor ΜΝ1 and the transistor ΜΝ2 is 1::1, the size of the transistor ΜΝ1 and the transistor _3 is 1: 1, the size of the transistor ΜΝ1 and the transistor ΜΝ4 is 1:0.25, and the size of the transistor ΜΝ1 and the transistor ΜΝ5 is 1 : 0.25, the size of the transistor ΜΝ 1 and the transistor ΜΝ 6 is 1: 0.25, and the size of the transistor ΜΝ 1 and the transistor ΜΝ 7 is 丨: 125. The transistor is sensing the input current Ur/, and changing the gate voltage of the transistor ,1, the CLK1 signal controls the switch ΜΝ8, and then the gate voltage of the transistor ΜΝ1, and the C1 capacitor is the sampling capacitor, thereby changing the electricity. The gate-source voltage of crystal_2 changes and the current of ΜΝ2 is Iq + Iw, ·, so the current flowing through ΜΝ3 changes to, and then samples through CLK2, C2 capacitor and MN9, while changing MN4 and MN5 and MN6 and ΜΝ7 The source voltage of the gate changes the current flowing through ΜΝ4 to 0.25 (Iq-U), the current flowing through _5 is changed to 0,25 (Iq-Im), and the current flowing through MN6 is changed to 0·25 (IqU, flowing through The MN7 current is changed to 1.25 (Iq-Iw/), wherein the clocks CLK1 and CLK2 are clock signals that do not overlap each other and are mutually inverted, and the input source is fed by the clock generator output. The transistor MN10 and the transistor MN11 and transistor MNL2 are used as switches, D1, D2, and D3 are control signals, which are fed by the output of the averager. The three transistor switches control the output current as a parameter multiple of the input current. In the example, the output current I(10)m can be 1.25 or 1.50 or 1.75 or 2 times the loss. The input current Ι~7ϊ. When the transistor MN10 and the transistor MN11 and the transistor MN12 are all turned on and the output current Um· is twice the input current. When the transistor MN10 and the transistor MN11 and the transistor MN12 are turned off, and The output current 1(10)(7) is 输入·75 times the input current 1/heart. When the transistor MN10 and the transistor MN11 and the transistor_12 turn off any two of them, the output current Um· is 1.50 times the input current h center. When the transistor_10 and the transistor MN11 and the transistor MN12 are all turned off' and the current Um outputted by 108268-950209.doc 4 41272531 is 1.25 times the input current Ι/ζιτ?. 'The fifth figure shows the nonlinearity. The non-linear discriminating circuit (ND) includes a plurality of current sources and a plurality of transistors, and the purpose of the circuit is to determine the positive and negative of the input Ud/current, output the true random number signal of the digit, and further input the current. 1/«/^ is used to add or subtract the parameter multiple current action, wherein the addition or subtraction is judged according to the positive and negative of the input current 1_. When the input current Ι / Λ /) ί · is positive, the transistor ΜΡ 21 is turned on, Transistor ΜΝ22 off The transistor ΜΝ23 is turned on, the transistor ΜΡ24 is turned off, the node 501 is at a low potential, the transistor ΜΡ26 is turned on, and the output is DOUT; ♦ is high, and the transistor ΜΝ27 is turned on, and the output current is current. When the input current Ι/ΤίΖ)/· is negative, the transistor ΜΡ21 is turned off, the transistor MN22 is turned on, the transistor MP24 is turned on, the transistor MN23 is turned off, the node 501 is turned on, the transistor MN25 is turned on, and the output DOUT is low. Then, the transistor MP28 is turned on, and the output current U seems to be the current I/w+(L-l6). The transistors MP40, MN35 and R form a current source 502 for the purpose of supplying a reference current I?. The transistors MP41, MP42, MP43, MP44 constitute a set of current mirrors, wherein the transistors ΜΡ41, ΜΡ42, ΜΡ43 are of the same size, and the size of the transistor ΜΡ44 is 8 times that of ΜΡ41. The current flowing through ΜΡ41, ΜΡ42, ΜΡ43 is 0.125 times Iα, and the current flowing through ΜΡ44 is Iα. Among them, the electro-crystals _36, ΜΝ37, _38, _39 constitute a set of current mirrors. In the preferred embodiment, the transistors ΜΝ36, ΜΝ37, ΜΝ38 are identical transistors, and the size of the transistor _39 is eight times that of ΜΝ36. The current flowing through _36, _37, ΜΝ38 is 0.125 times Ια, and the current flowing through _39 is Ifl. The crystal hall 29, read 30, dirty 31, draw 32, Li 33, draw 34 constitute three sets of switches, wherein continued 29 and _32 are controlled by signal / D1, MN30 and _33 are controlled by signal / D2, MN31 and _34 Controlled by signal / D3. The signal /^,/02,/03 is the output of the averager. When any of /0^/02, /03 is high and the rest is low, it is 〇·125Ια. When /Dl, /D2, /D3, the second signal is high and the rest is low ‘potential’, then 16 is 〇.25込. When the /Dl, /D2, /D3 signals are all high, then l is 0.3751. The sixth figure shows the architecture of the averager, which includes a digital logic 601; a synchronous switch 602; three sets of latching states 603. The three-digit real digital random input D〇UTi, d〇UT2, d〇UT3 are respectively The output of 121, 122, 123 in the first figure, due to the fact that the 3-bit real number random number d〇UTi, d〇Ut2, and d〇UT3 are high-potential bit numbers, the probability of occurrence is not equal probability. Occurs ^ Therefore, the architecture of the average is such that the output signals D1, D2, and D3 are events of a high number of bit events. The ultimate goal is to make the parameter multiple of 1;111 equal probability. Similarly, the output signal /Dl, /D2, /D3 is the number of high-potential bits 108268-950209.doc 1272531 will also have the rate of occurrence, the final purpose of the mixed parameters of the electric double material . With ^ p_0^, the output of the average li is synchronized with the three sets of LTH lu, 112, 113, and three sets of latches 6〇3 are used to output the magnetic 01, 〇2, 〇3, /〇1, /〇2, /〇3 . The probability of an event, etc. occurs. The ultimate goal is to make the parameter multiple current equal. In the same way, the event that the output signal muscles must be the number of bits in the (four) position will also have an equal probability. The ultimate goal is to make the parameter current of the parameter of yeah equal. The synchronizing switch 602 synchronizes the output of the averager with the three sets of m, 112, 113, and outputs signals D1, D2, D3, /01, 02, /03 using three sets of locks. In order to demonstrate the superiority of this invention, the preferred embodiment is based on (4) beer reading system provided by Taiwan Integrated Circuit Company. Cheng came to work. The seventh figure shows the 3-bit real digital random output (tt_L2.5v, 25 C) with an input clock of 10MHz. The first table lists the output of the random number through the verification results of Peng Gang ^, and further lists the verification results of the corner (comer). Industrial Applicability^Inventions can be applied to ························································································ However, the scope of the patent application proposed by the present invention is not exceeded. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a preferred embodiment of the present invention; FIG. 2 is a 1-bit real random number generator; FIG. 3 is a characteristic curve of a 1-bit real random number generator; : Linear sampling and holding circuit diagram; - Figure 5: Nonlinear decision circuit diagram; Figure 6: Averager circuit diagram; and Figure 7: The preferred embodiment of the 3-bit real digital random number rotation. [Major component symbol description] 100 averager 101 linear sample and hold circuit 108268-950209.doc • 10-1272531 102 > 103 > 104 1-bit real random number generator 105 clock generator 121, 122, 123 Linear Decision Circuit 200 Averager 201 Linear Sample and Hold Circuit 202 Nonlinear Decision Circuit 203 Line 401 Current Source 402 Current Source 403 Current Source 404 Current Source 405 Current Source 406 Current Source 501 Node 502 Current Source 601 Digital Logic 602 Synchronous Switch Current Source 603 latch lock 108268-950209.doc -11 -