1271134 九、發明說明： 【發明所屬之技術領域】 本發明係有關於電路佈局〇ayout)，尤指—種訊號線之佈 局結構及相關方法。 【先前技術】 在進行晶片或是印刷電路板(pCB)之電路佈局時，對於匯 流排(bus)的部分，必須盡可能讓匯流排的每個訊號線之負載 (loading)相同，以使傳輸的訊號有較好的相位一致性⑽挪 uniformity)。訊號線的負載主要包含電阻與寄生電容_批脱 capacitance)。習用的佈局做法為了使匯流排的負載相同，在 走線時常會使用阻尼線(damping line)，藉由增加線路長度或 利用特定形狀，以改變線路負載，從而達到負戴相同的目的。 只是，由於阻尼線的實際電阻與電容會因其長度、形狀以及 與週邊線路或元件的相對位置等因素，而難以精確估計，因 此完成佈局後，還須花費大量的時間與人力反覆進行調整及 驗證(亦稱為後模擬(post simulation))，以確認钸局所得之匯流 寺非負載相同。這對於講求產品開發速度的科技產業，是一項 不利因素。 另外，由於現今電子產品的功能與設計日趨複雜，因此 須在有限面積的晶片内或電路板上設置複雜密集的電路。然 而，在習用的佈局技術中，有時會為了增加阻尼線長度或改 變其形狀，而用到較大的繞線面積，這對於電路的設計與佈 1271134 局’亦是一項不利因素。 【發明内容】 本發明的目的之一，係提供一種訊號線佈局結構及相關 方法’可利用簡易、不需反覆模擬驗證的設計方式，快速達 成匯流排負載相同的目的，節省佈局時間。 本發明的另一目的，係提供一種訊號線佈局結構及相關 方法，可避免使用形狀複雜的線路，以縮小匯流排的寬度， 鄞省繞線面積。 本發明的又一目的，係提供一種訊號線佈局結構及相關 方法，對於光罩具有其免疫性。 為達前述目的，本發明之訊號線佈局結構至少包含：一 第一金屬線層，包括一組互相平行之第一金屬線，該組第一 金屬線包括複數個實質上等長之第一訊號線；以及一第二金 屬線層，包括至少一組互相平行之第二金屬線，各組第二金 屬線包括複數個實質上等長之第二訊號線。其中，各組第二 金屬線之該些第二訊號線與該些第一訊號線一對一相耦接， 並且，在同一組第二金屬線中，每一第二金屬線之跨越該組 第一金屬線的部分實質上皆為等長。 為使貴審查委員對於本發明能有更進一步的了解與認 同，茲配合圖式詳述本發明的實施方式如后。 【實施方式】 請同時參照圖，至圖三。圖一係繪示本發明之訊號線佈 1271134 局結構之一較佳實施例上視圖，圖二係繪示沿圖一之剖面線 1_1所得之剖面圖’而圖三係繪示沿圖一之剖面線hi所得之 到面圖。在此較佳實施例中，訊號線佈局結構100係為一個 四層結構，從上到下分別為： 參1271134 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a circuit layout 〇ayout), and more particularly to a layout structure and related methods of a signal line. [Prior Art] When performing circuit layout of a chip or a printed circuit board (pCB), for the bus portion, it is necessary to make the load of each signal line of the bus bar the same as possible for transmission. The signal has a good phase consistency (10) and uniformity). The load of the signal line mainly includes the resistance and parasitic capacitance _ batch capacitance. Conventional layout practices In order to make the load of the busbars the same, a damping line is often used when routing, and the same purpose is achieved by increasing the length of the line or using a specific shape to change the line load. However, since the actual resistance and capacitance of the damper line are difficult to accurately estimate due to factors such as its length, shape, and relative position to surrounding lines or components, it takes a lot of time and manpower to adjust it after the layout is completed. Verification (also known as post simulation) to confirm that the sinks obtained by the bureau are not loaded the same. This is a disadvantage for the technology industry, which emphasizes the speed of product development. In addition, due to the increasing complexity of the functions and designs of today's electronic products, complex and dense circuits must be placed in a limited area of the wafer or on the board. However, in conventional layout techniques, sometimes a larger winding area is used in order to increase the length of the damper line or change its shape, which is also an unfavorable factor for the design and layout of the circuit. SUMMARY OF THE INVENTION One object of the present invention is to provide a signal line layout structure and related method that can be easily utilized, and does not require repeated analog verification, to quickly achieve the same purpose of the bus load, thereby saving layout time. Another object of the present invention is to provide a signal line layout structure and related method, which can avoid the use of complicated shape lines to reduce the width of the bus bar and save the winding area. It is still another object of the present invention to provide a signal line layout structure and associated method that is immune to the reticle. To achieve the foregoing objective, the signal line layout structure of the present invention includes at least: a first metal line layer including a set of first metal lines that are parallel to each other, the set of first metal lines including a plurality of first signals of substantially equal length And a second metal line layer comprising at least one set of second metal lines that are parallel to each other, each set of second metal lines comprising a plurality of second signal lines of substantially equal length. The second signal lines of the second metal lines of each group are coupled to the first signal lines one-to-one, and, in the same group of second metal lines, each second metal line spans the group. The portions of the first metal line are substantially equal in length. For a more detailed understanding and recognition of the present invention, the embodiments of the present invention will be described in detail with reference to the drawings. [Embodiment] Please refer to the figure at the same time, to Figure 3. 1 is a top view of a preferred embodiment of the signal line 1271134 of the present invention, FIG. 2 is a cross-sectional view taken along line 1_1 of FIG. 1 and FIG. 3 is a view along FIG. The section line hi is obtained from the surface map. In the preferred embodiment, the signal line layout structure 100 is a four-layer structure, from top to bottom:
(1)苐一金屬線層：此層包括一組互相平行之第一金屬 、镦，該組第一金屬線包括複數個等長之第一訊號線101及第 一隔離線102’且配置為每一第一訊號線1〇1兩旁各有一第一 隔離線102，以隔離雜訊與干擾(interference)。在圖一之實施 例中第訊號線101係為一對差動(differential)訊號線，而 兩旁所配置的第-隔離線1G2為接地線。此對差動訊號線與 兩旁之第-隔離線102的間距(即圖一中的al)為等長，以使此 部份線路的寄生電容相同。 (种間隔離層：此層介於第—金屬線層與第二金屬線層 (見後文)間，可隔離雜訊與干擾。 (3)第二金屬線層··此層包括至少—組 第二金屬線包括複數個等長之第二訊號線= Ϊ 1=(_^第二域線_長），且配置為 斑干=一:fr〇3兩旁各有一第二隔離線104，以隔離雜訊 通孔H)5 一金屬線之第二訊號線103係經由複數個導 ^孔_㈣—金麟之第_ 等Τ 每-一 -平複數個中間隔離線⑽，係-對 弟—金屬線之第二訊號線103而設置，且不觸 1271134 及該些導通孔105，以避免短路。 一 之實施例中，係顯示了兩組第二金屬線，各組第 一至屬線係與該組第一金屬線相垂直。 皆為一卦#叙π綠綠各、、且之4二訊號線103 二對差動喊線’而兩旁所配置的第二隔離線⑽則為 ^地線。各組之差動訊號線細旁之第二隔離線⑽的間距 (㈣-令的a2與a3)為等長’惟a2不需等於^。此外，第 一金屬線層之差動訊號線本身之間距(即圖一之叫與第二金 屬線層之兩對差動訊號線本身之間距(即圖一之以與⑼三者 ^而相等。並且，各組第二金屬線跨越該組第—金屬線的 口^刀係各自等長(即圖-之^與⑺。此外，圖—之粗實線部 分即為前述之中間隔離線106，其在導通孔1〇5附近鑛，以 避免觸及導通孔1〇5。 (句底部隔離層1〇7 :此層位於底部，亦為執行隔離雜訊 與干擾的功能。 參照圖二與@三關面圖，當更驗解前述四層結構的 相對位置義。在@_的峨線佈局結構1GG巾由於匯流 排之各個訊號線的傳輸條件皆一致，因此負载也會相同。以 圖一之訊號傳輸職！與2來看，首先，路徑丨與2之長度 相同’因而電阻亦會相同；其次，兩路徑與周邊線路的相ς ，係’在上下方向或左右方向皆為對稱或相同，因而寄生電 容亦會相同。詳言之，在整個傳輸路徑上，路徑i與2和兩 旁隔離線之相對位置係左右對稱，和中間隔離線1〇6的間距 相同’和底部隔離層107的間距亦相同。特别是，訊號線佈 局結構100具有每-第二金屬線跨越該組第一金屬線之部分 1271134 ' 皆為等長的設計，亦即，在訊號實際所走的路徑外，多出圖 一之dl至d4的部分’這對於促成各傳輪路徑之寄生^容二 同，有很大的助益。 在圖一之實施例中，由於繞線的形狀單純，可使匯流排 的寬度違到最小，以節省繞線面積。在圖一中，匯流排共有 四條金屬線’其寬度最小可達三個最小線距〇^也）。此最小線 距係依訊號線佈局結構100所使用之製程而定。再者，以此 種方式佈局，更容易確保匯流排的負載相同，而不需再耗費 • 大1時間及人力進行後模擬。此外，由於整個佈局結構之隔 離設計相當完整，因此，後續在實作電路時，即使有光罩未 對準(maskmisalignment)的問題，也不會因為改變匯流排與週 邊元件或線路的原本相對位置關係，而影響到匯流排負^的 一致。簡言之，本發明之訊號線佈局結構對於光罩未對準的 問題具有免疫性。 值得注意的是，圖一之第二金屬線不一定要與第一金屬 線保持垂直，亦可呈現其他的相交角度，只要每—第二金屬 • 線之跨越該組第一金屬線的部分能維持實質上等長即可。此 處，每一第二金屬線具有跨越該組第一金屬線的部分，係代 表第一金屬線與該組第一金屬線呈現上下重疊的狀態。再 者，不同組之第二金屬線亦可與第—金屬線有不同的相交角 度，例如，圖一之兩組第二金屬線與第一金屬線之相交角度 可分別為45度與9G度。另外，圖—之第_訊號線丨⑴與第 為—般的單—訊麟，而不需使用差動訊 號線。_，第一 /第二金屬線即配置為每一單一訊號線之兩 1271134 旁各有一第一/第二隔離線。 圖一之實施例可擴充到使用多對差動訊號線的情形，以 擴展其應用範圍。圖四係為使用三對差動訊號線之一實施例 的上視圖。當然，在實際應用上，欲使用多少對差動訊號線 並無限制，此處僅為列舉其中一例。在圖四之實施例中，所 擴充的第一金屬線與第二金屬線仍各自維持在圖一實施例中 之相對關係。換言之，在第一金屬線層中，各對差動訊號線 與兩旁之第一隔離線1〇2(圖中標示為G)的間距(即圖四之al) 皆相同，各對差動訊號線本身之間距(即圖四之bl)亦皆相同； 在第二金屬線層中，兩組第二金屬線之各對差動訊號線與兩 旁之苐二隔離線104的間距(即圖四之a2與a3)各自皆相同， 而兩組第二金屬線之各對差動訊號線本身之間距(即圖四之 與b3)各自亦皆相同。 在圖一的較佳實施例中，第一金屬線層係位在第二金屬 線層上方。在另-實施例中，第—金屬線層則位在第二金屬 線層下方，亦可獲致類似的功效。 以現今的技術水平，晶片或電路板具有超過四層之多層 設計’是非常普遍的情形。圖-之四層佈局結構亦可適用於 此種晶片或電路板。原則上，可選用多層中的㈣四層，依 據前述圖-之上下順序安排各層，柯㈣本伽之訊號線 佈局結構。獨’為盡量降低線路的寄生電容，可將底部隔 離層與其他三層的間距放至最大^如，若晶4或電路_ 共有六層’則可選取最下-層(即第六層)作為 他三層置於最上三層（即第一、二、二芦彳。^ + 一增）。此外，若晶片或電 1271134 路板共有八層，則可利用上四層與下四層分別實作-個本發 歡訊號線佈局結構，其中一至四層(與五至八屬)分別為前述 之第-金屬層、中間隔離層、第二金屬層及底部隔離層。 以上所述，係利用較佳實施例詳細說明本發明，而非限 射本發明之關。大凡熟知此類技藝人士皆能贿，適當而 作些微的改變及調整，仍將不失本發明之要義所在，亦不脫 離本發明之精神和範圍。 【圖式簡單說明】 圖-係緣示本發明之匯流排佈局結構之一較佳實施例上視 圖。 圖二係繚示沿圖一之剖面線w所得之剖面圖。 圖三係繪示沿圖一之剖面線1141所得之剖面圖。 圖四係為使用三對差動訊號線之一實施例的上視圖。 101_第一訊號線 膨第二訊號線 105_導通孔 底部隔離層 【主要元件符號說明】 100-訊號線佈局結構 102·第一隔離線 104-第二隔離線 106·中間隔離線 11(1) a metal wire layer: the layer includes a set of first metal and tantalum which are parallel to each other, and the first metal wire includes a plurality of first signal lines 101 and a first isolation line 102' of equal length and configured as Each of the first signal lines 1 〇 1 has a first isolation line 102 on both sides to isolate noise and interference. In the embodiment of Fig. 1, the first signal line 101 is a pair of differential signal lines, and the first isolation line 1G2 disposed on both sides is a ground line. The distance between the pair of differential signal lines and the first-isolation line 102 on both sides (i.e., al in Figure 1) is equal, so that the parasitic capacitance of the portion of the line is the same. (Inter-type isolation layer: This layer is between the first metal line layer and the second metal line layer (see below) to isolate noise and interference. (3) Second metal line layer · This layer includes at least - The second metal wire of the group includes a plurality of second signal lines of equal length = Ϊ 1 = (_ ^ second domain line _ long), and is configured as a spot dry = one: fr 〇 3 has a second isolation line 104 on each side, The second signal line 103 for isolating the noise via hole H) 5 and the metal line is via a plurality of conductive holes _ (4) - Jin Lin's _ Τ Τ - 一 平 平 中间 中间 中间 中间 中间 中间 中间 中间 中间 中间 对 对The second line 103 of the metal line is disposed, and the 1271134 and the via holes 105 are not touched to avoid a short circuit. In one embodiment, two sets of second metal lines are shown, each set of first to genus lines being perpendicular to the set of first metal lines. Each is a 卦 叙 π green green, and 4 2 signal line 103 two pairs of differential shouting line 'and the second isolation line (10) arranged on both sides is ^ ground line. The spacing of the second isolation line (10) next to the differential signal line of each group ((4) - a2 and a3 of the order) is equal in length 'only a2 does not need to be equal to ^. In addition, the distance between the differential signal lines of the first metal line layer (ie, the distance between the two pairs of differential signal lines of FIG. 1 and the second metal line layer (ie, FIG. 1 is equal to (9) Moreover, each group of second metal wires spans the same length of the first metal wire of the group (ie, FIG. 2 and (7). In addition, the thick solid line portion of the figure is the aforementioned interval 106. It is in the vicinity of the via hole 1〇5 to avoid touching the via hole 1〇5. (The bottom layer isolation layer 1〇7: This layer is located at the bottom, which is also a function of isolating noise and interference. Refer to Figure 2 and @ The three-level map, when the relative positional meaning of the above four-layer structure is more verified, the transmission condition of each signal line of the busbar is the same in the convergence pattern of the @_ 峨 line layout structure, so the load will be the same. The signal transmission job! With 2, first, the path 丨 is the same as the length of 2' and thus the resistance will be the same; secondly, the two paths are opposite to the surrounding lines, which are symmetrical or the same in the up and down direction or the left and right directions. Therefore, the parasitic capacitance will be the same. In detail, the entire transmission path The relative positions of the paths i and 2 and the two isolation lines are bilaterally symmetric, and the spacing between the intermediate isolation lines 1 and 6 is the same as that of the bottom isolation layer 107. In particular, the signal line layout structure 100 has a per-first The two metal wires spanning the portion of the first metal wire of the group, 1271134', are of equal length design, that is, the portion of the dl to d4 of Figure 1 is outside the path actually taken by the signal. The parasitic capacitance of the path is very helpful. In the embodiment of Fig. 1, since the shape of the winding is simple, the width of the bus bar can be minimized to save the winding area. The bus bar has a total of four metal wires 'the width of which is at least three minimum line spacings 〇^ also.) The minimum line spacing is determined by the process used by the signal line layout structure 100. Furthermore, in this way, the layout is further It is easy to ensure that the load of the busbars is the same, no need to spend more. • Large time and manpower for post-simulation. In addition, since the isolation design of the entire layout structure is quite complete, even after the implementation of the circuit, even if there is a mask Quasi (m The problem of askmisalignment) does not affect the consistency of the busbars due to changing the original relative positional relationship between the busbars and the peripheral components or lines. In short, the signal line layout structure of the present invention is misaligned with the mask. The problem is immune. It is worth noting that the second metal wire of Figure 1 does not have to be perpendicular to the first metal wire, and may also exhibit other intersecting angles, as long as each - second metal wire crosses the group. The portion of a metal wire can be maintained substantially equal in length. Here, each of the second metal wires has a portion spanning the first metal wire of the group, and the first metal wire is overlapped with the first metal wire of the group. In addition, the second metal wires of different groups may have different intersection angles with the first metal wires. For example, the intersection angle between the two groups of second metal wires and the first metal wires in FIG. 1 may be 45 degrees respectively. With 9G degrees. In addition, the figure_the signal line 丨(1) and the first-order single-Xinlin do not need to use the differential signal line. _, the first/second metal line is configured to have a first/second isolation line adjacent to each of the two signal lines 1271134. The embodiment of Figure 1 can be extended to the use of multiple pairs of differential signal lines to extend its range of applications. Figure 4 is a top view of an embodiment using one of three pairs of differential signal lines. Of course, in practical applications, there is no limit to how many differential signal lines to use. Here is just one example. In the embodiment of Figure 4, the expanded first metal line and the second metal line are each maintained in an opposing relationship in the embodiment of Figure 1. In other words, in the first metal line layer, the distance between each pair of differential signal lines and the first isolation lines 1〇2 (indicated as G in the figure) on both sides are the same, and each pair of differential signals The distance between the lines themselves (ie, bl in FIG. 4) is also the same; in the second metal line layer, the distance between each pair of the second metal lines and the two isolated lines 104 (ie, FIG. 4) Each of a2 and a3) is the same, and the distance between each pair of differential signal lines of the two sets of second metal lines (ie, FIG. 4 and b3) are also the same. In the preferred embodiment of Figure 1, the first metal line layer is positioned above the second metal line layer. In another embodiment, the first metal line layer is located below the second metal line layer, and similar effects can be obtained. At today's state of the art, it is very common for a wafer or board to have a multi-layer design of more than four layers. The four-layer layout of Figure- can also be applied to such a wafer or board. In principle, it is possible to use four (four) layers in multiple layers, and arrange the layers according to the above-mentioned top-down order, and the signal line layout structure of Ke (four). In order to minimize the parasitic capacitance of the line, the distance between the bottom isolation layer and the other three layers can be maximized. If the crystal 4 or the circuit _ has six layers, the lowermost layer (ie, the sixth layer) can be selected. As his three layers are placed in the top three layers (ie, the first, second, and second reeds. ^ + one increase). In addition, if the wafer or the electric 1271134 board has eight layers, the upper four layers and the lower four layers can be used to implement a separate signal line layout structure, wherein one to four layers (and five to eight genera) are respectively a first metal layer, an intermediate isolation layer, a second metal layer, and a bottom isolation layer. In the above, the invention has been described in detail by way of preferred embodiments, without limiting the invention. Anyone who is familiar with such art can make a bribe, and appropriate changes and adjustments will remain without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig.-Bottom view shows a preferred embodiment of a bus bar layout structure of the present invention. Figure 2 is a cross-sectional view taken along line w of Figure 1. Figure 3 is a cross-sectional view taken along section line 1141 of Figure 1. Figure 4 is a top view of an embodiment using one of three pairs of differential signal lines. 101_First signal line Expanded second signal line 105_Connecting hole Bottom isolation layer [Main component symbol description] 100-signal line layout structure 102·First isolation line 104-Second isolation line 106·Intermediate isolation line 11