TWI269449B - Photo-electronic display device and the making method thereof - Google Patents

Abstract

The invention provides a photoelectric display device, which utilizes simplification of the manufacturing steps of the thin film transistor structure portion and does not limit the materials for source and drain electrode at the same time to controls accurately the film thickness of semiconductor layer for thin film transistor channel portion to prevent the un-uniform display. The drain electrode 26 is installed so as to extending from the active area layer AR onto the top of transparent insulation substrate 1 of the down position of pixel electrode 30. The source electrode 24 and the wiring of source 25 are installed to make the end surface locate at step back position comparing with any end surface of semiconductor film 6. The drain electrode 26 on the active area layer AR is also installed to make the end surface locate at step back position compared with parallel end surface of the semiconductor film 6.

Description

J269449 IX. Description of the Invention: [Technical Field] The present invention relates to an electro-optical display device and a method of fabricating the same, and in particular to an active matrix type electro-optical including a thin film transistor (TFT) as a switching element Display device and method of manufacturing the same. [Prior Art] On an electro-optical display device using liquid crystal and organic electroluminescence as an electro-optical element, switching elements such as thin film transistors are arrayed on a substrate and applied to each display pixel. Active matrix type array substrate 0 of independent image signals In order to increase the productivity of such an electro-optical display device, it is necessary to reduce the number of manufacturing steps of the TFT array substrate. For example, in the patent document, the light reduction is disclosed using FIG. 54 to FIG. A technique of etching the number of steps of lithography, and discloses a method of manufacturing a TFT array substrate by using a photolithographic lithography step of 5 times. For example, in the manufacturing process of the source/drain electrode and the channel portion of the TFT shown in FIGS. 58 and 59 of Patent Document 1, a metal film such as Ti (titanium) as a source/drain electrode is formed. Thereafter, a photoetching lithography step is used to pattern the photoresist, and an etchant composed of HF+IM) is used for etching, etching the Ti film and the ohmic contact of the semiconductor layer (11+ amorphous germanium (a second film, To form a source/drain electrode and a channel portion process. However, in this case, first, after removing the Ti film having a thickness of about 3 〇〇 nm as the first etching step, the ohmic contact film having a thickness of about 20 nm is removed.

^ Ύψ 2108-7516-PF 5 1269449 is the continuation of the second etching step. Usually, in the first etching step, in order to prevent the residual residue after the Ti film is roughly removed, the process proceeds excessively (4). The excessive (four) time is determined by considering the thickness variation of the etching residue, based on the in-plane distribution of the etched substrate, and the time at which the region where the etching rate is the slowest is etched as a starting point. In this case, since the second etching step starts from the point at which the Ti film is completely removed, the etching time changes depending on the etching rate distribution of the T1 film. The temporal change of this second etching step is responsible for the change in the film thickness of the ^Si film which is the m channel portion. Since this change is a change in the characteristics of the tft switch, there is a possibility that a defect of display unevenness is generated. In the above process, the Ti film and the ohmic contact film (n + a-Si film) are not subjected to wet etching, and may be removed by dry etching using a gas. However, in dry etching using a dry etching gas Ch (chlorine) gas of a Τ1 film, since the etching rate of the n+ a-Si film is approximately equal to that of the Ti film, it is difficult to control the above-mentioned a-Si film as a TFT channel portion. The film thickness is a problem that changes. As a method for solving such a problem, a method of forming a source/drain electrode by using an a-Si film and a metal film having an etching selectivity is considered. For example, after the Cr (chromium) film or the Mo (molybdenum) film is used, the photoresist is patterned using a photolithography lithography step, and as a first etching step, for example, in the case of a Cr film, a nitric acid recording + a supplemental acid system is used. In the case of the M ruthenium film, the etchant is composed of a dish of acid + nitric acid + acetic acid, and the Cr film or the M film is solidified to form a source/drain electrode. The ohmic contact film (n+ a-Si film) was not etched in this wet etching step. 2108-7516-PF 6 41269449 is s=. The second wide step 'etches the 接触 接触 contact film (n+ a_Si :) by dry etching using Cl 2 gas or CF 4 (or 2 - - : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : - The control of the film thickness variation of the Si film can be controlled only in the process of the second etching step. However, in these methods Φ, the ancient 芏田 I, 広^ is used as the source/drain electrode metal film. The types and processing processes are strictly limited. For example, 'when the micro-machining of the source and the electrodeless electrode is to be performed accurately, the accuracy is better than the wet (four) method, although for example, in the case of the Cr film. A well-known Cl2 gas is used in the middle, and in the case of the M tantalum film, a dry (four) gas (GF4 or muscle) is used, which is a general process, in which case the etching rate of the n+ a_Si film is combined. The film or the Mo film is approximately equal, and causes the same problem as in the case of the above-described η film. Further, in the case of forming a source with an a-Si film and a metal film having an etch selectivity, and a case of a pole electrode, for example, Requirements for heat resistance or resistance to money, etc. 'Because the metal film is limited (4) Cr film, film or A1 ( The film has a narrow range of selection in the case where the metal film is to be optimized, and has an inability to obtain sufficient characteristics as an electro-optical display device. In addition, in Patent Document 2, it is disclosed in the formation of a source. In the photoresist pattern in the case of the semiconductor layer without the electrode layer, when a dry etching method in which oxygen is mixed into a dry etching gas is used, the semiconductor film (a-Si film) which becomes the source/drain layer is etched, and the semiconductor is previously made. When the thickness of the photoresist film on the channel forming portion of the layer is reduced, the photoresist having the thin portion of the film thickness is etched according to the effect of the ashing effect, and a time difference is provided to etch the n + a-Si film which becomes the channel portion. 2108-7516-PF 7 »4 1269449 : In this method, 'although the money is engraved hundreds of hundreds of hundreds of wide areas: the honest conductor film' due to the simultaneous narrowing of several μπι~10 (10):: The ashing of the resist and the engraving of the nUi film in the lower layer make it difficult to control the film thickness of the a-Si film in the channel portion, and the problem of change occurs. Furthermore, since the source/drain electrode is formed thereafter, Using etch selectivity with a-Si film In the case of a membrane material, there is a problem that the selection of the material of the source and the drain electrode is very small. [Patent Document 丨] JP-A-8-50308 [Patent Document 2] JP-A No. 0-1 631 74 [Problem to be Solved by the Invention] As described above, according to the technique disclosed in Patent Document 1, the film thickness of the a-Si film serving as the TFT channel portion changes, and the change in switching characteristics of m becomes Defects in display unequalness may occur. In the case of a method of forming a source/drain electrode using a X a S i film and a metal film having an etch selectivity, there is a metal film type and processing used as a source/drain electrode. The process is strictly limited. Further, according to the technique disclosed in Patent Document 2, in the photoresist pattern in the case of forming the semiconductor pattern of the source/dipole layer, when dry etching is performed using oxygen gas mixed into a dry gas, etching becomes a source. When the semiconductor film (aH) of the electrode layer is made to light the thickness of the channel forming portion of the semiconductor pattern in advance, the photoresist of the thinner blade is etched according to the effect of the ashing effect, and the etching is performed by several hundred mmx. Semi-guided broad area

2108-7516-PF 41269449 The body film, while performing ashing of the photoresist in a very narrow region of several μπ!~10 μm, and etching the underlying n+ a-Si film, it is difficult to control the a- as the channel portion The film thickness of the Si film is a problem that changes in film thickness. In order to solve the above problems, an object of the present invention is to provide an electro-optical display device in which an active matrix type electro-optical display device is simplified with a gate electrode, a gate insulating film, a channel portion, a source/drain layer, and a source. In the manufacturing process of the TFT structure portion of the gate electrode, the material of the source φ pole and the drain electrode is not limited, and the film thickness of the semiconductor layer serving as the TFT channel portion is accurately controlled, and the change is suppressed to prevent variations in TFT characteristics. [Electronic optical display device according to claim 1 of the present invention, which is an electro-optical display device comprising an active matrix substrate, which is an apparatus for solving the problem] The insulating substrate is provided with a plurality of display pixels arranged in an array on the insulating substrate, and electrically connected to the pixel electric φ pole of the thin film transistor; the gate wiring is sequentially scanned to select the thin film electric a crystal; and a source wiring, the electrical signal is given to the pixel electrode; and the gate wiring and the source wiring are orthogonal to each other to form a moment Like. The thin film electromorphic system has an active region layer, and a semiconductor film bifurcation disposed under the source wiring, and a source electrode and a drain electrode, leaving a gap and selectivity on the active region layer The ground is assigned. In the active region layer, at least the source electrode is disposed such that an end surface position thereof is located at a position that is more than a predetermined distance from a position of either end surface of the active region layer, and the gate electrode is disposed from the foregoing The active region layer extends above the insulating substrate of the 2108-7516-PF 9 1269449 pixel display region, and the active region layer is absent from the lower layer of the gate electrode in the pixel display region. A method of manufacturing an electro-optical display device according to claim 3, wherein the method of manufacturing an electro-optical display device includes: an insulating substrate; a plurality of display pixels arranged in an array manner The insulating substrate has a pixel electrode electrically connected to the thin film transistor; the gate wiring sequentially scans and selects the thin film transistor; φ and the source wiring, and supplies an electrical signal to the pixel electrode; and the gate A method of manufacturing an electro-optical display device in which a main active matrix substrate having a matrix shape is formed orthogonally to the surface of the source wiring, comprising: (a) 4 forming a first conductive film on the insulating substrate Thereafter, a photolithographic lithography of the third pass is performed to pattern the gate wiring, and (b) an insulating film, a semiconductor film, and an ohmic contact film are sequentially formed over the gate wiring, and then the second step is performed. The secondary light is lithographically patterned, and the semiconductor film and the ohmic contact film are patterned to form an underlying film of the source wiring, and φ is simultaneously formed a step of separating the active region layer from the semiconductor film; and (c) after the step (b), after forming the second conductive film across the entire insulating substrate, the second conductivity Step of the film patterning step (C) has: (c-1) performing a third photoetching lithography on the second conductive film from the underlying film and the active region a step of forming a first photoresist pattern that is thinner than the channel portion corresponding to the channel portion of the thin film transistor in the upper portion of the insulating substrate to the pixel display region; (c- 2) removing the second conductive thin film on the first photoresist pattern without etching; (c_3)

2108-7516-PF 1269449 After the step (c-2), the front (four)th photoresist pattern is ashed and thinned, and the channel corresponding portion is removed, and a second photoresist pattern as an opening portion is formed. And (c_4) using the opening through the second photoresist pattern, the first and second ohmic contact films corresponding to the front track portion are sequentially transmitted through the fourth resist pattern, and the ohmic contact film is removed in order. In the second conductive film of the second photoresist pattern and the ohmic contact film, a step of patterning the source wiring while leaving a gap between the active region layer and the source electrode and the electrodeless electrode . According to the electro-optical display device of the first aspect of the invention, in the active region layer, at least the source electrode is disposed such that the end surface position is located in the active region When the source electrode and the drain electrode are patterned at the position of any one of the end faces of the layer, when the source electrode and the drain electrode are patterned, the conductive material is reattached to the end face of the active region layer as a conductive material. The substance prevents the source electrode and the drain electrode from being electrically conducted. Further, since the active layer is not provided on the lower layer of the gate electrode in the pixel display region, when the present invention is applied to a transmissive liquid crystal display device that illuminates the pixel display region with odd light, light is irradiated To the active region layer, and since the occurrence of current due to photoexcitation can be suppressed, deterioration of the shutdown characteristics of the thin film transistor can be prevented. According to the method of manufacturing an electro-optical display device according to the third aspect of the present invention, in the step (c) of patterning the second conductive film, the first light-transmissive lithography is transmitted through the third time. In the photoresist pattern, first, the second conductive film not covering the first photoresist pattern is removed, and 2108-7516-PF 11 and 1269449 are removed, and then the first photoresist pattern is ashed to form the second pattern. The photoresist pattern '= removes the second conductive film and the ohmic contact film corresponding to the j-channel portion from the core portion of the second photoresist, and simultaneously passes through the money contact! ^ goes to the second photoresist Pattern-covered second conductive film and ohmic, 'because the source electrode and the drain electrode pattern are on the active region layer

Shape = the source (four) _ case, can be made 3 times (four) lithography step into a thin film transistor, and can simplify the manufacturing steps. Further, since the J = case is ashed to be thinned and the second resist pattern of the channel corresponding portion is removed, the size of the second resist pattern in the plane direction is smaller than that of the first resist pattern. When the second photoresist pattern is used, at least the source electrode can be disposed such that the end surface position is located at a position greater than or equal to a predetermined distance from the position of the end surface of the active region layer, and the second conductive film is used. When the ohmic contact film is dry, even if the conductive material constituting these materials is attached to the (four) surface, the conductive material is permeable to prevent the source electrode from electrically conducting the electrode and the electrode. Further, since the opening portion of the photoresist pattern is passed through the second dimension, the conductive portion and the ohmic contact film corresponding to the channel portion are sequentially removed through the residual, even in the case of the semiconductor film and the ohmic contact film.

The contact film and the metal film which is not selective for the formation of the second conductive thin film, the temple or the etching process using no etching selectivity, can be good and work! - The second conductive film and the ohmic contact film are removed, and the film thickness of the semiconductor film in the channel portion of the thin dielectric transistor is controlled to be suppressed, and the change in the characteristics of the thin film transistor can be prevented. Display 2108-7516-PF 12 U69449 [Embodiment] <Α·Example 1><Α-1. Device Configuration> As an electro-optical display device according to Embodiment 1 of the present invention, a TFT is used as a switch The planar configuration of the TFT active matrix substrate 100 of the device's transmissive liquid crystal display device is shown in Fig. 1, and the cross-sectional configuration of A-〇-A in Fig. 1 is shown in Fig. 2. Fig. 1 is a plan view showing a pixel on a TFT active matrix substrate 1 on a TFT active matrix substrate 100, which are plurally arranged in a matrix. As shown in Fig. 1, a part of the transparent insulating substrate 1 such as a glass substrate is provided with a gate wiring 4 constituting a gate electrode 2. The gate wiring 4 is disposed so as to linearly extend in one direction on the transparent insulating substrate 1, and the direction is referred to herein as the X direction, and the direction orthogonal to the χ direction in the plane is referred to as the Υ direction. The auxiliary electric electrodes 3 which are spaced apart from the gate wiring 4 and extend parallel to the gate wiring 4 are disposed, and the size of the pixel electrode 30 in the x direction is provided by the gate wiring 4 and the auxiliary capacitor electrode 3. The 浐 assisted electric grid electrode 3 is also referred to as a storage capacitor electrode, and is an electrode that constitutes a capacitor that holds a driving voltage given from the TFT after the TFT that has been connected to each pixel is turned off, and is independent of the gate electrode 2 Composition. The auxiliary capacitor electrode 3 is added along the pixel electrode 30 in order to increase the capacitance.

The lower side of the two edge portions of the direction includes the assist capacitor electrode 31 in the γ direction. 2108-7516-PF 13 ^1269449 A linear semiconductor laminated film SL is provided on the upper side of the gate wiring 4 and the auxiliary capacitor electrode 3 so as to be orthogonal to each other. The semiconductor laminated film SL is formed by laminating an ohmic contact film 7 on the semiconductor film 6, and the semiconductor laminated film SL is disposed at a plurality of intervals to extend in the γ direction, and the adjacent semiconductor laminated film SL is provided to provide the X direction of the pixel electrode 30. the size of. Further, the semiconductive volume film SL is disposed so as not to overlap above the auxiliary capacitor electrode 31. The semiconductor laminated film SL is branched at the intersection with the gate wiring 4, and spring is provided to have a portion extending along the gate wiring 4, and a portion of the semiconductor film 6 constitutes an active region layer AR of the TFT. Further, a linear source wiring 25 is provided along the semiconductor laminated film SL on the upper portion of the semiconductor laminated film SL. The source wiring 25 is formed in the same manner as the semiconductor laminated film SL at the intersection with the gate wiring 4, and has a portion extending along the gate wiring 4, and this portion constitutes the source electrode 24 of the TFT. Further, an ohmic contact film is present on the lower layer of the source electrode 24. Further, the drain electrode 26 is disposed to extend from the active region layer AR to the upper side of the transparent insulating substrate 1 below the φ pixel electrode 30. The drain electrode 26 also has a portion extending in the X direction in the lower portion of the edge portion along the χ direction of the pixel electrode 3A. The source electrode 24 and the source line 25 are disposed such that their end faces are located at positions retracted from either end surface of the semiconductor film 6, and the end faces of the gate electrodes 26 on the active region layer AR are also disposed to be located at a ratio of semiconductors The film 6 is at a position where the parallel end faces are retreated. Further, the above-mentioned approximately parallel is not necessarily limited to patterning the end face of the electrodeless electrode 26 to be parallel to the end face of the semiconductor film 6, and it is also assumed that the end face of the electrodeless electrode 26 is formed to (4) the end of the semiconductor film 6.

2108-7516-PF 14 .1269449 Face tilt. The same phenomenon also occurs in the end faces of the source electrode 24 and the source wiring 25. In the active region layer AR, the source electrode 24 and the drain electrode 26 are provided with a space therebetween, and the semiconductor film 6 between them becomes a TFT channel portion, 27. A pixel drain contact hole 29 reaching the pixel electrode 30 is provided at a position where the drain electrode 26 is parallel to the TFT channel portion 27. Next, the cross-sectional configuration of the TFT active matrix substrate 1A will be described with reference to FIG. 2. As shown in FIG. 2, the gate electrode 2 (gate wiring 4) and the auxiliary capacitor electrode are disposed on the transparent insulating substrate 1, and The first insulating film 5 is disposed so as to cover all of the transparent insulating substrate 1, and is included on the gate electrode 2 (gate wiring 4) and the auxiliary capacitor electrode 3. The portion of the second insulating film 5 whose function is above the gate electrode 2 serves as a gate insulating film. The semiconductor film 6 is disposed on the first insulating film 5, and the ohmic contact film 7 is disposed on the semiconductor film 6. Further, an ohmic contact film is not disposed on the portion of the semiconductor film 6 that becomes the TFT channel portion 27. Further, although the source wiring 25 is disposed on the upper portion of the ohmic contact film 7, the upper portion of the ohmic contact film 7 in the active region layer AR is placed in the TFT channel portion 27, and is divided into portions where the source electrode 24 is disposed. And the portion where the electrodeless electrode 26 is disposed. Further, the drain electrode 26 extends from the upper portion of the ohmic contact film 7 to the side surface of the semiconductor film 6 and the upper portion of the first insulating film 5. And the second insulating film 28 is disposed to cover the transparent insulating substrate 1

All of the above includes the source wiring 25, the source electrode 24, and the electrodeless electrode 26 2108-7516-PF 15 41269449. The pixel electrode 3 is disposed on the second insulating film 28. The pixel electrode 3 is buried in the pixel non-electrode contact hole 29 penetrating through the second insulating film 28 and reaching the drain "pole 26", and the pixel electrode 3 and the electrodeless electrode 26 are electrically connected. Fig. 3 is a plan view showing a plurality of pixels arranged in a matrix, and the gate wirings 4 of the adjacent pixels in the Y direction are spaced apart from the auxiliary capacitor electrodes 3 so as not to overlap each other. <Α-2·Manufacturing Method> Next, a method of manufacturing the TFT active matrix substrate 1A will be described with reference to Figs. 4 to 14 showing a cross-sectional view of the manufacturing steps in order. Further, the cross-sections shown in Figs. 4 to 14 correspond to the cross section of A-〇-A in Fig. 1 . 15 to 19 are plan views showing the respective steps. First, in the step shown in FIG. 4, after forming a metal thin film (not shown) on the transparent insulating green substrate 1 such as a glass substrate, the first light lithography step is performed, and at least the patterned gate is formed. The electrode 2, the capacitor electrode 3, and the gate wiring 4 are provided. Here, as the first metal thin film, it is preferable to use an alloy having a low electrical resistance value of A1 or Mo (molybdenum) or the like as a main component. The most suitable production method for using Mo as the first metal thin film is to form a Mo film having a thickness of 2 Å by a known sputtering method using argon (Ar) gas. The money plating conditions at this time were DC magnetron sputtering, the coating power density was 3 W / c in , and the Ar gas flow rate was 4 〇 s c c in. In the first photo-etching lithography step, a photoresist pattern is formed and etched by dry etching 2108-7516-PF 16 41269449 using a mixed gas of sulfur hexafluoride (SF6) gas + oxygen (〇2) gas. Mo film. The etching rate of the Mo film at this time was about 2 〇〇nm/min. Thereafter, the photoresist pattern is removed to obtain the gate electrode 2, the auxiliary capacitor electrode 3, and the gate wiring 4. Fig. 15 is a plan view showing the gate electrode 2, the auxiliary capacitor electrode 3, and the gate wiring 4 formed on the transparent insulating substrate. Next, in the step shown in FIG. 5, the second insulating film 5 is formed to cover all of the transparent insulating substrate 1, and after covering the gate electrode 2 (the gate wiring line 4) and the auxiliary capacitor electrode 3, A semiconductor film 6 is formed on the first insulating film 5, and an ohmic contact film 7 is formed thereon. Thereafter, the semiconductor erbium 6 and the ohmic contact film 7 are patterned by the second lithography step. At this time, simultaneously with the linear semiconductor laminated film SL, the active region layer AR forming the TFT is also provided together. When the semiconductor film 6 and the ohmic contact film 7 are patterned, patterning is performed on the pixel display region where the pixel electrode 30 (Fig. 2) is formed later so that the semiconductor film 6 and the ohmic contact film 7 are not extended. _ As the best manufacturing method of the semiconductor film 6 and the ohmic contact film 7, a chemical vapor deposition (CVD) method is used: a tantalum nitride film (SiNx: X is a positive number) having a thickness of about 4 Å is formed as a The insulating film 5 is formed as an amorphous germanium (a-Si) film having a thickness of about 15 Å as the semiconductor film 6, and an amorphous germanium (11+) having phosphorus (P) added to a thickness of about 5 nm as an impurity is formed. The a-Si) film is used as the ohmic contact film 7 in the second photolithography lithography step to form a photoresist pattern by using sulfur hexafluoride (SF6) gas + hydrogen chloride (HC1) gas + helium (He Dry etching of mixed gas to etch semiconductor film 6 (a-Si film) and ohmic contact

2108-7516-PF 17 41269449 Film 7 (n+ a-Si film). The etching rate at this time is about 3 〇〇 nm / min. Thereafter, the photoresist pattern SL is removed to obtain a linear semiconductor laminated film SL, and an active region layer AR is obtained. Fig. 16 shows a plan view in which the semiconductor laminated film SL and the active region layer AR are partially overlapped on the gate electrode 2, the gate wiring 4, and the auxiliary grid electrode 3. The semiconductor film 6 is basically provided to form the active region layer ar, and is used as a constituent element of the linear semiconductor laminated film SL in a region overlapping with the formation region of the source wiring formed later, and can be used as a redundant wiring for the source wiring. The electrical signal is prevented from being interrupted even when the source wiring is broken. Next, the second metal thin film 8 is formed in the step of Fig. 6 to cover all of the transparent insulating substrate 1. Here, the most suitable production method using Mo as the second metal thin film 8 is to form a Mo film having a thickness of 20 Onm by a known money plating method using argon (Ar) gas. The money key condition at this time was a DC magnetron plating method, and the coating power density was 3 W/cm 2 and the Ar gas flow rate was 40 sccm. Next, in the steps shown in Figs. 7 to 9, a photoresist 9 is formed to cover all of the second metal thin film 8, and the photoresist is patterned by the third photo-etching lithography step. First, in the step shown in Fig. 7, a positive-type photoresist 9 of a novolac resin having a thickness of about 1.6 μm is applied by a spin coater, and is carried out at i2 〇 ° C for about 90 seconds. After prebaking, the first exposure was performed using a mask R1. The photoresist R10 has a transmission region 12 2108-7516-PF 18 41269449 of the light 13 that is completely transmitted through the light, and a light-shielding region u of the light 13 that completely blocks the exposure. Through the work exposure, the photoresist 9 is first formed completely. The exposed area 15 is exposed and the unexposed area 14 that is not exposed is completed. Next, in the step shown in FIG. 8, the second exposure mask R16 is used as a transmission region through which light is transmitted only in a region corresponding to the channel portion of the TFT, and the other regions are completely opaque. The shaded area of the exposed light. And, in the second exposure, the photoresist 9 is not completely exposed, and the exposed portion of the knives is exposed to light of about 2% to 4% of the first exposure intensity, that is, a so-called half exposure. A thin film thickness remains after development, and a half-exposure region is formed on the photoresist 9. After the two-stage exposure of the photoresist 9 as described above, development is carried out with an organic alkaline developing solution, and after about (10) seconds of post-boiling at 12 (%), a photoresist pattern is formed as shown in FIG. Rpi having a first thickness portion 2〇 (channel corresponding portion) corresponding to the channel portion of the elbow, a second thickness portion 2 thicker than the first thickness portion 2, and a second thicker portion than the second thickness portion 21. 3 at least three or more different film thicknesses of the thickness portion 22. An example of the thickness of each portion is that the film thickness of the thickness portion 20 of the crucible 1 is about 0.4 μm, the film thickness of the second thickness portion 21 is about 14 mm, and the film thickness of the third thickness portion 22 is about h 6 叩 (or 1.6 μm or more). ). . The second thickness portion 21 is formed on the semiconductor laminate film and on the active region 曰AR. The third thickness portion 22 is formed on a region where the pixel electrode 30 (Fig. 2) is formed later. "People, in the step shown in Figure 1", the photoresist pattern Rpi is used as the light.

2108-7516-PF 19 1269449 The cover etches the second metal thin film 8. Here, etching is performed by a known dry etching method using a mixed gas of SFe gas + helium gas. Fig. 17 is a plan view showing the second metal thin film 8 extending from the semiconductor laminate film red and the active region stratification to the region where the pixel electrode 3G (Fig. 2) is formed later. In Fig. 17, the photoresist pattern Rp 1 is present on the upper portion of the second metal thin film 8 without omitting the recording of the photoresist pattern. Next, in the step shown in FIG. 11, the first thickness portion 2〇 of the photoresist pattern RP1 is removed by thinning the photoresist pattern Rpi by using known photoresist ashing using oxygen plasma, and remains. The second thickness portion Η and the third thickness portion 22 form a channel portion 27 corresponding to the TFT (the portion of the figure becomes the photoresist pattern RP2 of the opening portion 23. At this time, as the film is fully thinned, as shown in FIG. The condition of the photoresist ashing is set such that the size (outer shape) of the planar pattern of the photoresist pattern RP2 becomes smaller than the photoresist pattern RP1. Next, in the step shown in FIG. 12, via the photoresist pattern Rp2 In the opening portion 23, the second metal thin film 8 and the ohmic contact film 7 are sequentially removed by etching. Here, as the most suitable etching method for these films, a well-known dry gas of a mixed gas of SFe gas + 〇2 gas is used. In the etching method, the etching rate is 200 to 300 nm/min in any of the films. Thus, by removing the second metal thin film 8 or the ohmic contact film 7 at the same etching rate, the films can be almost completely etched. Second metal film 8, in semi-conductive The laminated film SL is a source wiring 25, and is formed as a source 2108-7516-PF 20 1269449 electrode 24 and a drain electrode 26 in the active region layer ar. The gate electrode 26 is patterned to be from the active region layer AR. It extends to a region where the pixel electrode 3A (FIG. 2) is formed later. Thereafter, by removing the photoresist pattern RP2, as shown in FIG. 13, the source wiring 25 is disposed on the semiconductor laminated film SL, in the active region layer. The source electrode 24 and the drain electrode 26 are disposed on the AR. A region where the semiconductor film 6 is exposed between the source electrode 24 and the drain electrode 26 becomes a channel portion of the TFT 2 〇 photoresist pattern RP2 due to Compared with the photoresist pattern Rpi, the shape of the second metal film 8 and the ohmic contact film 7 of the source electrode 24, the source line 25, and the drain electrode 26 is smaller than that of the lower layer. The outer shape of 6 is small, and is viewed from above, so that the end faces of the source wiring 25 and the source electrode 24 are located at positions retracted from either end face of the semiconductor film 6, and are disposed such that the active region layer AR The end face of the drain electrode 26 is located at an end face that is approximately parallel to the half V body film 6. Further, the above-mentioned approximately parallel is not necessarily limited to patterning the end face of the gate electrode 26 to be parallel to the end face of the semiconductor film 6, and it is assumed that the end face of the button electrode 26 may be formed to face the end face of the semiconductor film 6. The same phenomenon occurs in the end faces of the source electrode Μ and the source wiring 25. Fig. 18 is a plan view showing the source wiring 25, the source electrode 24, and the drain electrode as shown in Fig. 18, and the source electrode 24 It is branched from the source wiring 25 and has a linear shape extending over the active region layer AR, and the electrodeless electrode 26 has a linear 胄> extending along the gate wiring 4. In the above description, the M 〇 film is used as the second metal film 8 and the dry etching method using the I-type gas (SF6 + 〇 2 mixed gas) is described.

2108-7516-PF 21 1269449 ''However, the metal thin film material or etching process is not limited thereto, and for example, Τι may be used as the second metal thin film 8, and may be etched using an etching solution using hydrogen i acid + lithospermic acid system. Methods. Next, in the step shown by ® 14, the second insulating film 25 is formed to cover the transparent insulating substrate! All of the above, using the fourth photo-lithography step, in the region where the pixel electrode 30 (FIG. 2) is formed later, the formation of the pupil is reached; and the pixel of the surface of the electrode 26 is in contact with the hole 2 9 . 19 is a plan view showing a state in which the pixel drain contact hole 29 is formed on the gate electrode 26, and the description of the second insulating film 28 is omitted. Finally, after the transparent conductive film is formed to cover all of the transparent insulating substrate 1, the pixel which is electrically connected to the gate electrode 26 is formed via the pixel drain contact hole 29 by the fifth light lithography step. The electrode 30' can be made up to the TFT active matrix substrate 100 having the cross-sectional structure shown in FIG. 2, and more specifically, in the form of mixed indium oxide (?n2?3) by a known sputtering method using an Ar gas. After the tantalum film 2 having a thickness of about 100 nm from tin oxide (SnCh), in the fifth photolithography lithography step, a photoresist pattern of a portion where the pixel electrode 30 is formed by the photoresist is formed, and is used for transmission. A well-known wet etching method of a solution of hydrochloric acid + nitric acid removes the exposed ITO film 3 to form the pixel electrode 30. '<Α-3. Effect of Features> Embodiments of the invention described above! In the TFT active matrix substrate 100, when the source wiring 25, the source electrode 24, and the drain electrode 26 are formed, first, the unnecessary portion of the 2108-7516-PF 22 1269449 2 metal is removed by using the photoresist pattern RP1. After the film 8, the photoresist pattern Rpi is ashed, and the source wiring 25, the source electrode 24, and the electrodeless electrode 26 are patterned using the thinned photoresist pattern RP2, and the TFT channel portion is patterned. The TFT structure portion including the gate electrode 2, the gate insulating film 5, the active region layer AR source electrode 24, and the drain electrode 26 may be formed by photolithography of the U-coating process three times, and the manufacturing steps can be simplified. The unnecessary portion of the second metal thin film 8 spanning a wide area is removed by the photoresist pattern RP1, and the second metal thin film 8 and the ohmic contact film 7 are sequentially removed by etching through the opening of the photoresist pattern Rp2 to form TFT channel portion 27. Therefore, when the second metal thin film 8 is formed by the ohmic contact film 7 of the a_Si film of the a-Si film and the a_Si film of the a+Si film, or even if etching is performed without etching selectivity In the process, since the second metal thin film 8 and the ohmic contact film are removed with good controllability, the film thickness of the semiconductor film 6 constituting the TFT channel portion 27 can be accurately controlled, and variations thereof can be suppressed, so that variations in TFT characteristics can be prevented. The display of the liquid crystal display device is uneven. This is not limited to the case where a film of amorphous is used as the semiconductor film 6 and the ohmic contact film 7, and even in the case of using a polycrystalline germanium, the same effect can be obtained. Month / When the photoresist pattern RP1 is formed, half exposure is performed, and the mouth A_*' can form a region where the photoresist material is removed, and the region is used as the corresponding channel portion, and the ash is transmitted through the ash. The portion is removed, and the other portions are thinned, so that the size of the photoresist pattern RP2 in the planar direction (the outer shape T is smaller than the photoresist pattern RP1. ' 2108-7516-PF 23 1269449 through the use of photoresist In the pattern RP2, the outer shape of the second metal thin film 8 and the ohmic (four) film 7 forming the source electrode 24, the source wiring 25, and the secret electrode 26 is smaller than the outer shape of the semiconductor film pattern 6, and when viewed from above, The end faces of the source wiring 25 and the source electrode 24 are disposed to be located at a position retreating from either end surface of the semiconductor film 6, and the end faces of the electrodeless electrodes 26 on the active region layer ar may be disposed to be located at a ratio of the semiconductor film When the second metal thin film 8 and the ohmic contact film 7 are retracted at a position where the parallel end faces are retracted, even if the material constituting these is used as a conductive material and is attached to the button facet, the penetration can be prevented. Conductive material The gas is electrically conductive. The source is electrically #24 and the pole is not electrically 3526. Further, the above-mentioned approximately parallel is not limited to the patterning of the end face of the electrodeless electrode 26 to be parallel to the end face of the semiconductor film 6, and it is assumed that the gate can also be The end surface of the electrode 26 is formed to be inclined with respect to the end surface of the semiconductor film 6. The same phenomenon also occurs in the end faces of the source electrode 24 and the source wiring 25. This effect will be further described with reference to Fig. 20 and Fig. 21. Fig. 21 is a perspective view showing the formation of a TFT structure including an active region layer AR. Fig. 2G shows a state in which no conductive reattachment is formed, and a state in which no conductive reattachment cr is formed in 20 is shown. As shown in FIG. 2A, the conductive reattachment GR generated during the dry etching of the second metal thin film 8 and the ohmic contact film is mainly deposited on the edge of the semiconductor film 6. P is mainly in the semiconductor film 6. The deposition region on the surface has a length from the end surface of the semiconductor film 6 and a width of 〇2μη], along:

The edge portion of the body film 6 is deposited. The above average value of 〇·2μιη is actually from 0·Ιμιη to the maximum 〇. 3μιΙ1. < 2108-7516-PF 24 1269449 has a thickness of about 15 〇M, and the end surface of the semiconductor film 6 is approximately covered by the conductive reattachment CR. The conductive reattachment (3) is deposited on the edge portion of the semiconductor film 6. The drain electrode 24, the electrode electrode 26, and the underlying ohmic contact film 7 are deposited.

^The position near the end face of the Lei 6 6, the conductive reattachment CR becomes electric $, L 戌 leakage control, in the name of the mine; the electric wind conducts the source electrode 24 and the drain electrode 26 ' while the m is closed The possibility of the leakage current becoming larger. In the TFT active matrix substrate 100 of the first embodiment of the present invention, the ashing condition is set such that the end surface position of the photoresist (four) Rp2 is more than .3 μπι in the plane direction than the corresponding end surface of the photoresist pattern RP1, due to the use of the first The outer shape of the resist pattern RP2, the second metal thin film 8 and the ohmic contact film 7 pattern source electrode 24, the source wiring 25, the electrodeless electrode 26, and the lower layer of the ohmic contact film 7 can be changed to the outer shape of the semiconductor film 6. small. Therefore, even when the conductive reattachment CR is deposited on the edge portion of the semiconductor film 6 as shown in FIG. 21, the contact between the source electrode 24" and the lower layer of the ohmic contact film 7 of the electrode and the like can be prevented. The reattachment cr prevents the conductive re-adhesion CR from becoming a current leakage path to electrically conduct the source electrode 24 and the drain electrode 26, as described above, the film thickness of the thickness portion 2 of the photoresist pattern RP1 , a spoon 〇 4 μπι, which is a value considering the controllability according to the half exposure, and a value considering the back distance of the end face of the photoresist pattern RP2 at the same time. That is, the first thickness portion 2 is permeable to oxygen plasma. The ashing is completely removed, and in the ashing, the setting conditions are used to make the photoresist pattern approximately equitectively and even at any position at about the same ashing speed.

2108-7516-PF 25 1269449 The end face of the RP2 is ashed to about 4 μm, and as a result, the end face of the photoresist pattern Rp2 is retracted by about 〇4_ from the photoresist pattern RP1. Since this value is larger than the maximum width 〇·3 μm of the conductive reattachment CR, the formation of a current leakage path by the conductive reattachment CR can be surely prevented. As described above, by performing the isotropic ashing, there is an advantage that the receding distance of the end surface of the resist pattern RP2 can be set in accordance with the thickness of the second thickness portion 20. In the TFT active matrix substrate 1 of the first embodiment of the present invention, as described using FIG. 5, the pixel display region on which the pixel electrode 3 is formed is patterned so that the semiconductor film 6 and the ohmic contact film 7 are not The semiconductor film 6 and the ohmic contact film 7 are not present in the lower portion of the gate electrode 26 extending to the pixel display region. Therefore, when the TFT active matrix substrate ι is used in the transmissive liquid crystal display device in which the backlight is irradiated to the pixel display region, since the semiconductor film 6 of the a-Si film is not irradiated with light, and current due to photoexcitation can be suppressed This occurs to prevent deterioration of the shutdown characteristics of the thin film transistor. <A-4. Modifications> In the example 1 +, the example in which w 7 and FIG. 8 are used, an example in which the two-stage exposure is performed to form the photoresist pattern RP1 is shown, but the present invention is not limited thereto, and may be used once. The exposure forms a photoresist pattern RP1. That is, as shown in Fig. 22, the portion corresponding to the half-exposure region 19 is a semi-transmissive region in which the amount of light to be exposed is 20 to 40%, and the transmissive region 33 having complete transmission of light can be used and completely covered. The mask R3 of the light-shielding region 32 of the light that has been exposed is exposed to a positive-type photoresist 9 of a phenol resin type.

2108-7516-PF 26 .1269449 The mask R31 having the semi-transmissive region 34 can reduce the transmission amount of the light 13 in the wavelength region for exposure (usually 350 nm to 450 nm) to 2 〇 to 40%. A pattern formed at a position corresponding to the semi-transmissive region 34 or a semi-transmissive region 34 having a slit opening shape is formed by a light diffraction phenomenon. When the mask R31 having the semi-transmissive regions 34 is used, the photoresist patterns RP1 having the first to third thickness portions 20, 21, and 22 shown in FIG. 9 can be formed together by one exposure, thereby simplifying the light. Etching the lithography step. <Β·Example 2><Β-1 _Device configuration> The electro-optical display device according to the second embodiment of the present invention includes a self-luminous type of an organic electroluminescence (EL) element using a TFT as a switching element. The planar configuration of the TFT active matrix substrate 200 of the organic EL display device is shown in Fig. 23, Β-0-Β in Fig. 23, and the cross-sectional configuration of the line is shown in Fig. 24. 23 is a plan view showing one pixel on the TFT active matrix substrate 200, and these pixels are plurally arranged in a matrix on the TFT active matrix substrate 200. In FIGS. 23 and 24, the same components as those of the TFT active matrix substrate 100 shown in FIG. 1 and FIG. 2 are denoted by the same reference numerals, and the description thereof will not be repeated. As shown in FIG. 23, a part of the transparent insulating substrate 1 such as a glass substrate is provided with a closed wiring 4 constituting a gate electrode 2. The gate wiring 4 is disposed so as to extend linearly in one direction on the transparent insulating substrate ,. Here, the direction is referred to as the X direction, and the direction orthogonal to the χ direction in the plane is referred to as the Υ direction. 2108-7516-PF Bamboo 1269449 A linear semiconductor laminate film is placed in the upper side of the gate wiring 4

SL provides a large pixel area 40 in the X direction

The active region layer formed by the portion of the semiconductor film 6 of the boring blade' is provided with a linear source wiring 25 along the semiconductor laminated film SL in the upper portion of the semiconductor laminated film SL. Similarly to the semiconductor laminated film SL, the source wiring 25 is branched at the intersection with the gate wiring 4, and has a portion extending along the gate wiring 4, and this portion constitutes the source electrode 24 of the TFT. Further, an ohmic contact film 7 is present under the source electrode 24. Further, the drain electrode 26A is disposed such that the upper source electrode 24 and the source wiring 25 of the transparent insulating substrate 1 extending from the active region layer ar to the lower side of the φ anode electrode 38 (pixel electrode) are disposed. The end surface is located at a position retreating from either end surface of the semiconductor film 6, the active region layer ar, and the end surface of the electrode electrode 26A are also disposed to be located at a position retreating from an end surface parallel to the semiconductor film 6. Further, the above-mentioned approximately parallel is not necessarily limited to patterning the end face of the electrodeless electrode 26A to be parallel to the end face of the semiconductor film 6, and it is also possible that the end face of the electrodeless electrode 26A is formed with respect to the end face of the semiconductor film 6. tilt. The same phenomenon occurs in the end faces of the source electrode 24 and the source wiring 25, 2108-7516-PF 28 1269449. In the active region layer A R , the source electrode 24 and the electrodeless electrode 26 are spaced apart from each other, and the semiconductor film 6 between them becomes the m channel portion 27. Further, at a position parallel to the TFT channel portion 27 of the electrodeless electrode 26, an anode to the anode electrode 38 and a contact hole μα are provided: a frame 41 is provided to surround the pixel region 40, and an electroluminescent layer 42 is provided. An anode electrode 38 having a region larger than the surface of the electroluminescence layer 42 is provided in a region having a larger-number than the edge portion of the frame 41. The cathode electrode is provided integrally on the display region in which the pixels are arranged in a plurality of manners in the form of a moment p. Further, the mother storage device is electrically slid and sealed with an inert gas such as Ar or a sealing material such as nitrogen gas, and the illustration thereof is omitted. . Next, the cross-sectional configuration of the TFT active matrix substrate 2A will be described with reference to FIG. 24. As shown in FIG. 24, the closed electrode 2 (gate wiring 4) is disposed on the transparent insulating substrate i, and the ith insulating film is disposed. 5 covers all of the transparent insulating substrate 1 and includes a gate electrode 2 (gate wiring 4). Further, the function of the "j insulating film 5 is disposed above the gate electrode 2 as the interpole. The semiconductor film 6 is disposed on the first insulating film 5, and the ohmic contact film 7 is disposed on the semiconductor film 6. . Further, the ohmic contact film 7 is not disposed on the portion of the semiconductor film 6 that becomes the tft channel portion 27. A source wiring 25 is disposed on an upper portion of the ohmic contact film 7, and an upper portion of the ohmic contact film 7 in the active region layer AR is located in the TFT channel portion 27 and is divided into a portion where the source electrode 24 is disposed and a drain electrode is disposed. Portion of electrode 26. 2108-7516-PF 29 1269449 The drain electrode 26 extends from the upper portion of the ohmic contact film 7 to the side surface of the semiconductor film 6 and the upper portion of the first insulating film 5. Further, the second insulating film 28 is disposed so as to cover all of the transparent insulating substrate, and includes the source wiring 25, the source electrode 24, and the drain electrode 26. In addition, an interlayer insulating film 36 made of a photosensitive organic resin film is disposed so as to cover all of the second insulating film 28, and is provided to penetrate the interlayer insulating film 36 and the second insulating film 28 to reach the gate electrode 26A. The anode drain contact hole 29A is provided with a reflection film 38a to cover a portion corresponding to the pixel region 40 of the interlayer insulating film 36 while covering the inner surface of the anode electrodeless contact hole 29A and contacting the electrode electrode 26A. Further, an ITO film 3 is disposed on the reflection film 38a, and the anode electrode 38 is constituted by the reflection film 38a and the ITO film 38b. A bezel layer 41 made of an organic resin is provided to surround the pixel region 40', and the portion corresponding to the pixel region 40 becomes the opening portion 5A. The frame layer 4i is provided to be a flat surface on the interlayer insulating film 36 between adjacent pixels. An electroluminescent layer 42 is disposed on an upper portion of the anode electrode 38 corresponding to the bottom surface portion of the opening portion 50, and a cathode electrode 43 is provided to cover the flat surface of the frame layer 4i while covering the inner surface of the opening portion 5〇 and contacting The electroluminescence layer 42 is covered with an encapsulating material 44 such as an inert gas such as Ar or a nitrogen gas, in a display region including the cathode electrode 43 and the pixels are arranged in a matrix. The package material 44 is terminated outside the display region, and the dangerous electrode 43 is configured to be electrically connected to the ground terminal of the terminal connection portion for inputting a signal from the outside of the display region.

2108-7516-PF 30 1269449 <Β-2·Manufacturing method> Next, a method of manufacturing the TFT active matrix substrate 2A will be described with reference to Figs. 25 to 39 in which the cross-sectional views of the manufacturing steps are sequentially displayed. The section shown in Fig. 2 corresponds to the section of the line 6_〇__ of Fig. 1. 40 to 46 are plan views showing the respective steps. First, in the step shown in FIG. 25, after forming a first metal thin film (not shown) on the transparent insulating substrate 1 such as a glass substrate, at least the gate electrode is patterned by the first photo-etching lithography step. 2 and gate wiring 4. Here, as the first metal thin film, it is preferable to use an alloy having a low electrical resistance value of A1 or Mo or the like as a main component. Further, the manufacturing method suitable for the first metal thin film is the same as the method described in the first embodiment, and thus the description thereof will be omitted. 40 is a plan view showing the gate electrode 2 and the gate wiring 4 formed on the transparent insulating substrate 1. In the step shown in FIG. 26, the first insulating film is formed to cover all of the transparent insulating substrate 1, and after covering the gate electrode 2 (gate wiring 4), the semiconductor film 6 is formed on the first insulating film 5. Further, an ohmic contact film 7 is formed thereon. Thereafter, the semiconductor film 6 and the ohmic contact film 7 are patterned by the second photo-etching lithography step. At this time, a linear semiconductor laminated film SL' is provided, and an active region layer ar for forming a TFT is also provided. The method of manufacturing the semiconductor film 6 and the ohmic contact film 7 is the same as that of the method described in the first embodiment, and thus the description thereof will be omitted. 41 is a view showing formation of a semiconductor laminated film SL and an active region layer AR.

2108-7516-PF 31 1269449 A plan view partially overlapping the gate electrode 2 and the gate wiring 4. The semiconductor film 6 is basically provided to constitute the active region layer AR', but can be used as a constituent element of the linear semiconductor laminated film SL formed to overlap the formation region of the source wiring formed later. As a redundant wiring of the source wiring, electrical signal interruption can be prevented even when the source wiring is broken. Next, in the step shown in Fig. 27, a second metal thin film is formed to cover all of the transparent insulating substrate 1. Further, the manufacturing method suitable for the second metal thin film 8 is the same as the method described in the embodiment, and therefore the description thereof will be omitted. Next, in the steps shown in FIGS. 28 to 30, the photoresist 9 is formed to cover all of the second metal thin film 8, and the photoresist 9 is patterned by the third photo-etching lithography step to form light. Resistance pattern. Incidentally, the method of forming the photoresist pattern RP1 is the same as the method described with reference to Figs. 7 to 9, and therefore the description thereof will be omitted. Next, in the step shown in Fig. 31, the second metal thin film 8 is etched by using the photoresist pattern RP1 as a mask. Here, etching is performed by a known dry etching method using a mixed gas of SFe gas + 〇2 gas. Fig. 42 is a plan view showing the formation of the second metal thin film 8 extending from the semiconductor laminated film on the active region layer AR to the region where the anode electrode 38 (Fig. 24) is formed later. In addition, in FIG. 42, the description of the photoresist pattern RP1 is omitted, and it is needless to say that the pattern RP is stored on the upper portion of the second metal thin film 8, and secondly, in the step shown in FIG. 32, a known method of transmitting oxygen plasma is used. Photoresist ashing, using a comprehensive thinning of the photoresist pattern Rpi to remove the photoresist

2108-7516-PF 32 1269449 The first thickness portion 2 of the pattern RP1 is 2〇, and the second thickness portion 21 and the third thickness portion 22' remain, and the portion corresponding to the channel portion 27 (FIG. 24) of the TFT is formed as the opening portion 23 The photoresist pattern Rp2. At this time, as the film is formed in a comprehensive manner, as shown in Fig. 32, the conditions of the photoresist ashing are set so that the size (outer shape) in the plane direction of the photoresist pattern Rp2 becomes smaller than the photoresist pattern RP1. In the step shown in Fig. 33, the second metal film 8 and the ohmic contact film 7 are sequentially removed by etching through the opening portion 23' of the photoresist pattern rP2. Since the etching method suitable for these films is the same as that described in the embodiment, the description thereof is omitted. Further, the second metal thin film 8 patterned by etching is used as the source wiring 25 on the semiconductive volume layer film SL, and becomes the source electrode 24 and the drain electrode 26A in the active region layer AR. The drain electrode 26A is patterned to extend from the active region layer AR to a region where the anode electrode 38 (Fig. 24) is formed later. P Then, by removing the photoresist pattern RP2, as shown in Fig. 34, the source wiring 25 is disposed on the semi-conductive volume film SL, and the source electrode 24 and the drain electrode 26A are disposed on the active region layer ar. The photoresist pattern RP2 has a smaller outer shape than the photoresist pattern βρι, and the outer shape of the second metal thin film 8 and the ohmic contact film 7 forming the source electrode 24, the source wiring 25, and the drain electrode 26A is lower than that of the lower layer. The outer shape of the semiconductor film 6 is small. When viewed from above, the end faces of the source wiring 25 and the source electrode 24 may be disposed so as to be located at a position where the end surface of the semiconductor film 6 retreats from the end surface of the semiconductor film 6 The end face of 26A may be provided with a position of 2108-7516-PF 33 1269449, which is a position retracted from an end face approximately parallel to the semiconductor film 6. Further, the above-mentioned approximately flat is not necessarily limited to patterning the end face of the gate electrode 26a to be parallel to the end face of the semiconductor film 6, and it is assumed that the end face of the electrodeless electrode 26A is formed to be inclined with respect to the end face of the semiconductor film 6. The same phenomenon also occurs in the end faces of the source electrode Μ and the source wiring 25. 43 is a plan view showing the source wiring 25, the source electrode 24, and the drain electrode 26α. As shown in Fig. 43, the source electrode 24 is branched from the source wiring 25 and has a linear shape extending over the active region layer AR. In the step shown in FIG. 35, after the second insulating film 28 is formed to cover all of the transparent insulating substrate, the interlayer insulating film 36 made of a photosensitive organic resin film is applied, and the first layer is used. The fourth photo-etching lithography step 'forms a contact hole 2 9A that penetrates the surface of the electrodeless electrode 26 A. In addition, since the manufacturing method suitable for the second insulating film 28 is the same as that described in the first embodiment, the description thereof is omitted. As a method for producing the interlayer insulating film 36, a spin coating method is used. • A acryl-based photosensitive resin film, for example, a product name pC335 manufactured by JSR, having a film thickness of about 2 μm is applied. Through the fourth photo-etching lithography step, a contact hole penetrating the interlayer insulating film 36 and reaching the surface of the second insulating film 28 is formed. Further, by using a known fluorine-based gas, the second insulating film 28' on the bottom surface of the contact hole is removed by etching to obtain an anode-drain contact hole 29 which reaches the surface of the gate electrode 26A. FIG. 44 is a plan view showing the gate electrode 26Α. In the state in which the anode drain contact hole 29A is formed, the description about the second insulating film 28 is expediently omitted. 2108-7516-PF 34 1269449 Next, in the step shown in FIG. 36, a third metal thin film (not shown) is formed to cover all of the transparent insulating substrate 1, and the photo-etching lithography step is performed for the first time. An anode electrode 38 is formed on the pixel region 40 (Fig. 24). Fig. 45 is a plan view showing a state in which the anode electrode 38 is formed on a portion corresponding to the pixel region. Here, as a method for producing a third metal thin film, a reflective film 38 & of a thickness of about 30 Å, which is made of a cerium alloy containing A1 (aluminum) as a main component, is formed by a known sputtering method, and then a splash is used. A non-crystalline IT(a-lTO) film 38b having a thickness of about 1 〇 (10) was formed by plating. Thereafter, the photoresist pattern is formed by the fifth photolithography lithography step described above, and the % electrode 3 8 is patterned by engraving. Although the known dry etching method can be used in the same manner as the first and second metal thin films described above, the IT0 film 38b can be etched by an etching liquid for the A1 alloy composed of phosphoric acid + nitric acid + acetic acid. Therefore, a method of etching the lower layer of the reflective film 38a of the A1 alloy and the upper layer of the ιτ film 38b together with a solution containing phosphoric acid + nitric acid + acetic acid may be employed. The other advantage that the I TO film 38b can be etched together with the lower reflective film 38a, since the work function has a value of about 5. OeV higher than that of the A1 alloy of about 4. 〇eV, the injection can be improved to organic The efficiency of the hole carriers of the electroluminescent layer composed of the ruthenium material or the like has an advantage of improving the light-emitting efficiency of the organic EL display element. Further, since the IT0 film 38b is in an amorphous state, unlike the polycrystal, there is almost no surface unevenness due to the presence of grain boundaries, and it is possible to prevent poor display of light emission due to poor hole carrier injection caused by surface unevenness.

2108-7516-PF 35 1269449 The I? film 38 having an amorphous state having such advantages can be formed by, for example, a sputtering method in which a mixed gas of water (LO) gas is added to an Ar gas. Further, instead of the ΙΤ0 film 38b, a ruthenium film in which indium oxide (ΐη〇3) and zinc oxide (ΖηΟ) are mixed, or a ruthenium film in which zinc oxide (ΖηΟ) is mixed on the ιτο film may be used. The I Ζ 0 film or the I ΤΖ 0 film may be etched with an oxalic acid-based etching solution, or may be etched simultaneously with the lower-layer reflective film 38a by etching using a known etching solution of a ruthenium-doped alloy containing phosphoric acid + nitric acid + acetic acid. Next, in the step shown in Fig. 37, in order to provide the pixel region 40 (Fig. 24) for forming an organic EL layer as an electroluminescent layer, first, an organic resin layer composed of polyamine or the like is formed by coating. The entire surface of the transparent insulating substrate 1 is covered, and the sixth photolithographic lithography step is performed to form the frame layer 4 ι which becomes the opening portion 5 部分 in the portion corresponding to the pixel region 40 . It is preferable that the organic resin film forming the frame layer 41 is a polyilylimine-based material which has little water absorption which affects the characteristics and reliability of the organic EL layer. As a method for producing the frame layer 41, a material having a product name circle of Toray manufactured by a thickness of about 2 μm is applied, and an opening having a surface reaching the anode electrode 38 is formed by etching using the sixth photolithography lithography step. The frame layer 41 is a plan view showing a state in which the frame layer 41 having the opening portion 50 is formed on a portion corresponding to the pixel region * 以 in plan view. Next, in the step shown in Fig. 38, an organic EL material is formed on the surface of the anode electrode 38 exposing the bottom surface of the opening portion 5A to obtain an electric shock.

2108-7516-PF 36 1269449 Light-emitting layer 42 As a method for producing the electroluminescent layer 42, a well-known vapor deposition method can be used to sequentially deposit a layer on the anode electrode 38 to obtain a hole transport layer, an organic EL layer, and an electron. Transport layer. Here, as the hole transport layer, a well-known triarylamine (1:1^311 & 111丨1^), aromatic 腙(]^(^&20116), aromatic-substituted azole Wide range of organic materials such as (pyrazoline), stilbene, etc., for example, _N-Dipheny1-N, N-Bis (3-methy1 phenyl) having a film thickness of 1 to 2 〇〇 nm -1, Γ-Diphenyl-4, 4' diamine (TPD), etc. Also, as the organic EL layer, a well-known dicyanomethy 1 enepyran inducer (red luminescence) and a coumar ine system (green luminescence) having a film thickness of 1 to 20 nm are formed. Materials such as quinacridone (green luminescence), terraphenyl butadiene (blue luminescence), and distyrylbenzene (blue luminescence). _ As an electron transport layer, a known thickness of oxiadiazole inducer, triazole inducer, In the above, the electroluminescent layer 24 is formed by sequentially laminating the hole transport layer, the organic EL layer, and the electron transport layer. In order to increase the light emission rate of the electroluminescence layer, electricity can also be used. Hole transport layer becomes hole injection layer The two-layer structure of the hole transport layer and the electron transport layer become a two-layer structure of the electron transport layer and the electron injection layer. Next, in the step shown in Fig. 39, a transparent guide 2108-7516 of the IT film or the like is formed. PF 37 1269449 The electric film covers all of the transparent insulating substrate 1 including the inner surface of the opening 50, and the cathode electrode 43 is formed by the seventh photolithography process. The cathode electrode 43 serves as the anode electrode 38. The counter electrode is formed with the electroluminescent layer 42 interposed therebetween, and is configured to be connected to the lower electroluminescence layer 42 in the pixel region 4A. Further, the main surface of the cathode electrode 43 preferably has a south flatness. θ As a method for producing the cathode electrode 43, a non-crystalline a-ITO film having a thickness of 1 〇〇 nm can be formed by sputtering in a gas in which an IM gas is mixed in an Ar gas. Thereafter, a photoresist pattern is formed by a photolithography lithography step, and after etching with a known oxalic acid-based etchant, the photoresist pattern is removed to obtain a cathode electrode 43. Further, as the cathode electrode 43, ITO can be used. The diaphragm or ITZ diaphragm replaces the a-1 TO membrane. Finally, in order to prevent the light emission of the display panel caused by moisture or impurities, the display area containing the electroluminescence light is enclosed by an insulating material such as an inert gas such as Ar or a nitrogen gas. TFT A TFT active matrix substrate 200 having a cross-sectional structure as shown in FIG. 24 can be obtained.

Further, as the encapsulating material 44, a transparent glass material is used, and a sealing agent is formed on the outer peripheral portion of the display panel of the FT-movable matrix substrate 200, and the package is formed by pressing. <Β~3· Effect of Features> The TFT active matrix substrate 2 of the second embodiment of the present invention described above

In 2108-7516-PF 38 1269449, a TFT structure composed of a gate electrode 2, a gate insulating film 5, an active region layer AR, a source electrode 24, and a electrodeless electrode ^ can be formed by a photo-etching lithography step of a 3-person Department, which simplifies the manufacturing steps. Further, the unnecessary portion of the second metal thin film 8 spanning a wide area is removed by the photoresist pattern RP1, and the second metal thin film 8 and the ohmic contact film are sequentially removed by etching through the opening portion 23 of the photoresist pattern Rp2. The TFT channel portion 27 is formed. _ Therefore, when the second metal thin film 8 is formed by the ohmic contact film 7 of the a-Si film semiconductor film 6 and the n+ a_Si film and the metal film which is not subjected to the selective selectivity, or even if no etching selectivity is used In the etching process, since the second metal thin film 8 and the ohmic contact film 7 are removed with good controllability, the film thickness of the semiconductor film 6 constituting the TFT channel portion 27 can be accurately controlled, and variations thereof can be suppressed, so that TFT characteristics can be prevented. The display of the organic anal display device caused by the change is uneven. By the etching using the photoresist pattern RP2, the outer shape of the second metal thin film 8 and the ohmic contact film 7 forming the source electrode 24, the source wiring 25, and the drain electrode 26A is made smaller than the outer shape of the semiconductor film pattern 6. When viewed from above, the end faces of the source wiring 25 and the source electrode 24 are disposed so as to be located at a position retracted from either end surface of the semiconductor film 6, and the end faces of the gate electrodes 26 on the active region layer AR can be disposed. When the second metal thin film 8 and the ohmic contact crucible 7 are dry-etched at a position retreating from the end surface approximately parallel to the semiconductor film 6, even if a substance constituting these is used as a conductive material and then adhered to the etching surface, It is prevented that the source electrode 24 and the drain electrode 26 are electrically conducted through the conductive material.

2108-7516-PF 39 1269449 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing the configuration of a TFT active matrix substrate according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the configuration of a TFT active matrix substrate according to a first embodiment of the present invention. Fig. 3 is a plan view showing a state in which the TFT active matrix substrate of the first embodiment of the present invention is arranged in a matrix. Fig. 4 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the first embodiment of the present invention. Fig. 5 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the first embodiment of the present invention. ® 6 is a cross-sectional view showing a manufacturing step of the TFT active matrix substrate of the first embodiment of the present invention. Fig. 7 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the first embodiment of the present invention. Fig. 8 is a cross-sectional view showing the steps of the TFT active matrix substrate of the first embodiment of the present invention. Fig. 9 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the first embodiment of the present invention. Fig. 1 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate of a first embodiment of the present invention. Fig. 11 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the first embodiment of the present invention.

Figure 12 is a cross-sectional view showing the manufacturing steps of 2108-7516-PF 1269449 of the TFT active matrix substrate of Embodiment 1 of the present invention. Figure 13 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate of an embodiment j of the present invention. Figure 14 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate according to Embodiment 1 of the present invention. Figure 15 is a plan view showing the manufacturing steps of the active matrix substrate in accordance with an embodiment of the present invention. Fig. 16 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the first embodiment of the present invention. Figure 17 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the first embodiment of the present invention. Figure 18 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the first embodiment of the present invention. Fig. 19 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the first embodiment of the present invention. Fig. 20 is a perspective view showing a TFT construction portion. Fig. 21 is a perspective view showing a TFT structure portion in which a conductive reattachment is formed. Figure 22 is a cross-sectional view showing a modification of the manufacturing procedure of the TFT active matrix substrate of the first embodiment of the present invention. Figure 23 is a plan view showing the configuration of a TFT active matrix substrate according to a second embodiment of the present invention. Figure 24 is a cross-sectional view showing the configuration of a TFT active matrix substrate according to a second embodiment of the present invention. 2108-7516-PF 41 i269449 Fig. 25 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the second embodiment of the present invention. Figure 26 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate according to a second embodiment of the present invention. Figure 27 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate according to a second embodiment of the present invention. Figure 28 is a cross-sectional view showing the steps of fabrication of the TFT active matrix substrate of the second embodiment of the present invention.

Figure 29 is a cross-sectional view showing the steps of wearing the TFT active matrix substrate of the second embodiment of the present invention. Figure 30 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate according to a second embodiment of the present invention. Figure 31 is a cross-sectional view showing a manufacturing step of a TFT active matrix substrate according to a second embodiment of the present invention. Figure 32 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the second embodiment of the present invention. Figure 33 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the second embodiment of the present invention. Figure 34 is a cross-sectional view showing a manufacturing step of a TFT ± moving matrix substrate according to a second embodiment of the present invention. Figure 35 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the second embodiment of the present invention. Fig. 36 is a cross-sectional view showing the steps of manufacturing the TFT of the second embodiment of the present invention.

2108-7516-PF 42 .1269449, FIG. 37 is a cross-sectional view showing a gas-making step of the TFT active matrix substrate of Embodiment 2 of the present invention. Figure 38 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the second embodiment of the present invention. Figure 39 is a cross-sectional view showing the steps of manufacturing the TFT active matrix substrate of the second embodiment of the present invention. Figure 40 is a plan view showing the manufacturing process of the TFT active matrix substrate of Embodiment 2 of the present invention. Figure 41 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the second embodiment of the present invention. Figure 42 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the second embodiment of the present invention. Figure 43 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the second embodiment of the present invention. Figure 44 is a plan view showing the manufacturing steps of the TFT active matrix substrate of Embodiment 2 of the present invention. Figure 45 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the second embodiment of the present invention. Figure 46 is a plan view showing the manufacturing steps of the TFT active matrix substrate of the second embodiment of the present invention. [Main component symbol description], 4 gate wiring, 6 semiconductor film, 2108-7516-PF 43 1269449 7 ohm contact film, 8 second metal film, 23 opening, 24 source electrode, 25 source wiring, 26 汲Polar electrode, 27 TFT channel portion, 30 pixel electrode, AR active region layer, RP1, RP2 photoresist pattern. ❿

2108-7516-PF

Claims (1)

1269449 X. Patent application scope: 1. An electro-optical display device 'includes an active matrix substrate, having: an insulating substrate; a plurality of display pixels arranged in an array on the insulating substrate to have an electrically connected thin film electric a pixel electrode of the crystal; a gate wiring, sequentially scanning and selecting the thin film transistor; and a source wiring, and an electrical signal is given to the pixel electrode; and the gate wiring is orthogonal to the source wiring plane And the thin film electromorphic system has: an active region layer, a semiconductor film bifurcation disposed under the source wiring; and a source electrode and a drain electrode on the active region layer Having a space and optionally being disposed; at least the source electrode is disposed on the active region layer such that the end surface position thereof is located at a position more than a predetermined distance from any end surface of the active region layer The foregoing drain electrode is disposed to extend from the active region layer to the pixel display region Above the edge of the substrate; without the active region layer on the pixel display region of a lower layer of the drain electrode. 2. The electro-optical display device according to claim 1, wherein the predetermined distance is 0.3 μm. 2108-7516-PF 45 1269449 3. A method of manufacturing an electro-optical display device, wherein the electro-optical display device comprises a line matrix substrate, and (4) the (four) material substrate has: a matrix-shaped device that is orthogonal to the wiring plane The manufacturing method includes: an insulating substrate; a plurality of & pixels, a pixel electrode having an electrically conductive (tetra) thin film transistor on the insulating substrate; and an interpolar wiring, wherein the thin film transistor is sequentially selected; a source wiring for giving an electrical signal to the pixel electrode; and the gate wiring and the source electrode are described as an electron optical display (a) a step of patterning the gate wiring by forming a first conductive film on the front substrate, and then patterning the gate wiring; (b) above the gate wiring After the insulating film, the semiconductor film, and the ohmic contact film are sequentially formed, the second photo-etching lithography is performed, and the semiconductor film and the ohmic contact film are patterned to form a lower film of the source wiring, and a sub-film is formed. a step of the semiconductor film bifurcated active region layer; and (C) after the step (b), after forming the second conductive film across the entire insulating substrate, the second conductive film Step (c): (c-1) performing a third photoetching lithography on the second conductive film to extend from the underlayer film and the active region layer to the pixel a step of forming a light-emitting resist pattern on the upper surface of the display region corresponding to the channel portion of the thin film transistor; and forming a thinner photoresist pattern on the other portion; 2108-7516-PF 46 1269449 1 on the photoresist pattern (c-2) removing the second conductive thin film not covered by the etching; (4) after the step (c-2), ashing and thinning the ith photoresist pattern while removing the pair of channels , j ^. a step of forming a second photoresist pattern as the opening 4; and (c-4) sequentially removing the second portion corresponding to the channel portion by using the opening through the second photoresist pattern The conductive film and the ohmic contact film simultaneously remove the second conductive film and the ohmic contact film that do not cover the second photoresist pattern, and sequentially leave a gap between the active region layer and the source electrode. The step of patterning the drain electrode and patterning the source wiring at the same time. 4. The method of manufacturing an electro-optical display device according to claim 3, wherein the step (c-3) includes a ashing speed of the photoresist remaining on the channel corresponding portion. The ashing step is performed under the condition that the ashing speed of the side surface of the first photoresist pattern is the same. 5. The method of manufacturing an electro-optical display device according to claim 3, wherein the step (cl) comprises: using a positive photoresist as the photoresist material of the first photoresist pattern; The exposure intensity of the channel corresponding portion of the first photoresist pattern is a half exposure of 20 to 40% of the exposure intensity of the other portion. 2108-7516-PF