TWI269136B - Stabilizing power circuit - Google Patents
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!269136 九、發明說明： 【發明所屬之技術領域】 本發明係關於―穩^化電源電路，用以使例如PC(個人 電腦）板等電子電路零件所使用之直流電源穩定。 【先前技術】 '近年來要設計PC板等電子電路零件之直流電源穩定化 电源電路時’ & 了電路本身之省空間化及低成本化之觀點 外’為了要避免穩定化電源電路發生之電源雜訊所引起的 零件全體之誤動作或破壞，已致力於盡量抑制電源雜訊。 特別，對電源雜訊，要求電源投入時（起動時）之過衝 (overshoot)之抑制，能抑制此過衝之穩定化電源電路正 開發中。 圖3,係表示日本特開平1〇 — 1 61 758號公報所揭示之習 知i C化之穩定化電源電路之構成。 在圖3所示之穩定化電源電路，藉由驅動電壓（從透過 電=線VDD(電源電壓VDD)輸入之電屢取出）而成為⑽動^ 之電流放大電路101的P通道FETQn，係將輸出電壓 輸出於輸出端子105，而此輸出電壓νουτ，係當作藉由電 流增強（current booster)電路101之電阻R11及R1 3所構 成之串聯電路（分壓電路）分壓之連接點N之電壓而被檢 測’此檢測電壓Vdet，回授至在差動放大電路1〇7作差動 動作之一對（差動對）P通道FETQ13及Q15中之fETQ15之閘 才系〇 構成差動放大電路107之差動對之FETQ13及Q15之負 1269136 載，係作 Q19 〇 電流鏡連接之構成電流鏡電路之N通道FETQ17及 另一方面’在差動放大電路1〇7之另一 p通道FETQ13 之閘極’藉由定電壓源1 〇9施加基準電壓Vr。 1驅動 若基準電壓Vr >檢測電壓vdet之情形 用之N通道FETQ21之閘極電壓則增大。 此％，因FETQ21之源極側接地，汲極側連接於 =閘極，且透過電阻R15連接於電源線VDD，故當肫邛21 完全成為ON時，FETQ11之閘極則大致成為接地電位。 其結果’FETQ11變成0N使輸出端子1〇5之輪出電壓增 大，以分壓電路所分壓之檢測電壓Vdet亦上升。 另一方面，藉由檢測電壓心之上升而成為基準電壓 Vr〈檢測檢測Vdet之情形，FETQ1!驅動用之n通道fetq2 ^ 之閘極電壓則減少而變成〇FF。 此時，目FETQ21及FETQ11係如上述之連接關係，告 FETQ21完全變成0FF時，FETQU之閘極則大致成為電源^ 壓VDD’其結果，FETQ11變成〇FF而使輸出端子ι〇5之輪 出電壓Vout減少，以分壓電路所分壓之檢測電壓“Μ 2 減少。 如上述，以產生於連接點N之電壓Vdet與基準電壓許 一致之方式使輪出電壓穩定化。 在此’在如上述構成之穩定化電源電路之電源電壓投 入時，基準電M Vi-定，相對於此，輸出電壓_係 0V，因此檢測電壓Vdet亦係〇v，故FETQ21及FETQH分別 1269136 變成⑽，使輸出電壓v〇ut急劇上升。 此時，差動放大電路i07不能追隨上述輪出電屢⑽ 之急劇變化，即使輸出電塵Vout到達基準電麗Vr，因不能 迅速使FETQ21 OFF，故會有使輸出電壓v〇ut過衝之虞。 此點，在圖3所示之穩定化電源電路，在分塵電路之 輸出點（連接點N)(連接於差動放大電路107之差動對 (FETQ13及Qi5)之檢測電壓側的FETQ15之閘極）與輪出端 子1〇5(或接地端子GND)之間與分壓電路之電阻並聯= 入電容器cu，以此電容器C11使對輸出電壓v〇ut之變卩化 的1動放大電路107之動作（差動對FETQ13及以5之動作） 速度加快而使FETQ21之0N/0FF速度上升，藉此來抑制上 述過衝發生。 /然而，在上述習知之穩定化電源電路，電源起動時之 過衝之抑制期間，係由依據分壓電路之電阻Ri丨之電阻值 (設為R11)與插入電容器C11之電容值（設為cu)所定之時 間常數（R11 C11 )來決定。 因此，為了要更有效地抑制過衝，需要使時間常數 _ M1C11增大，在分壓電路之電阻R11之電阻值小之情形下， 插入電容器則必須使用例如鋁電解電容器等之大電容的電 容器。 。此種大電容的電容器，因成本昂貴，故不能使穩定化 電源電路低成本化，其結果致使組裝有穩定化電源電路之 Pc板等電子電路零件之成本增加。 又，鋁電解電容器等之大電容的電容器，其尺寸亦大， 1269136 因此，使穩定化雷 化，其結果，^路（Ic化時係1C本身）之尺寸大型 電子電路零件内的省==穩定化電源電路之pc板等 【發明内容】 本發明有鑒 本及/或尺寸辦力a月形而為’其目的在於提供：不使成 .&2 ^ g 能抑制過衝之穩定化電源電路。 為解決上述eg 路，係具備：1喊’本發明之第1特徵之穩定化電源電 $壓輸出電路，將所供應之電源電壓藉由主動負載元 件控制成穩定化之於φ千广 秸田主勳負載兀 、 輪出笔壓而從輸出端子輸出·， 差動放大電路，且右•锋 以產生彳1私山一 及第2差動對電晶體，用 ^ Λ Μ電壓所檢測之檢測電壓與基準電#之門 差電壓；電流鏡雷败—人、 土十罨复之間的 ^ 路，匕3勿別連接於該第1及第2莫黏 對電晶體且透過連接點棘、 差動 、逆筏點被此形成電流鏡連接的 電晶體；及輸出雷a， ± 及弟4 铷出电曰曰體，用以輸出依據所產 該電流鏡電路之主動倉都的 电i及 吩心王勡員载的差動放大信號； 驅動電路，按昭戶斤齡φ & 牧…、所輸出之差動放大信號對該主 兀件輸出控制信號；及 動負載 降低阻抗用電路’連接於該輸出端子 之連接點間，以使該連接點之交流阻抗降低。動放大琶路 依本發明之第"寺徵，因藉由連接於輸 放大電路之電流鏡電路之連接點間的降低㈣路差2 , 連接點之交流阻抗降低’故能使輸出端子之輪出電單之1 升旁路差動放大電路而傳達至輪出電晶體。"·之上 1269136 、左因此，能抑制起因於差動放大電路之動作遲延（因無法 追隨輪出電壓之上升所致）的過衝發生。 w 1為解決上述問題，本發明之帛2特徵在於，該降低阻 才几用電路係電容器。 、依本發明之第2特徵，降低阻抗用電路能以電容器來 :成’因輸出端子及電流鏡電路之連接點間的阻抗高，故 能使此電容器之電容為充分小。 “因低電容之電容器成本低且小$，故不僅能抑制過 衝，且能降低穩定化電源電路之成本及大小。 為解決上述問題，本發明之第3特徵在於·· ^千^弟1及第2差動對電晶體，係各射極共通連接之pNp 型電晶體，其係將該基準電壓供應於該第丨差動對電晶體 之基將該檢測„供應於該第2差動對電晶體之基極； 必％机鏡电路之第3電晶體係NpN型電晶體，其具有 契及弟1差動對電晶體之集極連接之集極、連接於接地端 子之射極、及連接於該連接點之基極，並將該基極及集極 共通連接； 邊電流鏡電路之第4電晶體，係NpN型電晶體，其具 有與該第2差動對電晶體之集極連接之集極、連接於接地 端子之射極、及連接於該連接點之基極，並將該基極及集 極共通連接； 該輸出電晶體，係、PNP型電晶體，其具有連接於該連 接點之基極、連接於接地端子之集極、及連接於該驅動電 路之射極。 1269136 依本發明之第3特徵，因藉由連接於輸出端子與及差 7放大電路之電流鏡電路之連接點間的降低阻抗用電路， 彳連接點之交流阻抗降低，故能使輸出端子之輸出電屢之 上升方路差動放大電路而傳達至輸出電晶體。 因此’能抑制起因於差動放大電路之動作遲延(因盈法 追隨輸出電壓之上升所致）的過衝發生。 為解決上述問題，本發明之第4特徵在於： 該第1及第2差動對電晶體，係共通連接各源極之p 通，場效電晶體’用以將該基準電壓供應於該第！差動對 電晶體之閘極，將該檢測電壓供應於該第2差動對電晶體 之閘極； 該電流鏡電路之第3電晶體’係N通道場效電晶體， 其具有與該第1差動對電晶體之汲極連接之汲極、連接於 接地端子之源極、及連接於該連接點之閉極，並將該閉極 及汲極共通連接； 甘該電流鏡電路之第4電晶體，係N通道場效電晶體， 八具有與該第2差動對電晶體之汲極連接之沒極、連接於 接地端子之源極、及連接於該連接點之閘極，並將該閘極 及汲極共通連接； 4輪出電晶體，係、P通道場效電晶體，其具有連接於 該連接點之閘極、連接於接地端子之沒極、及連接於該驅 動電路之源極。 依本發明之第4特徵，因藉由連接於輸出端子與差動 放大電路之電流鏡電路之連接點間的降低阻抗用電路，使 11 I269l36 連接點之交流阻抗降低，故能使從輸出 上升旁路差動放大電路而傳達至輸出電 令而子之輸出電壓 晶體。 之 因此，能抑制起因於差動放大電路 追隨輸出電壓之上升所致）的過衝發生 【實施方式】 之動作遲延（因無 法 之％定化電源電路。 電源電路1之概略構 參照附圖說明本發明之實施形態 圖1 ’係表示本實施形態之穩定化 成的方塊圖。 :電壓輸出電路 1 6、定電流電路 10 18 如圖1所示，穩定化電源電路1，具備 分塵電路1 2、驅動電路1 4、預調整器 及差動放大電路（運算放大器）2〇。 電壓輸出電路10，係按照驅動電路14之驅動控制而動 ，從電源電壓Vin(從輸入端子IN供應）產生穩定之輸出 壓Vout，將所產生之輸出電壓v〇ut從輸出端子〇υτ輸出。 作 電 •即，電壓輸出電路10，具備：ΝΡΝ型雙載子電晶體 (bipolar transist〇r)(以下，簡稱電晶體）qi，係將集極 連接於具有輸入端子IN之電源線DL1、，將射極連接於輸 出端子OUT之主動負載元件；PNP型雙載子電晶體（以下， 間稱電晶體）Q2,係與此電晶體Q1形成達林頓（Darl ingt〇n) 連接之主動負載元件的PNP型雙載子電晶體，即，分別具 有與電源線DL1及電晶體Q1之集極分別連接之射極、以及 與電晶體Q1之基極連接之集極。 又’電壓輸出電路1 〇具備電阻R1，設置於將電晶體 Q1之射極與輸出端子〇υτ間、及電晶體Q1之基極與電晶體 12 1269136 Q2之集極間的連接點分別連接之線。 为壓电路12，由在輸出端子〇υτ及接地端子g·間彼 此串聯之電阻R2及R3構成。 驅動電路14，具備：NPN型電晶體q3，連接於電壓輸 出迅路1 0之電晶體Q2之基極與接地端子GND間；NpN型電 曰曰體Q4，與電晶體Q3形成達林頓連接，即，將射極連接於 電晶體Q3之基極；電晶體q4之集極連接於電源線Du。 又，驅動電路14具備電阻，插入於電晶體之集 極及連接電晶體Q2之基極與電晶體Q3之集極的線之間。 預調整器16，連接於電源線DL1與接地端子GN])間， 其係用以將一定之基準電壓Vref供應於差動放大電路2〇 之電路。 定電流電路18,具備第！及第2定電流供應部…及 18b刀別連接於電源線DLi與差動放大電路20及驅動電 路1 4之間。 又，差動放大電路20具備差電壓產生部21，用以產生 檢測電壓Vdet(藉由分壓電路12檢測）與基準電壓Vref(從 預調整器16供應）之差電壓。 。此差電壓產生部21具備PNP型電晶體Q8及Q9(共射 2) ’其構成將各射極共通連接於第i定電流供應部之 疋私流輸出側的差動對電晶體。 差動對琶曰曰體之一電晶體Q8之基極連接於分麼電 電阻R2及R3之連接點N1，藉由分壓電路12所檢 測之檢測電麼Vdet{=v〇utxR3AmR3)^供應至電晶體 13 1269136 之基極。 差動對電晶體之另一雷曰雜 逼日日體Q9之基極連接於預調整器 1 6，從此預調整器1 6所徂座 斤仏應之基準電壓yref則供應至電 晶體Q9之基極。 又’差動放大電路20具傷電流鏡（eurrent ffiirror)電 路22,其構成差動對電晶體⑽、Q9之主動負载（active 1aod) ° 此電流反射器電路22，且供· mdm , ”備· NpN型電晶體Q6，具有 與差動對電晶體Q8、Qg之檢 + 抑之彳欢測電壓側電晶體Q8之集極 連接點N 2連接的集極，及遠接 及連接於接地端子GND之射極；及 晶體Q7，具有盘差動斟+ ^ ^ /、差動對电晶體之基準電壓側電晶 體Q9之集極連接的集極， 千R 及逑接於接地端子GND之射極； 电日日體Q7之基極及集極透過電阻R6連接。 電晶體Q7之集極透過電阻以在連接關連接於電晶 :::極，電晶體⑽之基極透過電容器 體Q6及Q8之連接點N2。 再者，差動放大電路20具備PNP刑 Q5，复且女* 八1有PNP型差動輸出電晶體BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a "stabilized power supply circuit" for stabilizing a DC power supply used for electronic circuit components such as a PC (Personal Computer) board. [Prior Art] 'In recent years, when designing a DC power supply for electronic circuit components such as PC boards, the power supply circuit is stabilized, and the space saving and low cost of the circuit itself are taken out, in order to avoid stabilizing the power supply circuit. All the malfunctions or damages of the parts caused by the power supply noise have been made to suppress the power supply noise as much as possible. In particular, for power supply noise, suppression of overshoot during power-on (starting) is required, and a stabilized power supply circuit capable of suppressing this overshoot is under development. Fig. 3 is a view showing a configuration of a conventional stabilized power supply circuit disclosed in Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. 1 61 758. In the stabilized power supply circuit shown in FIG. 3, the P-channel FET Qn of the current amplifying circuit 101 of (10) is turned on by the driving voltage (received from the power input through the transmission line = VDD (supply voltage VDD)). The output voltage is output to the output terminal 105, and the output voltage νουτ is taken as the connection point N of the series circuit (dividing circuit) composed of the resistors R11 and R1 3 of the current booster circuit 101. The voltage is detected as 'this detection voltage Vdet, and is fed back to the differential amplifier circuit 1〇7 for the differential operation (differential pair) of the pET FETs in the P channels FETs Q13 and Q15 to form a differential The differential pair of amplifier circuit 107 has a negative 1269136 for FETQ13 and Q15, and is used as the N-channel FET Q17 of the current mirror circuit formed by Q19 〇 current mirror connection and the other p-channel of the differential amplifier circuit 1〇7 on the other hand. The gate of FETQ13 applies a reference voltage Vr by a constant voltage source 1 〇9. 1 drive If the reference voltage Vr > detects the voltage vdet, the gate voltage of the N-channel FET Q21 increases. In this case, since the source side of the FETQ21 is grounded, the drain side is connected to the = gate, and the transmission resistor R15 is connected to the power supply line VDD, when the ? 21 is completely turned on, the gate of the FET Q11 is substantially at the ground potential. As a result, the FET Q11 becomes 0N, and the output voltage of the output terminal 1〇5 is increased, and the detection voltage Vdet divided by the voltage dividing circuit also rises. On the other hand, when the detection voltage Vr is detected by detecting the rise of the voltage core, the detection voltage Vdet is detected, and the gate voltage of the n-channel fetq2 ^ for driving the FET Q1! is decreased to become 〇FF. At this time, the FETQ21 and the FETQ11 are connected as described above, and when the FET Q21 is completely turned to 0FF, the gate of the FETQU is substantially the power supply voltage VDD', and the FET Q11 becomes 〇FF and the output terminal ι〇5 is turned out. The voltage Vout is reduced, and the detection voltage "Μ 2 is reduced by the voltage dividing circuit. As described above, the wheel voltage is stabilized in such a manner that the voltage Vdet generated at the connection point N coincides with the reference voltage. When the power supply voltage of the stabilized power supply circuit configured as described above is input, the reference power M Vi- is determined. In contrast, since the output voltage _ is 0 V, the detection voltage Vdet is also 〇v, so that the FET Q21 and the FET QH are respectively 1269136, so that the FET Q21 and the FET QH become (10), respectively. The output voltage v〇ut rises abruptly. At this time, the differential amplifier circuit i07 cannot follow the abrupt change of the above-described round-trip power (10), and even if the output dust Vout reaches the reference battery Vr, the FET Q21 cannot be quickly turned off, so that the The output voltage v〇ut is overshoot. At this point, in the stabilized power supply circuit shown in Figure 3, at the output point of the dust separation circuit (connection point N) (the differential pair connected to the differential amplifier circuit 107 (FETQ13) And Qi5) detection The gate of the FET Q15 on the voltage side is connected in parallel with the resistance of the voltage dividing circuit between the wheel terminal 1〇5 (or the ground terminal GND) = the capacitor cu, and the capacitor C11 changes the output voltage v〇ut. The operation of the first dynamic amplifier circuit 107 (the operation of the differential pair FET Q13 and the operation of 5) is increased, and the ON/OFF frequency of the FET Q21 is increased to suppress the occurrence of the overshoot. However, the above-described stabilization is achieved. The power supply circuit and the overshoot during power-on startup are time constants determined by the resistance value of the resistor Ri (based on the voltage divider circuit (set to R11) and the capacitance of the capacitor C11 (set to cu) (R11) Therefore, in order to suppress overshoot more effectively, it is necessary to increase the time constant _ M1C11, and in the case where the resistance value of the resistor R11 of the voltage dividing circuit is small, it is necessary to use, for example, an aluminum electrolytic capacitor when inserting the capacitor. Capacitors with large capacitances. Such capacitors with large capacitances are expensive, so the cost of the stabilized power supply circuit cannot be reduced. As a result, the cost of electronic circuit components such as Pc boards in which a stabilized power supply circuit is assembled is increased. In addition, the capacitors of large capacitances such as aluminum electrolytic capacitors have a large size, and 1269136, therefore, stabilizes the lightning. As a result, the size of the large-sized electronic circuit components in the size of the circuit (Ic is 1C itself) == The invention relates to a PC board for stabilizing a power supply circuit, etc. [SUMMARY OF THE INVENTION] The present invention has a shape and/or a size of a month. The purpose of the present invention is to provide: the stability of overshoot can be suppressed without being made. & 2 ^ g In order to solve the above-mentioned eg path, the present invention provides: 1 stabilized power supply voltage output circuit of the first feature of the present invention, and the supplied power supply voltage is controlled to be stabilized by φ thousand by an active load element. The main field of the stalk field is loaded with 笔, the pen pressure is output, and the output is output from the output terminal. The differential amplifier circuit is used to generate the 彳1 private mountain and the second differential pair transistor, which is detected by the voltage of ^ Λ Μ The voltage difference between the detection voltage and the reference power #; the current mirror is defeated - the circuit between the person and the earth, and the 匕3 is not connected to the first and second non-adhesive pair transistors and through the connection point spines , the differential, the reverse point is electrically connected by the current mirror Body; and output lightning a, ± and brother 4 铷 power 曰曰 body, used to output the differential amplification signal according to the electrical position of the active sump of the current mirror circuit and the driver's heart; The display of the differential amplification signal outputted by the display of the differential amplification signal to the main component and the connection circuit of the dynamic load reduction impedance is connected between the connection points of the output terminal to make the connection point The AC impedance is reduced. According to the invention, the "amplifier" is reduced by (four) path difference 2 between the connection points of the current mirror circuit connected to the amplifier circuit, and the AC impedance of the connection point is lowered. The 1 liter bypass differential amplifier circuit of the wheel output is transmitted to the wheel-out transistor. "·1269136, left, therefore, can suppress the occurrence of overshoot due to the delay of the operation of the differential amplifier circuit (due to the inability to follow the rise of the wheel-out voltage). In order to solve the above problems, the second aspect of the present invention is characterized in that the circuit breaker is used for the circuit breaker. According to the second aspect of the present invention, the circuit for reducing impedance can be made of a capacitor: since the impedance between the connection point of the output terminal and the current mirror circuit is high, the capacitance of the capacitor can be sufficiently small. "The capacitor of low capacitance is low in cost and small, so it can not only suppress overshoot, but also reduce the cost and size of the stabilized power supply circuit. To solve the above problem, the third feature of the present invention is that ... And the second differential pair transistor is a pNp type transistor in which the emitters are commonly connected, and the reference voltage is supplied to the base of the second differential pair transistor, and the detection is supplied to the second differential The base of the transistor; the third crystal system NpN type transistor of the % mirror circuit, which has the collector of the differential connection of the transistor 1 and the emitter connected to the ground terminal, And a base connected to the connection point, and the base and the collector are connected in common; the fourth transistor of the edge current mirror circuit is an NpN type transistor having a set of the second differential pair of transistors a collector connected to the pole, an emitter connected to the ground terminal, and a base connected to the connection point, and commonly connecting the base and the collector; the output transistor, the PNP type transistor, having the connection a base at the connection point, a collector connected to the ground terminal, and connected to the Electrokinetic shot way to the extreme. According to a third feature of the present invention, since the impedance reducing circuit is connected between the connection point of the current mirror circuit connected to the output terminal and the difference amplifier circuit, the AC impedance of the connection point is lowered, so that the output terminal can be The output power is repeatedly transmitted to the output transistor by the rising square differential amplifier circuit. Therefore, the occurrence of overshoot due to the delay of the operation of the differential amplifier circuit (which is caused by the rise of the output voltage due to the gain method) can be suppressed. In order to solve the above problems, a fourth feature of the present invention resides in that the first and second differential pair transistors are commonly connected to p-channels of respective sources, and the field effect transistor ' is used to supply the reference voltage to the first ! Differentially applying to the gate of the transistor, supplying the detection voltage to the gate of the second differential pair transistor; the third transistor of the current mirror circuit is an N-channel field effect transistor having a differential pole connected to the drain of the transistor, a source connected to the ground terminal, and a closed pole connected to the connection point, and the closed pole and the drain are connected in common; 4 transistor, an N-channel field effect transistor, VIII having a gate connected to the drain of the second differential pair transistor, a source connected to the ground terminal, and a gate connected to the connection point, and The gate and the drain are connected in common; the 4-wheel output transistor, the P-channel field effect transistor has a gate connected to the connection point, a pole connected to the ground terminal, and is connected to the driving circuit The source. According to the fourth aspect of the present invention, the impedance reduction circuit is connected between the output terminal and the connection point of the current mirror circuit of the differential amplifier circuit, so that the AC impedance of the connection point of the 11 I269l36 is lowered, so that the output can be increased. Bypassing the differential amplifier circuit and transmitting it to the output voltage crystal of the output. Therefore, it is possible to suppress an overshoot occurring due to an increase in the output voltage of the differential amplifier circuit. [Embodiment] The operation delay is delayed (the power supply circuit cannot be fixed by %. The schematic configuration of the power supply circuit 1 will be described with reference to the drawings. Fig. 1 is a block diagram showing the stabilization of the present embodiment. The voltage output circuit 16 and the constant current circuit 10 18 are as shown in Fig. 1. The stabilized power supply circuit 1 is provided with a dust separation circuit 1 2 The drive circuit 14 , the pre-regulator, and the differential amplifier circuit (operational amplifier) 2 . The voltage output circuit 10 is driven by the drive control of the drive circuit 14 and is stabilized from the power supply voltage Vin (supply from the input terminal IN). The output voltage Vout is output from the output terminal 〇υτ. The power output circuit 10 includes a bipolar transistor (hereinafter referred to as a bipolar transist 〇r). The transistor qi is an active load device that connects the collector to the power supply line DL1 having the input terminal IN and the emitter to the output terminal OUT; the PNP type double carrier transistor ( B2, which is a PNP type bipolar transistor that forms an active load element connected to the Darlington (Darl ingt〇n), which has a power line DL1 and a transistor, respectively. The emitter of Q1 is connected to the emitter and the collector connected to the base of the transistor Q1. The voltage output circuit 1 has a resistor R1 disposed between the emitter of the transistor Q1 and the output terminal 〇υτ. And a line connecting the base of the transistor Q1 and the collector of the transistor 12 1269136 Q2 respectively. The voltage circuit 12 is composed of resistors R2 and R3 connected in series with each other between the output terminal 〇υτ and the ground terminal g·. The driving circuit 14 is provided with an NPN type transistor q3 connected between the base of the transistor Q2 of the voltage output circuit 10 and the ground terminal GND; the NpN type electric body Q4 forms a Darlington with the transistor Q3. Connecting, that is, connecting the emitter to the base of the transistor Q3; the collector of the transistor q4 is connected to the power line Du. Further, the driving circuit 14 is provided with a resistor, inserted in the collector of the transistor and connected to the base of the transistor Q2. Between the pole and the line of the collector of transistor Q3. Pre-regulator 16, It is connected between the power line DL1 and the ground terminal GN]) for supplying a certain reference voltage Vref to the circuit of the differential amplifier circuit 2A. Constant current circuit 18, with the first! The second constant current supply unit ... and 18b are connected between the power supply line DLi and the differential amplifier circuit 20 and the drive circuit 14 . Further, the differential amplifier circuit 20 includes a difference voltage generating portion 21 for generating a difference voltage between the detection voltage Vdet (detected by the voltage dividing circuit 12) and the reference voltage Vref (supplied from the pre-regulator 16). . The difference voltage generating unit 21 includes PNP type transistors Q8 and Q9 (common beam 2)', and constitutes a differential pair transistor in which the respective emitters are connected in common to the chiral current output side of the i-th constant current supply unit. The base of the transistor Q8 of the differential pair is connected to the junction point N1 of the resistors R2 and R3, and the detection voltage detected by the voltage dividing circuit 12 is Vdet{=v〇utxR3AmR3)^ Supply to the base of the transistor 13 1269136. The base of the differential pair of the transistor is connected to the pre-regulator 1 6 , and the reference voltage yref of the pre-regulator 16 is supplied to the transistor Q9. Base. Further, the 'differential amplifying circuit 20 has an urrent mirror circuit 22 which constitutes an active pair of active pair transistors (10) and Q9 (the active current circuit 22, and is supplied with mdm, ” · NpN type transistor Q6 has the collector connected to the differential pair transistor Q8, Qg + and the collector connection point N 2 of the voltage side transistor Q8, and the remote connection and the ground terminal The emitter of GND; and the crystal Q7, having the disc differential 斟 + ^ ^ /, the collector connected to the collector of the reference voltage side transistor Q9 of the differential transistor, the thousand R and the 逑 connected to the ground terminal GND The base and collector of the electric Japanese body Q7 are connected through a resistor R6. The collector of the transistor Q7 is transmitted through a resistor to be connected to the electro-crystal::: pole, the base of the transistor (10) is transmitted through the capacitor body Q6 and The connection point of Q8 is N2. Furthermore, the differential amplifier circuit 20 has a PNP penalty Q5, and the female* 八1 has a PNP-type differential output transistor.
其具有連接於連接點N2之基極，連 之隼托 4 遷接於接地端子GND 市極’及連接於定電流電路 之輪屮彳日I 您罘2疋電流供應部18b 側之射極，將差動對電晶體Q8及 作各電晶騁夕隹4兩a ^ 、 Q9之差毛壓，當 之電日日驊… m咸輪出；驅動電路14 9豆Q4之基極，連接於第2定電流供雁卹]斗 輪出電曰_ n 、心邛1 8b及差動 a日日體Q5間之中途之連接點N4。 並且，本實施形態之穩定化電源電路卜具備連接於其 14 1269136 輪出端子out及雷曰 a ^ 日日體Q6之基極間的電容器C2，當作降低 I且抗用電路3〇，在輪 一 出兩曰舰 在輸出埏子〇叮與電流鏡電路22之差動輪 =-Q5側之電晶體⑽之基極間透過連接點㈣連接， =輸㈣子術及電晶體⑽之基極間μ流阻抗。 °兒明本貫施形態之穩定化電源電路1之全體動 士兒巧對⑴通常動作冑，⑵電源電壓投人時分別加以 5兄明。 (1)通常動作時 :入i而子IN所供應之電源電壓"η，藉由電壓輸出· 帝〇之電晶體Q1降低電壓後，當作.輸出電壓Vout輸出。 / 2將所輸出之輸出電壓Vout分壓並加以檢測， 夺檢測之檢測電壓Vdet供應至差動放大電路2g之電晶體. ⑽之基極。 另方面，在構成差動放大電路20之差動對之電晶體 ，從定電流電路18之第1定電流供應部18a供應 疋电/;,L 11，疋電流11，透過電晶體Q8及Q9，進一步透過 電晶體Q6及q7流通。 籲 曰此柃，因電晶體Q6及们構成電流鏡電路22，通過電 :體Q6#之集極電力icl與通過電晶體Q7之集極電流ic2 帝j相等故若分別供應至差動對電晶體Qg及q8之基準 電壓Vref與檢測電壓Vdet係相等之情形1包含分別通 過差動對電晶體Q9及Q8之集極電& Ic3及IC4在内之全 部之集極電流Icl〜Ic4則成為相等。 在此，若輸出電壓Vout降低，使檢測電壓Vdet比基 15 1269136 l L化以小之情形（基準電壓Vref >檢測電壓Vdet)， 電晶體⑽之集極電流Ic3則增大，而 流1c4則減少，因雷流鏡雷踗99 ^ 因^爪鏡电路22之兩集極電流Icl及ic2 :別流通同量之電流，故電晶體⑽之集極電流所增加之分 Μ充電於電容器C1 ’差動輪出電晶體Q5之基極電位上 升而差動輸出電晶體Q 5之射極電流減少。It has a base connected to the connection point N2, and the connection 4 is connected to the ground terminal GND and the emitter of the current supply circuit is connected to the ferrule of the constant current circuit. The difference between the differential pair of transistor Q8 and each of the electro-crystals 骋 隹 4 4 a ^, Q9, the difference between the hair pressure, when the electricity day is ... m salty round; drive circuit 14 9 beans Q4 base, connected to The second constant current for the geese shirt] bucket wheel power 曰 _ n, heart 邛 1 8b and the difference between the Japanese and Japanese Q5 connection point N4. Further, the stabilized power supply circuit of the present embodiment includes a capacitor C2 connected between the 14 1269136 turn-out terminal out and the base of the Thunder a ^ Japanese body Q6, and is used as the lowering I and the anti-use circuit 3〇. The two ships are connected by the connection point (4) between the base of the output transistor 12 and the differential mirror of the current mirror circuit 22 on the differential wheel =-Q5 side, and the base of the transistor (4) and the base of the transistor (10). Inter-μ flow impedance. ° 儿 明 本 贯 形态 形态 形态 形态 形态 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定 稳定(1) During normal operation: The power supply voltage "η supplied by i and sub-IN is output as the output voltage Vout by the voltage output of the transistor Q1 of the emperor. / 2 The output voltage Vout is divided and detected, and the detected detection voltage Vdet is supplied to the base of the transistor (10) of the differential amplifier circuit 2g. On the other hand, in the transistor constituting the differential pair of the differential amplifier circuit 20, the first constant current supply portion 18a of the constant current circuit 18 supplies the electric current /;, L 11, the current 11 is transmitted through the transistors Q8 and Q9. It is further circulated through the transistors Q6 and q7.曰 曰 柃 柃 因 因 因 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电In the case where the reference voltage Vref of the crystals Qg and q8 is equal to the detection voltage Vdet, all of the collector currents Icl to Ic4 including the collectors of the transistors Q9 and Q8, respectively, Ic3 and IC4 are obtained. equal. Here, if the output voltage Vout is lowered and the detection voltage Vdet is made smaller than the base 15 1269136 L (reference voltage Vref > detection voltage Vdet), the collector current Ic3 of the transistor (10) is increased, and the flow 1c4 is increased. Then, due to the Thunderbolt Thunder 99 ^ due to the two collector currents Icl and ic2 of the claw mirror circuit 22: the same amount of current flows, so the collector current of the transistor (10) is increased and the charge is charged to the capacitor C1. The base potential of the differential wheel output transistor Q5 rises and the emitter current of the differential output transistor Q 5 decreases.
口差動輸出電晶體Q5之射極電流減少，故從第2定電 ^供應部18b所供應之定電流12透過連接點^流入驅動 i路14之電晶體Q4之基極的電流則增大，而使電晶體^ 之射極電流增大，其結果，使電晶體Q3之射極電流，即， 增大電晶體q2及Q3控制用之控制信號。 藉由私晶體Q3之射極電流增大，從電壓輸出電路i 〇 之$晶體Q2之基極吸引至電晶體⑽之基極電流則增大， ”，果因包曰曰體Q1之射極電流會增大，故輸出電壓v〇ut 則增加。 、另方面，輸出電壓v〇ut增加，使檢測電壓vdei：比 基準電壓Vref A之情形（基準電壓Vref <檢測電壓·Since the emitter current of the differential output transistor Q5 is reduced, the current supplied from the constant current 12 supplied from the second constant power supply portion 18b to the base of the transistor Q4 that drives the i-channel 14 through the connection point is increased. The emitter current of the transistor ^ is increased, and as a result, the emitter current of the transistor Q3, that is, the control signal for controlling the transistors q2 and Q3 is increased. By increasing the emitter current of the private crystal Q3, the base current drawn from the base of the crystal Q2 of the voltage output circuit i 至 to the transistor (10) increases, ", because of the emitter of the package Q1 The current will increase, so the output voltage v〇ut increases. On the other hand, the output voltage v〇ut increases, so that the detection voltage vdei: is higher than the reference voltage Vref A (reference voltage Vref < detection voltage·
Vdet)电日日體Q9之集極電流Ic4增大而電晶體Q8之集極 电 3減〉、，因電流鏡電路22之兩集極電流I c 1及I c2 /刀別*通同置之電流，故電晶體Q8之集極電流IC3減少之 分量，則被差動輪出電晶體Q5之基極吸引，致差動輸出電 晶體Q5之射極電流增大。 口差動輸出電晶體Q5之射極電流增大，故從定電流 (乂弟2笔〃IL供應部18 b供應）透過連接點N 4流至驅動電 16 1269136 路1 4之電晶體Q4之基極之電流則減少，分別使驅動電路 1 4之包晶體Q4之射極電流及電晶體q3之射極電流（控制信 號）減少。 藉由電晶體Q3之射極電流減少，從電壓輸出電路j 〇 之電晶體Q2之基極向電晶體Q3吸引之基極電流則減少， °果因电晶體Qi之射極電流減少，故輸出電壓v〇ut 則降低。 θ如上述，以分壓電路12所檢測之電壓Vdet與基準電 [Vref —致之方式使輪出電壓穩定化。 (2)電源電壓投入時 曰在穩定化電源電路i之電源電麼Vin投入時，基準電 j kef (從預調整器16供應至差動對電晶豸叩之基極）係 ^二相對於此，輸出電厂堅⑽係、0V，因此檢測電壓 e (猎由分壓電路12檢測而供應至 極）亦成為0V。 Μ』糾<基 輸出Ξ: V』輸出電路1〇之電晶體收及Q1分別變成0N 輸出電壓Vout則急劇上升。 此時，在本實施形態之構成， 晶…基極(連接於差動放大電路在2=厂堅一 的差動輸出電晶體Q5之基極)之間連二之電流鏡電路2: 低阻抗用電路30,故輸出電壓 之阻抗則交流地降低。 /…曰體Q6之基極間 因此，瞬間電流（依據輸出端子〇υτ -之急劇上升）則將分麼電路12 =輪出電壓Vou· 冲間流入電晶體Q6之 1269136 基極’使電晶體Q6之集極電流Iel瞬間增大。 此時，由於來自讓1φ& 弟1疋電々丨L供應部18 a之定電流11係 :定’故電晶體Q8之集極電流Ic3則減少，其結果，從電 晶體Q5之基極吸引電流而使差動輸出電晶體Q5 0N，驅動 电路14之电晶體Q4及q3分別維持〇FF狀態。 因電晶體Q3維持〇FF狀態，故電壓輸出電路ι〇之輸 出電壓電晶體⑽及Q1亦維持_狀態，其結果，即使電Vdet) The collector current Ic4 of the electric Japanese body Q9 increases and the collector current of the transistor Q8 decreases by 3, because the two collector currents I c 1 and I c2 of the current mirror circuit 22 are co-located The current is reduced, so that the component of the collector current IC3 of the transistor Q8 is reduced, and the base of the differential wheel output transistor Q5 is attracted, so that the emitter current of the differential output transistor Q5 is increased. The emitter current of the differential output transistor Q5 is increased, so that the constant current (supplied from the 2IL 2 supply unit 18b) flows through the connection point N4 to the transistor Q4 of the driving circuit 16 1269136. The base current is reduced to reduce the emitter current of the package crystal Q4 of the drive circuit 14 and the emitter current (control signal) of the transistor q3, respectively. By reducing the emitter current of the transistor Q3, the base current drawn from the base of the transistor Q2 of the voltage output circuit j to the transistor Q3 is reduced, and the emitter current of the transistor Qi is reduced, so the output is reduced. The voltage v〇ut is lowered. As described above, the voltage Vdet detected by the voltage dividing circuit 12 and the reference power [Vref are stabilized in a manner such that the wheeling voltage is stabilized. (2) When the power supply voltage is input, when the power supply of the stabilized power supply circuit i is supplied with Vin, the reference electric power j kef (supply from the pre-regulator 16 to the base of the differential-to-electrical crystal) is relative to In this case, the output power plant (10) system and 0 V are output, so that the detection voltage e (hunted by the voltage dividing circuit 12 and supplied to the pole) also becomes 0V. Μ 纠 纠 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基 基At this time, in the configuration of the present embodiment, the base of the crystal (connected to the differential amplifier circuit at the base of the differential output transistor Q5 of the factory = 2) is connected to the current mirror circuit 2: low impedance With the circuit 30, the impedance of the output voltage is reduced AC. /... The base of the body Q6, therefore, the instantaneous current (according to the sharp rise of the output terminal 〇υτ -) will be divided into circuit 12 = wheel voltage Vou · rush into the transistor Q6 1269136 base 'to make the crystal The collector current Iel of Q6 increases instantaneously. At this time, since the constant current 11 from the 1 φ & 1 疋 供应 L supply unit 18 a is fixed, the collector current Ic3 of the transistor Q8 is decreased, and as a result, the current is drawn from the base of the transistor Q5. With the differential output transistor Q5 0N, the transistors Q4 and q3 of the drive circuit 14 are maintained in the 〇FF state, respectively. Since the transistor Q3 maintains the 〇FF state, the output voltage transistors (10) and Q1 of the voltage output circuit ι are also maintained in the _ state, and as a result, even if the electricity
源電壓上升時，輪出+歐V 斤了铷出私壓V〇ut之上升仍按照上 之電容之時間常數遲延。 谷的C2籲 藉由輸出電壓Vout之上升遲延，能吸收對輸出電壓When the source voltage rises, the turn-off + ohms and volts of the private voltage V〇ut rises and is delayed according to the time constant of the upper capacitor. Valley C2 calls the output voltage by absorbing the delay of the output voltage Vout
Vout之上升的差動放大電路2〇之動作遲延，其結果，能抑 制按照差動放大電路2〇之動作遲延的過衝（請⑽。⑷之-發生。 另-方面’若輸出電壓v〇ut下降之情形，因電晶體卯 之基極射極間之電荷瞬間透過電容器C2釋出，故使電晶體 Q 6之集極電流I c 1瞬間減少。 此時，目來自第1定電流供應部18a之定電流n係—籲 定，故電晶體Q8之集極電流Ic3則增大，其結果，對電晶 體Q5之基極供應電流而使差動輸出電晶體卯〇FF，驅動電 路14之電晶體Q4及Q3分別變為〇N狀態。 因電晶體Q3分別變為on狀態，故電壓輸出電路丨〇之 輸出電壓電晶體Q2及Q1則分別變為⑽狀態，其結果，不 會文到差動放大電路20之差動對電晶體⑽及⑽之動作的 影響，而能使輸出電壓Vout瞬間增大。 18 1269136 其結果’亦能抑制按照差動放大電路2〇之動作遲延的 過低（undershoot)之發生。 又’在本實施形態，因輸出端子OUT及差動放大電路 2 0之黾a曰體Q 6之基極間之阻抗充分大，故能使電容器c 2 之電谷為非常小，而能將例如陶瓷電容器等之小型、低成 本之電容器當作電容器C2來使用。 因此，不僅能抑制過衝及過低，亦能減低穩定化電源 笔路1之成本，進而，能獲得組裝有此穩定化電源電路1 之PC板等電子電路零件内之省空間化。 又，在本實施形態，差動放大電路20之差動對電晶體 及電流鏡電路用電晶體，雖分別使用PNP型電晶體及_ :電晶體，但本發明並不限定於此構成，差動對電晶體及 電流鏡電路用電晶體，亦能分別使用卿型電晶體及卿 又，差動對電晶體及電流鏡電路用電晶體，亦能 場效電晶體（FET) 〇 bAs a result, the operation of the differential amplifier circuit 2 that is rising in Vout is delayed, and as a result, it is possible to suppress an overshoot that is delayed in accordance with the operation of the differential amplifier circuit 2 (please (10). (4) - occurs. Another aspect - if the output voltage v〇 When ut falls, the charge between the base emitters of the transistor 瞬间 is instantaneously transmitted through the capacitor C2, so that the collector current I c 1 of the transistor Q 6 is instantaneously reduced. At this time, the target is supplied from the first constant current supply. The constant current n of the portion 18a is called, so that the collector current Ic3 of the transistor Q8 is increased. As a result, a current is supplied to the base of the transistor Q5 to make the differential output transistor FF, and the drive circuit 14 The transistors Q4 and Q3 are respectively in the 〇N state. Since the transistors Q3 are turned on, the output voltage transistors Q2 and Q1 of the voltage output circuit 变为 are in the (10) state, respectively. The influence of the differential to the differential amplifier circuit 20 on the operation of the transistors (10) and (10) can increase the output voltage Vout instantaneously. 18 1269136 The result 'can also suppress the delay in the operation of the differential amplifier circuit 2 Low (undershoot) occurs. In the state, since the impedance between the output terminal OUT and the differential amplifier circuit 20 and the base of the body Q 6 is sufficiently large, the electric valley of the capacitor c 2 can be made very small, and for example, a ceramic capacitor or the like can be used. A small, low-cost capacitor is used as the capacitor C2. Therefore, not only the overshoot and the undershoot can be suppressed, but also the cost of stabilizing the power supply stroke 1 can be reduced, and further, the PC equipped with the stabilized power supply circuit 1 can be obtained. Further, in the present embodiment, the differential-optical amplifier circuit 20 uses a PNP-type transistor and a _: transistor for the differential-optical-transistor and the current-mirror circuit. However, the present invention is not limited to this configuration. For the transistor for the differential pair transistor and the current mirror circuit, it is also possible to use the crystal of the crystal type and the crystal for the differential pair transistor and the current mirror circuit, respectively. Field effect transistor (FET) 〇 b
例如’圖2,係表示穩定化電源電路^之概 圖，分別將P通道FETQ8a、Q9a使用為差動對電晶體、 通道FETQ6a、Q7a使用為電流鏡電路22a用電晶^。又/ 具有與圖1大致同等功能之構成要件 曰：又’ 畋甘妨日日。 付就而省 在圖2所示之差動放大電路2〇a，將圖1所示 午 體Q5~Q9分別以FETQ5a〜Q9a取代，且各基極、I之各電 $極X射 $別成為閘極、汲極、源極，除此以外， M逆筏關係同樣 19 1269136 故省略其說明。 士在本文形例之穩定化電源電路1 a之電源電壓Vin投入 時，從預調整器16供應至差動對FETQ9a之閘極之基準電 壓Μ係—定，相對於此，輸出電塵V〇ut係〇v，因此藉 由分壓電路12檢測而供應至差動對F_a之閘極之檢測 電壓Vdet亦成為〇v。 因此，電屡輸出電路10(之電晶體Q2 & Q1)分別成為 〇N ’輸出電壓Vout則急劇上升。 π在本、夂形例之構成，因在輸出端子⑽T與φ 甲1極（連接方；電流鏡電路22a之差動輸出叮刊5&之閘極） 之間連接作為降低阻抗用電路3〇之電容器c2，故輸出端子 OUT與FETQ6a之閘極間之阻抗則交流地降低。 、 口此瞬間電流（依輸出端子OUT之輸出電壓v〇ut之-急劇上升)則將分嫩12旁路而瞬間流入卿&之間 極，使FETQ6a之汲極電流Idl瞬間增大。 此時，因來自第1定電流供應部18a之定電流n係一 ΓρτοΓ FETQ8a ^ ^^ Id2 M，J ^ ^ ^ ^ ^ ^ ^ ^ ^ · &之閑極電壓減少而使差動輸出FETQ5a ON，驅動電 路14(之私晶體q4及分別維持⑽ρ狀態。 因電晶體Q3維持_狀態’故電壓輸出電路ι〇(之輸 出電壓電晶體Q2及⑴亦維持〇FF狀態，其結果，即使電 源電壓上升時，輪出電壓V〇ut之上升仍按照上述電容哭C2 之電容之時間常數遲延。 藉由輸出电壓v〇ut之上升遲延，能吸收對輸出電壓 20 1269136For example, Fig. 2 shows an outline of a stabilized power supply circuit, and P-channel FETs Q8a and Q9a are used as differential-optical transistors, and channel FETs Q6a and Q7a are used as current mirror circuits 22a. Also / constituting elements that have roughly the same functions as those in Figure 曰: ’ 畋 畋 日 日 。. In the differential amplifying circuit 2〇a shown in FIG. 2, the noon bodies Q5 to Q9 shown in FIG. 1 are replaced by FETs Q5 to Q9a, respectively, and the respective bases and Is are charged by the X-rays. In addition to the gate, the drain, and the source, the M-reverse relationship is also 19 1269136, and the description thereof is omitted. When the power supply voltage Vin of the stabilized power supply circuit 1a of the present example is input, the reference voltage supplied from the pre-regulator 16 to the gate of the differential pair FET Q9a is determined, and the electric dust V〇 is output. Since the ut system 〇v, the detection voltage Vdet supplied to the gate of the differential pair F_a by the voltage dividing circuit 12 is also 〇v. Therefore, the electric output circuit 10 (the transistors Q2 & Q1) suddenly rises as the output voltage Vout of 〇N '. The configuration of the π is in the form of the present invention, and is connected between the output terminal (10)T and the φ1 pole (the connection side; the differential output of the current mirror circuit 22a) and the gate of the current mirror circuit 5a. With the capacitor c2, the impedance between the output terminal OUT and the gate of the FET Q6a is reduced AC. At this moment, the current (by the output voltage v〇ut of the output terminal OUT rises sharply) bypasses the minute 12 and instantaneously flows into the junction between the gate and the gate, so that the drain current Id1 of the FET Q6a instantaneously increases. At this time, the differential current from the first constant current supply portion 18a is a constant current output FET Q5a due to a decrease in the idle voltage of the constant current n of a ΓρτοΓ FETQ8a ^ ^^ Id2 M, J ^ ^ ^ ^ ^ ^ ^ ^ ^ & ON, the drive circuit 14 (the private crystal q4 and the (10) ρ state are maintained. Since the transistor Q3 maintains the _ state, the voltage output circuit ι〇 (the output voltage transistors Q2 and (1) also maintain the 〇FF state, and as a result, even the power supply When the voltage rises, the rise of the voltage V〇ut is still delayed according to the time constant of the capacitance of the capacitor C2. The rise of the output voltage v〇ut can absorb the output voltage 20 1269136.
Vout之上升的差動放大電路20a之動作遲延，其結果，能 抑制知：知差動放大電路2 0 a之動作遲延的過衝（〇 v g r s h ο 〇 t) 之發生。 另一方面，若輸出電壓V〇ut下降之情形，因FETQ6a 之閘極源極間之電荷透過電容器C2瞬間釋出，故使FETQ6a 之汲極電流I d 1瞬間減少。 此時，因來自第1定電流供應部1 8a之定電流n係一 疋’故F E T Q 8 a之汲極電流I d 2則增大，其結果，差動輸出 FETQ5a之閘極電壓增大而使差動輸出FETQ5a OFF，驅動電 修 路14(之電晶體Q4及Q3)分別變為ON狀態。 因驅動電路14(電晶體Q3)變為ON狀態，故電壓輸出 甩路1 0(之輸出電壓電晶體Q2及q 1)則分別變為⑽狀態， 其結果，不會受到差動放大電路20a之差動對FETQ8a及Q9a -之動作的影響，而能使輸出電壓V〇ut瞬間增大。 其結果，亦能抑制按照差動放大電路2〇a之動作遲延 的過低（undershoot)之發生。 如上述，在本變形例，亦能使用電容小之電容器c2來 # 抑制過衝及過低的發生，而能獲得與上述實施形態大致同 樣之效果。 本發明，並不限定於上述實施形態及變形例，在本發 明所屬之範圍内，能將上述實施形態及變形例作各種變形 來實施。 【圖式簡單說明】 圖卜係表示本發明之實施形態之穩定化電源電路之概 21 1269136 略構成的方塊圖。 圖2，係表示本實施形態之變形例之穩定化電源電路之 概略構成的方塊圖。 圖3，係表示習知之穩定化電源電路之概略構成的方塊 圖。 【主要元件符號說明】 卜1 a 穩 定 化 電 源電路 10 電 壓 Ψμ 出 電路 12 分 壓 電 路 14 驅 動 電 路 16 預 調 整 器 18 定 電 流 電 路 18a 第 1 定 電 流供應_ 18b 第 2 定 電 流供應· 20、 20a 差製 7放大電路 21 差 電 壓 產 生部 、 22a 電流鏡電路 30 降低 阻抗 用電路 101 電 流增 強 電路 105 輸 出 端 子 107 差 動 放 大 電路 109 定 電 壓 源 Cl、 C2電 容 器 DL1 電 源 線 22 1269136 GND 接地端子 IN 輸入端子 N、Nl、N2、N3、N4 連接點 OUT 輸出端子 Q1-Q9 雙載子電晶體 Q 5 a〜Q 9 a 場效電晶體 R1-R6 電阻 Vdet 檢測電壓 Vref 基準電壓 23The operation of the differential amplifier circuit 20a that rises in Vout is delayed, and as a result, it is possible to suppress the occurrence of overshoot (〇 v g r s h ο 〇 t) of the delay of the operation of the differential amplifier circuit 20 a. On the other hand, when the output voltage V〇ut falls, the charge between the gate and the source of the FET Q6a is instantaneously discharged through the capacitor C2, so that the drain current Id1 of the FET Q6a is instantaneously reduced. At this time, since the constant current n from the first constant current supply unit 18a is one, the gate current Id2 of the FET Q 8a increases, and as a result, the gate voltage of the differential output FET Q5a increases. When the differential output FET Q5a is OFF, the drive electric path 14 (the transistors Q4 and Q3) are turned to the ON state. Since the drive circuit 14 (transistor Q3) is turned on, the voltage output circuit 10 (the output voltage transistors Q2 and q1) is in the state of (10), and as a result, the differential amplifier circuit 20a is not received. The difference affects the operation of the FETs Q8a and Q9a -, and the output voltage V〇ut can be instantaneously increased. As a result, it is also possible to suppress the occurrence of undershoot due to the delay of the operation of the differential amplifier circuit 2a. As described above, in the present modification, it is also possible to suppress the occurrence of overshoot and undershoot using the capacitor c2 having a small capacitance, and it is possible to obtain substantially the same effects as those of the above embodiment. The present invention is not limited to the above-described embodiments and modifications, and various modifications and changes can be made to the above-described embodiments and modifications within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 2b is a block diagram showing a schematic configuration of a stabilized power supply circuit according to an embodiment of the present invention. Fig. 2 is a block diagram showing a schematic configuration of a stabilized power supply circuit according to a modification of the embodiment. Fig. 3 is a block diagram showing a schematic configuration of a conventional stabilized power supply circuit. [Main component symbol description] 1 a Stabilization power supply circuit 10 Voltage Ψ μ Output circuit 12 Voltage dividing circuit 14 Drive circuit 16 Pre-regulator 18 Constant current circuit 18a 1st constant current supply _ 18b 2nd constant current supply · 20, 20a Differential 7 Amplifying Circuit 21 Differential Voltage Generating Unit, 22a Current Mirror Circuit 30 Circuit for Lowering Impedance 101 Current Enhancing Circuit 105 Output Terminal 107 Differential Amplifying Circuit 109 Constant Voltage Source Cl, C2 Capacitor DL1 Power Line 22 1269136 GND Ground Terminal IN Input terminal N, Nl, N2, N3, N4 Connection point OUT Output terminal Q1-Q9 Bipolar transistor Q 5 a~Q 9 a Field effect transistor R1-R6 Resistance Vdet Detection voltage Vref Reference voltage 23
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003434876A JP2005196233A (en) | 2003-12-26 | 2003-12-26 | Stabilizing power circuit |
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| TW200521642A TW200521642A (en) | 2005-07-01 |
| TWI269136B true TWI269136B (en) | 2006-12-21 |
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| JP2006127225A (en) | 2004-10-29 | 2006-05-18 | Torex Device Co Ltd | Power circuit |
| JP5390932B2 (en) * | 2009-05-14 | 2014-01-15 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Power circuit |
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