1264800 i3861twf.doc/m 九、發明說明： 【發明所屬之技術領域】 本發明關於一種半導體元件的製造方法，且特別是有 • 關於一種可改進在玻璃上之矽(silicon-on-glass，SOG)製程 的方法和採用該方法所製造的元件。 【先前技術】 非易失性儲存元件(non_v〇latile mem〇ry device幻已經 被廣泛地用於儲存不需頻繁修正的訊息。這種儲存元件例 如包括唯頃§己憶體(ROM)、可編程唯讀記憶體(pR〇M)、可 擦除可編程唯讀記紐(EPRqM)、電性可擦除可編程唯讀 記憶體(EEPROM)和快閃可擦除可編程唯讀記憶體(flash EEPROM)。 非易失性儲存元件通常可儲存並保持代表訊息的電 荷。例如，EPROM可包括許多浮置閘極儲存單元⑽此吨 gate、memory cell)，每個浮置閘極儲存單元都包括一個電荷 俘獲層（charge trapping layer) ’用來保持代表一個資料的電 • 荷。圖1A繪示為習知形成於半導體基板(substrate)1〇上的 浮置閘極儲存單元1〇〇的結構。儲存單元1〇〇包括形成於 ' 基板10上並互相隔開一段距離的擴散區（diffusion . reglon)102和104’這兩個擴散區102和1〇4之間定義為一 個通道（Channel)l〇6。在通道106上形成第_疋介電層 (dielectric layer)!08，在第一介電層！〇8上形成電荷俘 no,在電荷俘獲層no上形成第二介電層112，並且 二介電層112上形成閘極(gate)114。第一介電層⑽可由 Ϊ264800 13861 twfd〇c/m 穿隨氧化物（tunnel oxide)所据々 氧化石夕或氧化物氣ΓΓ 第二介電層112可由二 所構成。電荷俘蒋声 氮化矽所構成。 日 可由夕晶矽(polysilicon)或 時，i=3(biaS V〇ltage)於間極H4和擴散區102、刚 何就可進人電荷俘獲層⑽而編程儲存單元剛， 或ϋ荷俘獲層11G移出從而擦除儲存單元100。 式的單元100的過程中，包含電洞或電子等形 二夂:了^弟―介電層⑽或第二介電層m，並儲存 可改變用以讀取Li Γ獲層110中的電荷將 VQltaH、，4t、儲存早兀100的閥限電壓（threshold 還是Γ _存於儲存單元1GG中的位it㈣是“〇，， 的全==00從其他元件或後續步驟中所形成 =屬接點以及擴散區102、1〇4隔離開來，則使用層間介 =Γ electric，ILD)116來填充儲存單元⑽和 …的縫隙，其中金屬接點與閘極114接觸。層 間H可作爲—低介電常數材料，其用來將 點與儲存單元_電性隔離。最常見的層間 曰 利用化學氣相沉積（CVD)技術而由硼磷矽酸鹽破； (b⑽-Ph〇sph〇-silicate glass，BPSG)所形成，其中高溫將 助於此種硼磷矽酸鹽玻璃之化學氣相積 _ ' 種選擇方案是採用只需要較低溫度丁式玻另： (spin-on_glass，S0G)技術而形成層間介電質丨丨6。旋塗式玻 1264800 13861twf.doc/m 璃技術是將溶有Si02和摻作 板上並固化《料麵减塗到基 固化過程中，溶劑4::^ "】郇近的層中。例如，在圖1A 中，當採職塗式___ 中的溶劑會擴散到電鮮獲層no中，= 貝告儲予早兀100的效能。爲了阻止溶劑擴散，如圖 所不可以在層間介電質116和儲存單it 1GG之間提供一 個概層（liner layer)l 18。1264800 i3861twf.doc/m IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and particularly to a silicon-on-glass (SOG) improvement The method of the process and the components manufactured by the method. [Prior Art] Non-volatile storage elements (non_v〇latile mem〇ry device illusion have been widely used to store messages that do not need to be frequently corrected. Such storage elements include, for example, only ** memories (ROM), Program-Read Only Memory (pR〇M), Erasable Programmable Read Only (EPRqM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Erasable Programmable Read-Only Memory (flash EEPROM) A non-volatile storage component can typically store and hold a charge representing a message. For example, an EPROM can include a number of floating gate storage units (10), a ton of gate, memory cells, and each floating gate storage unit. Both include a charge trapping layer 'used to hold the charge representing a piece of data. Fig. 1A shows the structure of a floating gate storage unit 1〇〇 which is conventionally formed on a semiconductor substrate. The storage unit 1 includes a diffusion region 102 and 104' formed on the substrate 10 and spaced apart from each other by a distance (dreffusion. reglon) 102 and 104' defined as a channel between the two diffusion regions 102 and 104. 〇 6. A first dielectric layer!08 is formed on the channel 106, in the first dielectric layer! A charge trap no is formed on the germanium 8, a second dielectric layer 112 is formed on the charge trap layer no, and a gate 114 is formed on the second dielectric layer 112. The first dielectric layer (10) may be composed of Ϊ264800 13861 twfd〇c/m, depending on the oxide oxide, oxide oxide or oxide gas, and the second dielectric layer 112 may be composed of two. Charge trapping sound is composed of tantalum nitride. The storage cell, or the charge trapping layer, can be programmed by the polysilicon or the time, i=3 (biaS V〇ltage) at the interpole H4 and the diffusion region 102, and just entering the charge trapping layer (10). The 11G is removed to erase the storage unit 100. In the process of the unit 100, a hole or an electron is formed in the form of a dielectric layer (10) or a second dielectric layer m, and the storage can be changed to read the charge in the Li acquisition layer 110. VQltaH, 4t, store the threshold voltage of 100 ( (threshold or 位 _ stored in the storage unit 1GG bit it (four) is "〇,, all == 00 formed from other components or subsequent steps = 属The dots and the diffusion regions 102, 1〇4 are isolated, and the gap between the storage cells (10) and ... is filled with interlayer dielectrics, IL electric, ILD) 116, wherein the metal contacts are in contact with the gate 114. The interlayer H can be used as low a dielectric constant material used to electrically isolate a point from a storage cell. The most common interlayer enthalpy is destroyed by borophosphonate using chemical vapor deposition (CVD) techniques; (b(10)-Ph〇sph〇-silicate Glass, BPSG), in which high temperature will help the chemical vapor phase of this borophosphonate glass _ 'The choice of the scheme is to use only lower temperature singapore: (spin-on_glass, S0G) technology And the formation of interlayer dielectric 丨丨6. Spin-on glass 1264800 13861twf.doc/m glass technology will be dissolved The SiO2 and the blended board are cured and the "surface is reduced to the base curing process, the solvent 4::^ "] is in the vicinity of the layer. For example, in Figure 1A, when the solvent in the ___ Will diffuse into the electric fresh layer no, = the performance of the slogan to the early 兀 100. In order to prevent solvent diffusion, as shown in the figure can not provide a layer between the interlayer dielectric 116 and the storage unit it 1 GG (liner Layer) l 18.
類似地，在採用被金屬間介電質(inter_metaidide她 IMD)層而互相隔離的多層金屬接點的儲存元件中，此種 IMD層可藉由SOG技術而形成，並且可使用氧化物概層 阻止溶劑擴散於鄰近的層中’而此種擴散將損害儲存單元 的效能。例如’ ® 1B表示在基板2〇2上所形成的儲存元 件200。儲存元件200包括第一金屬接點2〇4和藉由IMD 層208而與第一金屬接點204隔離的第二金屬接點2〇6。 IMD層208可藉由SOG技術而形成。imd層208和第一 金屬接點204之間的襯層210可阻止IMD層208在固化時 其溶劑的擴散。 普通的襯層118或210由二氧化矽(si〇2)所構成，其 可利用SiH4和％0的混合氣體或四乙基正石夕酸鹽 (tetraethylorthosilicate，TEOS)與 〇2 或 〇3 的混合組合等藉 由電漿增强化學氣相沉積（Plasma Enhanced Chemical Vapor Deposition, PECVD)法所形成。但是，採用 si〇2 作 爲氧化物襯層118或210的問題是，由於用來形成10) 116 1264800 13861twf.doc/m 或IMD 208的溶解s〇G的溶劑 以實現ILD116或IMD2〇8的低=有，度的氫， =:擴，由⑽形成的 下面的層，其例如為電荷俘獲層ΐι〇或 =〇而進入 此種風擴散的結果可能會使儲存單元'〇土 4 202等。 失去儲存於其中的電荷並表現出不良=存元件200 類似於儲存單^ 或儲 屬性。 求之標準的比較乃是如圖中里〜果與所要 ^屬性可經由_個讀之 _電壓的變化而反應出來 曼:::子… 100 ^〇〇〇 標準要求之闕限電難不大於 必需在儲存於其中的:凡100或儲存元件200 ，率的增加，電=r;再 存單元100洳Μ左-Μ。 因此，要如何讓儲 電荷是十分重要Γ 盡可能地長時間保存儲存 過臨m等度人的Λ國專利申請號5,805,013提出一旦超 效。Ghneim等^ ^、子便由其鍵結區（b〇nding site)被釋 的製程以及在所^出了藉由在浮㈣極㈣沉積介電層 下mf/有後_製程中將溫度保持在臨界溫度之 擴散二特別向儲存單71的浮置間極(電荷俘獲層） 特別疋在Ghneim等人的發日种，含氫介電層和所 1264800 13861twf.doc/m 有後續介電層/導電厣都B / 〇〇Απ 數情况是在35^下 多 散於:低溫度製程可能會減少氫擴 低的處理^下二層内的縣’然而’經由在此較 糾Γ 1 連㈣程所形成的材料品質較差，使得 :=Γ元的可靠性仍會受到損害。、、 其板本種儲存元件的形成方法，包括提供一個 月b〇H牛上形成昌含石夕(silicon-rich)的介電声。 — 本發明提供—種半導體9 =形成-富含㈣介電層。:4=二= 電層 料塗式麵層，《«富切介 此儲包括基板和儲存單元的半導體元件。 含石夕的介電^在基板上的功能部件和在功能部件上的富 個儲存單亓4 4工 ，一…— 人丄W夕储存 上沾二個位於基板上的功能部件和在 。此半導體元件更包括在富含秒的^ 旱元。每 功能部件 陣列本提供—種半導體7^牛’包括—基板和-儲存- 二中儲存器陣列包括在基板上的多個儲存 上的富含矽的介電層 12648脫一 電貝上的一旋塗式破璃層。 為讓本發明之上述和其他目的、 易懂，下文特舉較佳實二以明顯 優點。 幾見亚獲侍本發明的特徵和 些實 A二上的概述和下面的詳細說明僅為本發明之 細方=、，,用以解釋本發明，而非用以限定本發明。 的於ΐ作為本說明書之—部分的圖式描緣了本發明 優二:二？用來與說明書共同說明本發明的技術特徵、 【實施方式】 所有關對本發明之較佳實_作詳細說明。在 所有=中，相_元件㈣乃是絲相同或難的元件在 ϋ明提供一種新式的非易失性儲存元件 陶技術所形成的位於層間介 ：Similarly, in a storage element using a plurality of metal contacts that are isolated from each other by an inter-metaidide (IMD) layer, such an IMD layer can be formed by SOG technology and can be blocked using an oxide layer. The solvent diffuses into the adjacent layers' and such diffusion will impair the performance of the storage unit. For example, '® 1B denotes a storage element 200 formed on the substrate 2〇2. The storage element 200 includes a first metal contact 2〇4 and a second metal contact 2〇6 isolated from the first metal contact 204 by the IMD layer 208. The IMD layer 208 can be formed by SOG technology. The liner 210 between the imd layer 208 and the first metal contact 204 prevents the IMD layer 208 from diffusing its solvent upon curing. The conventional lining layer 118 or 210 is composed of cerium oxide (si〇2), which can utilize a mixed gas of SiH4 and %0 or tetraethylorthosilicate (TEOS) and 〇2 or 〇3. The mixed combination or the like is formed by a plasma enhanced chemical vapor deposition (PECVD) method. However, the problem with the use of si〇2 as the oxide liner 118 or 210 is due to the solvent used to form 10) 116 1264800 13861twf.doc/m or IMD 208 to dissolve s〇G to achieve a low ILD116 or IMD2〇8 = There is a degree of hydrogen, =: expansion, the underlying layer formed by (10), which is, for example, a charge trapping layer ΐι〇 or =〇, and the result of such wind diffusion may result in a storage unit 'alumina 4 202 and the like. Loss of charge stored therein and exhibits a bad = storage element 200 is similar to a storage unit or storage attribute. The comparison of the standard is as shown in the figure. The fruit and the attribute of the desired ^ can be reflected by the change of the voltage of _ reading. Man:::sub...100 ^〇〇〇The standard requirement is not more than necessary. In the storage: 100 or storage element 200, the rate increases, electricity = r; re-storage unit 100 洳Μ left-Μ. Therefore, how to make the stored charge is very important Γ Save the storage as long as possible. The patent application number 5,805,013 of the person who is equal to the m is proposed to be effective. Ghneim et al ^ ^, the process of the release of the bond from the b〇nding site and the temperature is maintained by the mf / after the process in the floating (four) pole (four) deposited dielectric layer The diffusion at the critical temperature is particularly directed to the floating interpole (charge trapping layer) of the storage unit 71. In particular, the Ghneim et al., the hydrogen-containing dielectric layer and the 1264800 13861 twf.doc/m have subsequent dielectric layers. / Conductive 厣 B / 〇〇Α π number of cases is scattered at 35 ^: low temperature process may reduce the treatment of hydrogen expansion ^ County under the second layer 'however' via here more Γ 1 (4) The quality of the material formed by the process is poor, so that the reliability of the == unit will still be damaged. And a method for forming the storage element of the plate, comprising providing a silicon-rich dielectric sound on a b〇H cattle. - The present invention provides a semiconductor 9 = formed - rich (tetra) dielectric layer. :4=2=Electrical layer The coating type surface layer, ««Fusiejie This storage semiconductor element including substrate and storage unit. The dielectric components on the substrate, the functional components on the substrate, and the rich storage unit on the functional components, one...the human 丄W 储存 storage on the two functional components on the substrate and in. This semiconductor component is further included in the second-rich ^Yu yuan. Each of the functional component arrays provides a semiconductor-in-a-substrate-substrate and-storage-secondary memory array comprising a plurality of storage-rich germanium-rich dielectric layers 12648 on the substrate. Spin-coated glass layer. In order to make the above and other objects of the present invention easy to understand, the following specific description is preferred to advantage. The invention is not limited to the scope of the invention. Yu Yu as a part of the specification of the description of the present invention, the second advantage: two? The technical features of the present invention will be described in conjunction with the specification, and the preferred embodiments of the present invention will be described in detail. In all =, phase_component (4) is the same or difficult component of the wire. In the description, a new type of non-volatile storage component is provided.
=介電卿)層的富含石夕的-襯層，其用來阻止S0G :存:Ϊ的擴散。圖3Α和圖_示爲本發明的非易失 #主^二閱圖3Α,本發明第—實施例的儲存元件300形成 基板％之上並包括形成於半導體基板3〇之= 圖中只不出了—個）°ILD層304形成於基板 盘Λ处广F件302之上，用以提供絕緣功能並填充基板30 =月部件搬和基板3G上的其他^件或功能部件3〇2 之間的縫隙。ILD@ 304可藉由將訓溶液旋塗並將其固 10 1264800 13861 twf.doc/m 和功能部件3〇t电層306形成於仙層304和基板30 ILD層304可以开二’用以阻止S〇G溶液中的氫的擴散。 全部之上。形成於介電襯層的部分（圖中未示）或 300 It ίΓ^3()2可包括任何適合組成非易失性儲存元件 圖3Α所V ::為間極結構或金屬接點。舉例而言，如 能部件搬可以為多層閘極結構，其中 母個^層閘極結構包括：例如，基板％之上的第一介電層 :之弟介電層308之上的電荷俘獲層310、電荷俘“ ^上的的第二介電層312、第二介電層M2之上的間極 3M。弟電層烟和第二介電層312都可包含氧化物， 例如為—乳切。電荷俘獲層310可包括氮切或多晶 石夕間極314可包括金屬。如圖3A所示，儲存元件3〇〇 更可包括形成於基板3 〇内並對應於功能部件3 〇 2之兩側的 擴散區316和318，其中擴散區316和318相隔-段距離 並在其兩者之間定義出一個通道32〇。 本务明的介電襯層306是富含矽的，並可藉由化學氣 相沉積(CVD)技術而形成，以包含一富含石夕的氧化物，其 中，，富切的氧化物中，其㈣子與氧原子的個數比率 乃是咼於在Si〇2中的個數比率。在本發明的一實施例中， 該矽原子與氧原子的個數比率乃是高於丨：丨。如此，介電 襯層306將含有大量的懸掛矽鍵(danglingsiiic〇nb〇nd)。在 後續之形成ILD層304的步驟中，這些懸掛矽鍵將會捕獲 1264800 13861twf.doc/m 。原子亚與2結合’從而阻止氫原子進人功能部件地或 土板30。由富含矽氧化物所形成的介電襯層3〇6更可 功能部件观和ILD層遍之間的阻障層㈣邮，以= 止，氣或形成ILD層綱所使㈣SO。溶液中的溶劑的 廣放口此’就增加了儲存於儲存元件3〇〇(例如俘獲層W 中的保持時間。此外’採用富含％氧化物所形成的介電襯 層306 ’就沒有必要在後續步驟(如形成ILD層3〇4)中 較低溫度。 寸 八類似地，在採用被金屬間介電(IMD)層所隔離的多層 金屬接點的儲存元件中，此IMD層可藉由SOG技術而幵^ 成，亚可使用富含矽氧化物之襯層，以防止溶劑向鄰近的 層擴散。例如為圖3B所示之本發明第二實施例的儲存元 件400。儲存元件4〇〇在半導體基板4〇上形成。儲存元件 400可包括形成於半導體基板40中的電路元件（圖未示）， 如電晶體或電容器。儲存元件4〇〇更可包括多個第一金屬 接點402和多個第二金屬接點4〇4而爲電路元件提供電性 ，觸。IMD層406將第一金屬接點402和第二金屬接點4〇4 電性隔離。IMD層406還填充基板40和第一金屬接點4〇2= Dielectric layer) is rich in stone-like lining, which is used to prevent SOG: deposit: Ϊ diffusion. FIG. 3A and FIG. 3 are diagrams showing a nonvolatile memory of the present invention. The memory device 300 of the first embodiment of the present invention is formed over the substrate % and includes the semiconductor substrate 3; The ILLD layer 304 is formed on the wide F piece 302 at the substrate tray to provide an insulating function and to fill the substrate 30 = the monthly component and the other components or functional components on the substrate 3G 3〇2 The gap between them. ILD@304 can be formed by spin coating a training solution and solidifying it 10 1264800 13861 twf.doc/m and a functional component 3 〇t electrical layer 306 on the layer 304 and the substrate 30 ILD layer 304 can be opened to prevent Diffusion of hydrogen in the S〇G solution. All above. The portion formed in the dielectric liner (not shown) or 300 It Γ 3 (2) may comprise any suitable non-volatile storage element. Figure 3: V: is an interpole structure or a metal contact. For example, the component can be a multi-layer gate structure, wherein the parent gate structure includes, for example, a first dielectric layer above the substrate %: a charge trapping layer over the dielectric layer 308 310, the second dielectric layer 312 on the charge trap, the interpole 3M on the second dielectric layer M2, and the second layer and the second dielectric layer 312 may comprise an oxide, for example, a milk The charge trapping layer 310 can include a nitrogen cut or polycrystalline whisker 314. The drain electrode 314 can include a metal. As shown in FIG. 3A, the storage element 3 can further include a substrate 3 〇 formed and corresponding to the functional component 3 〇 2 Diffusion regions 316 and 318 on either side, wherein diffusion regions 316 and 318 are spaced apart by a segment distance and define a channel 32 therebetween. The dielectric liner 306 of the present invention is enriched in germanium and It can be formed by chemical vapor deposition (CVD) technology to contain a cerium-rich oxide, wherein the ratio of the number of (iv) to oxygen atoms in the rich-cut oxide is The ratio of the number of Si〇2. In one embodiment of the present invention, the ratio of the number of germanium atoms to oxygen atoms is higher than that of germanium. Thus, the dielectric liner 306 will contain a large number of danglingsiiic〇nb〇nd. In the subsequent step of forming the ILD layer 304, these hanging 矽 bonds will capture 1264800 13861 twf.doc/m. Sub-bonded with 2' to prevent hydrogen atoms from entering the functional component or the earth plate 30. The dielectric liner 3〇6 formed by the cerium-rich oxide is more capable of viewing the barrier layer between the functional component and the ILD layer. (4) Post, by =, gas or form an ILD layer (4) SO. The wide opening of the solvent in the solution increases the storage time stored in the storage element 3 (for example, the retention time in the trap layer W. The dielectric liner 306' formed by the % oxide is not necessary to have a lower temperature in subsequent steps (such as forming the ILD layer 3〇4). Similarly, in the inter-metal dielectric (IMD) layer In the isolated multi-layer metal contact storage element, the IMD layer can be formed by SOG technology, and a ruthenium-rich oxide liner can be used to prevent solvent from diffusing into adjacent layers. For example, FIG. 3B The storage element 400 of the second embodiment of the invention is shown. The storage element 4 is now The semiconductor substrate 4 is formed on the substrate 4. The storage element 400 may include circuit elements (not shown) formed in the semiconductor substrate 40, such as a transistor or a capacitor. The storage element 4 may further include a plurality of first metal contacts 402 and The plurality of second metal contacts 4〇4 provide electrical properties to the circuit components. The IMD layer 406 electrically isolates the first metal contacts 402 from the second metal contacts 4〇4. The IMD layer 406 also fills the substrate 40. And the first metal contact 4〇2
以及基板40上的其他元件或功能部件之間的缝隙。I]VfD f 406可以是藉由將SOG溶液旋塗並將其固化所形成。_ 馬含矽之介電襯層408乃是在IMD層406與基板40和第 :金屬接點402之間形成，用以阻止SOG溶液中氫的擴 散。IMD層406可在部分（圖中未示）或全部的介電襯層4〇8 上形成。 1264800 13861twf.doc/m 在本發明的一實施例中，介電襯層4〇8是一富含矽氧 化物層，其中矽原子數量與氧原子數量的比率大:： 因此，由於在富含石夕之氧化物襯層術巾之石夕懸掛鍵的存 在，用以形成IMD層406的SOG溶液中之溶劑中的氫原 子將會被阻止進入第一金屬接點4〇2或基板4〇内。 相較於Si02，富含矽氧化物具有更高折射率(refractive index)和消光係數(extincti〇n⑶也丨也价）。例如，富含石夕氧 化物所形成的襯層306或408對於小於40〇nm的波長可以 具有至少1.6的折射率或者是至少〇·5的消光係數。 襯層306或408可以具有大約爲200〜3000埃 (Angstrom)的厚度，其可藉由使用化學氣相沉積(CVD)技術 而形成’例如電漿增强之化學氣相沉積(PECVD)或高密度 之電漿化學氣相沉積(HDPCVD)技術。在化學氣相沉積技 術中’可以使用的氣體源之組合爲siH4和〇2、siH4和 乂0、TEOS和A或TE〇s和〇3，並可以控制氣體的流量 以獲付想要的石夕對於氧之比率。 在一實施例中，可使用混合於Ar中的SiH4與02之氣 體源組合並藉由CVD技術所形成之襯層306或408的厚 度大約為1000埃，其中SiH4、02和Ar的流量分別爲100 seem(母分鐘之標準立方厘米）、％ sccin和5〇 seem，並且 CVD的射頻(RF)功率爲3000W。換句話說，SiH4與02的 流量比率爲2。在上述條件下所形成的氧化物在248 nm波 長下的折射率大約爲1.5，消光係數大約爲1.7，並且矽原 子的濃度大於70%。 13 (8： I2648QQ6ltwUoc/m 進行==:=出儲存元件’並對其 元件的資料保持屬性，料^^方法所製造之儲存 "，方柱代表儲存元件丰Λ比較圖形。在圖 cycle)後之閥限電壓的變化，大碩取周期(reading 法所製造的儲存元件，第_ 對應於本發明的方 要f所示，採= 其貝料保持屬性要優於標準要求。 、：子兀牛 構的發明，可排列多個具有錯存單元或彻-And a gap between other components or functional components on the substrate 40. I] VfD f 406 can be formed by spin coating a SOG solution and curing it. The dielectric liner 408 of the horse is formed between the IMD layer 406 and the substrate 40 and the metal contact 402 to prevent diffusion of hydrogen in the SOG solution. The IMD layer 406 can be formed on portions (not shown) or all of the dielectric liners 4A8. 1264800 13861twf.doc/m In an embodiment of the invention, the dielectric liner 4〇8 is a cerium-rich oxide layer in which the ratio of the number of germanium atoms to the number of oxygen atoms is large: The presence of the diarrhea bond of the Shi Xizhi oxide lining towel, the hydrogen atoms in the solvent in the SOG solution used to form the IMD layer 406 will be prevented from entering the first metal contact 4〇2 or the substrate 4〇. Inside. Compared to SiO 2 , the cerium-rich oxide has a higher refractive index and an extinction coefficient (extincti 〇 n (3) is also valence). For example, the liner 306 or 408 formed by the rich cerium oxide may have a refractive index of at least 1.6 or an extinction coefficient of at least 〇·5 for wavelengths less than 40 〇 nm. Liner 306 or 408 may have a thickness of approximately 200 to 3000 Angstrom, which may be formed by chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD) or high density. Plasma chemical vapor deposition (HDPCVD) technology. In chemical vapor deposition technology, the combination of gas sources that can be used is siH4 and 〇2, siH4 and 乂0, TEOS and A or TE〇s and 〇3, and can control the flow of gas to get the desired stone. The ratio of oxygen to oxygen. In one embodiment, the thickness of the liner layer 306 or 408 formed by combining the gas source of SiH4 and 02 mixed in Ar and formed by CVD technique is about 1000 angstroms, wherein the flow rates of SiH4, 02, and Ar are respectively 100 seem (standard cubic centimeters of mother minutes), % sccin and 5 〇seem, and the radio frequency (RF) power of CVD is 3000W. In other words, the flow ratio of SiH4 to 02 is 2. The oxide formed under the above conditions has a refractive index of about 1.5 at a wavelength of 248 nm, an extinction coefficient of about 1.7, and a concentration of ruthenium atoms of more than 70%. 13 (8: I2648QQ6ltwUoc/m carries out ==:= out of the storage component' and maintains the attributes of its components, the storage made by the method ^^ method, and the square column represents the richness of the storage component. Figure in the figure cycle) After the change of the threshold voltage, the large acquisition period (the storage element manufactured by the reading method, the _ corresponding to the invention f shown, the mining = its material retention properties are better than the standard requirements. The invention of the yak structure can arrange multiple units with faulty units or
St而構成，存陣列。圖5㈣為本發明的二 列排=夕f 5ίΚ) °儲存器_ ’包括按多條行愈多條 歹J排列的多個儲存單元3〇〇，1 丁/、夕仏 應於字元線(wordline)w〜立元。^丁^_列分別對 據本發明，命曰轉、i 兀線⑽hne)BL。還有，根 上件可以在積體電路(1C)晶片 有儲存早疋300之結構的儲存單元共同形成 二構f成此種儲存器陣列或1C晶片 1 疋顯而易見的，因此在此便不再詳細討論。 1本發明已以較佳實施例揭露如上，然其並非用以 =舍日月’任何熟習此技藝者，在不脫離本發明之精 内，當可作些許之更動與潤飾，因此本發明之保 摩巳圍當視後附之申請專利範圍所界定者為準。 ，、π 【圖式簡單說明】 圖1Α繪示爲習知的非易失性儲存單元。 圖1Β繪示爲習知的儲存元件。 14 12648收— 圖2繪示爲圖ία所示之儲存單元的資料保持屬性在 , 與標準要求相比較的圖形表示。 圖3Α繪示爲本發明第一實施例的一種儲存元件。 圖3Β繪示爲本發明第二實施例的一種儲存元件。 圖4繪示為採用本發明的方法所製造的儲存元件的資 • 料保持屬性與其要求之標準的比較圖形。 圖5繪示爲本發明的一種儲存器陣列。 【主要元件符號說明】 • 10、30、40 :基板 1〇〇 :儲存單元 102、104 :擴散區 106 :通道 108、112 :介電層 110 ··俘獲層 114 :閘極 116 :層間介電質 φ 118 ··襯層 200 :儲存單元 . 202 :基板 204、206 ··金屬接點 208 :金屬間介電質層 210 :襯層 300 :儲存元件 302 ··功能部件 (8 15 13861twf.doc/m 1264800 304 :層間介電層 306、308、312 :介電層 310 :俘獲層 314 :閘極 316、318 :擴散區 • 320 :通道 400 :儲存元件 402、404 :金屬接點 # 406 ··金屬間介電層 408 :介電層 500 :儲存器陣列 WL :字元線 BL :位元線St is constructed and stored in an array. Figure 5 (d) is a two-row row of the present invention = 夕 f 5 Κ ° 储存 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储 储(wordline) w ~ Li Yuan. ^丁^_ Columns According to the present invention, the 曰 曰, i 兀 line (10) hne) BL. Further, the root member can be formed on the integrated circuit (1C) wafer having the structure in which the structure of the memory 300 is stored together to form the two structures f such a memory array or a 1C wafer 1 , so that it is not detailed here. discuss. 1 The present invention has been disclosed in the above preferred embodiments, but it is not intended to be used by the skilled person, and the present invention may be modified and retouched without departing from the spirit of the invention. The scope of the patent application scope attached to the company is subject to the definition of patent application. , π [Simple Description of the Drawings] FIG. 1A shows a conventional non-volatile storage unit. Figure 1A shows a conventional storage element. 14 12648 Receiving - Figure 2 is a graphical representation of the data retention properties of the storage unit shown in Figure ία compared to the standard requirements. FIG. 3A illustrates a storage element in accordance with a first embodiment of the present invention. FIG. 3A illustrates a storage element in accordance with a second embodiment of the present invention. Figure 4 is a graph showing the comparison of the material retention properties of the storage elements produced by the method of the present invention with the required standards. Figure 5 illustrates a memory array of the present invention. [Main component symbol description] • 10, 30, 40: substrate 1 〇〇: storage unit 102, 104: diffusion region 106: channel 108, 112: dielectric layer 110 · · capture layer 114: gate 116: interlayer dielectric Φ 118 ·· lining 200 : storage unit. 202 : substrate 204 , 206 · metal contact 208 : inter-metal dielectric layer 210 : lining 300 : storage element 302 · · functional components (8 15 13861twf.doc /m 1264800 304: interlayer dielectric layer 306, 308, 312: dielectric layer 310: trapping layer 314: gate 316, 318: diffusion region • 320: channel 400: storage element 402, 404: metal contact # 406 Inter-metal dielectric layer 408: dielectric layer 500: memory array WL: word line BL: bit line