TWI263318B - An electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts - Google Patents

An electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts

Info

Publication number
TWI263318B
TWI263318B TW091135289A TW91135289A TWI263318B TW I263318 B TWI263318 B TW I263318B TW 091135289 A TW091135289 A TW 091135289A TW 91135289 A TW91135289 A TW 91135289A TW I263318 B TWI263318 B TW I263318B
Authority
TW
Taiwan
Prior art keywords
contacts
allows
traces
routing
electronic assembly
Prior art date
Application number
TW091135289A
Other languages
English (en)
Other versions
TW200403821A (en
Inventor
Kuljeet Singh
Kevin E Wells
Julius Delino
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200403821A publication Critical patent/TW200403821A/zh
Application granted granted Critical
Publication of TWI263318B publication Critical patent/TWI263318B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S439/00—Electrical connectors
    • Y10S439/907—Contact having three contact surfaces, including diverse surface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Measuring Leads Or Probes (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
TW091135289A 2002-08-26 2002-12-05 An electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts TWI263318B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/228,524 US6885102B2 (en) 2002-08-26 2002-08-26 Electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts

Publications (2)

Publication Number Publication Date
TW200403821A TW200403821A (en) 2004-03-01
TWI263318B true TWI263318B (en) 2006-10-01

Family

ID=31887616

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091135289A TWI263318B (en) 2002-08-26 2002-12-05 An electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts

Country Status (8)

Country Link
US (3) US6885102B2 (zh)
CN (1) CN100541777C (zh)
AU (1) AU2002368185A1 (zh)
DE (1) DE10297785B4 (zh)
GB (1) GB2412495B (zh)
HK (1) HK1075327A1 (zh)
TW (1) TWI263318B (zh)
WO (1) WO2004019406A1 (zh)

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US6916995B2 (en) * 2003-02-25 2005-07-12 Broadcom Corporation Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing
US20050073805A1 (en) * 2003-09-19 2005-04-07 Brent Stone Integrated circuit package
US7259453B2 (en) * 2004-02-24 2007-08-21 Intel Corporation Hexagonal array structure for ball grid array packages
DE102006032073B4 (de) * 2006-07-11 2016-07-07 Intel Deutschland Gmbh Elektrisch leitfähiger Verbund aus einem Bauelement und einer Trägerplatte
JP2008098531A (ja) * 2006-10-14 2008-04-24 Funai Electric Co Ltd 半導体集積回路装置
US8103988B2 (en) * 2006-11-08 2012-01-24 Mentor Graphics Corporation Use of breakouts in printed circuit board designs
WO2008057598A2 (en) * 2006-11-08 2008-05-15 Mentor Graphics Corporation Alternating via fanout patterns
US7757196B2 (en) * 2007-04-04 2010-07-13 Cisco Technology, Inc. Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards
US7979983B2 (en) * 2007-04-04 2011-07-19 Cisco Technology, Inc. Connection an integrated circuit on a surface layer of a printed circuit board
JP2010123602A (ja) * 2008-11-17 2010-06-03 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
USD759022S1 (en) * 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
USD758372S1 (en) 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
WO2015146738A1 (ja) * 2014-03-24 2015-10-01 技術研究組合光電子融合基盤技術研究所 Ｉｃチップを基板に搭載させるための基板上のパッド・アレイ構造、並びに当該パッド・アレイ構造を有する光モジュール
USD864968S1 (en) * 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface
USD784309S1 (en) * 2015-07-15 2017-04-18 Samsung Electronics Co., Ltd. Electronic device

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US4932902A (en) * 1989-03-21 1990-06-12 Crane Electronics, Inc. Ultra-high density electrical interconnect system
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US5512765A (en) * 1994-02-03 1996-04-30 National Semiconductor Corporation Extendable circuit architecture
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US5589728A (en) * 1995-05-30 1996-12-31 Texas Instruments Incorporated Field emission device with lattice vacancy post-supported gate
US5784262A (en) * 1995-11-06 1998-07-21 Symbios, Inc. Arrangement of pads and through-holes for semiconductor packages
US5691569A (en) * 1995-12-20 1997-11-25 Intel Corporation Integrated circuit package that has a plurality of staggered pins
EP1311032B1 (en) * 1996-10-10 2006-09-20 Fci High density connector and method of manufacture
SG71046A1 (en) * 1996-10-10 2000-03-21 Connector Systems Tech Nv High density connector and method of manufacture
US6064113A (en) * 1998-01-13 2000-05-16 Lsi Logic Corporation Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances
JP4069991B2 (ja) * 1998-08-10 2008-04-02 株式会社 日立ディスプレイズ 液晶表示装置
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6664620B2 (en) * 1999-06-29 2003-12-16 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
US6474476B1 (en) * 2000-08-30 2002-11-05 Advanced Micro Devices, Inc. Universal carrier tray
US6417463B1 (en) * 2000-10-02 2002-07-09 Apple Computer, Inc. Depopulation of a ball grid array to allow via placement
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US6556454B1 (en) * 2000-10-31 2003-04-29 Agilent Technologies, Inc. High density contact arrangement
US6770963B1 (en) * 2001-01-04 2004-08-03 Broadcom Corporation Multi-power ring chip scale package for system level integration
US6677831B1 (en) * 2001-01-31 2004-01-13 3Pardata, Inc. Differential impedance control on printed circuit
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US6906425B2 (en) * 2002-03-05 2005-06-14 Resolution Performance Products Llc Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive
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TW539238U (en) * 2002-04-30 2003-06-21 Via Tech Inc Flip-chip packaging substrate

Also Published As

Publication number Publication date
GB2412495B (en) 2007-03-21
HK1075327A1 (en) 2005-12-09
AU2002368185A1 (en) 2004-03-11
DE10297785T5 (de) 2005-09-08
US6885102B2 (en) 2005-04-26
DE10297785B4 (de) 2013-10-10
US7064431B2 (en) 2006-06-20
CN1695244A (zh) 2005-11-09
GB2412495A (en) 2005-09-28
US7282796B2 (en) 2007-10-16
GB0502931D0 (en) 2005-03-16
CN100541777C (zh) 2009-09-16
US20050090125A1 (en) 2005-04-28
US20040036176A1 (en) 2004-02-26
WO2004019406A1 (en) 2004-03-04
TW200403821A (en) 2004-03-01
US20050087858A1 (en) 2005-04-28

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