TWI263229B - Memory device with interface for serial transmission and error correction method for serial transmission interface - Google Patents
Memory device with interface for serial transmission and error correction method for serial transmission interfaceInfo
- Publication number
- TWI263229B TWI263229B TW094108147A TW94108147A TWI263229B TW I263229 B TWI263229 B TW I263229B TW 094108147 A TW094108147 A TW 094108147A TW 94108147 A TW94108147 A TW 94108147A TW I263229 B TWI263229 B TW I263229B
- Authority
- TW
- Taiwan
- Prior art keywords
- serial transmission
- interface
- memory device
- error correction
- correction method
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Debugging And Monitoring (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094108147A TWI263229B (en) | 2005-03-17 | 2005-03-17 | Memory device with interface for serial transmission and error correction method for serial transmission interface |
US11/161,957 US20060236204A1 (en) | 2005-03-17 | 2005-08-24 | Memory device with serial transmission interface and error correction mehtod for serial transmission interface |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094108147A TWI263229B (en) | 2005-03-17 | 2005-03-17 | Memory device with interface for serial transmission and error correction method for serial transmission interface |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI263229B true TWI263229B (en) | 2006-10-01 |
TW200634835A TW200634835A (en) | 2006-10-01 |
Family
ID=37109998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094108147A TWI263229B (en) | 2005-03-17 | 2005-03-17 | Memory device with interface for serial transmission and error correction method for serial transmission interface |
Country Status (2)
Country | Link |
---|---|
US (1) | US20060236204A1 (zh) |
TW (1) | TWI263229B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418979B (en) * | 2008-04-09 | 2013-12-11 | Embedded programmable chip with debugging circuit and debugging method with spi protocol | |
TWI762900B (zh) * | 2020-02-27 | 2022-05-01 | 瑞昱半導體股份有限公司 | 電子裝置以及通訊方法 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7822958B1 (en) * | 2006-03-10 | 2010-10-26 | Altera Corporation | Booting mechanism for FPGA-based embedded system |
US8090955B2 (en) | 2007-10-17 | 2012-01-03 | Micron Technology, Inc. | Boot block features in synchronous serial interface NAND |
US8102710B2 (en) * | 2007-10-17 | 2012-01-24 | Micron Technology, Inc. | System and method for setting access and modification for synchronous serial interface NAND |
US8103936B2 (en) | 2007-10-17 | 2012-01-24 | Micron Technology, Inc. | System and method for data read of a synchronous serial interface NAND |
US8429329B2 (en) | 2007-10-17 | 2013-04-23 | Micron Technology, Inc. | Serial interface NAND |
US8549246B2 (en) * | 2008-04-30 | 2013-10-01 | Micron Technology, Inc. | SPI NAND protected mode entry methodology |
TW201239893A (en) * | 2011-03-25 | 2012-10-01 | Silicon Motion Inc | Method for enhancing data protection performance, and associated personal computer and storage medium |
KR20140074685A (ko) * | 2012-12-10 | 2014-06-18 | 삼성전기주식회사 | 전자 태그 장치 및 그의 통신 방법 |
JP6577302B2 (ja) * | 2015-08-28 | 2019-09-18 | 東芝メモリ株式会社 | メモリシステム |
US11023312B2 (en) * | 2018-11-21 | 2021-06-01 | Marvell Asia Pte, Ltd. | Serial management interface with improved reliability |
JP2020154584A (ja) * | 2019-03-19 | 2020-09-24 | キオクシア株式会社 | メモリシステム |
US11847077B2 (en) * | 2021-12-06 | 2023-12-19 | Himax Technologies Limited | Serial peripheral interface integrated circuit and operation method thereof |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5606532A (en) * | 1995-03-17 | 1997-02-25 | Atmel Corporation | EEPROM array with flash-like core |
US6356555B1 (en) * | 1995-08-25 | 2002-03-12 | Terayon Communications Systems, Inc. | Apparatus and method for digital data transmission using orthogonal codes |
JP3307579B2 (ja) * | 1998-01-28 | 2002-07-24 | インターナショナル・ビジネス・マシーンズ・コーポレーション | データ記憶システム |
US6466564B1 (en) * | 1998-09-14 | 2002-10-15 | Terayon Communications Systems, Inc. | Two dimensional interleave process for CDMA transmissions of one dimensional timeslot data |
US6718506B1 (en) * | 2000-10-02 | 2004-04-06 | Zoran Corporation | High speed DVD error correction engine |
US20040153902A1 (en) * | 2003-01-21 | 2004-08-05 | Nexflash Technologies, Inc. | Serial flash integrated circuit having error detection and correction |
-
2005
- 2005-03-17 TW TW094108147A patent/TWI263229B/zh active
- 2005-08-24 US US11/161,957 patent/US20060236204A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418979B (en) * | 2008-04-09 | 2013-12-11 | Embedded programmable chip with debugging circuit and debugging method with spi protocol | |
TWI762900B (zh) * | 2020-02-27 | 2022-05-01 | 瑞昱半導體股份有限公司 | 電子裝置以及通訊方法 |
Also Published As
Publication number | Publication date |
---|---|
US20060236204A1 (en) | 2006-10-19 |
TW200634835A (en) | 2006-10-01 |
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