1261919 1 3620twf.d〇c/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體及其製造方法，且特別是 有關於一種非揮發性記憶體及其製造方法。 【先前技術】 非揮發性記憶體中的可電抹除可程式唯讀記憶體 (Electrically Erasable Programmable Read Only Memory， eeprom)具有可進行多次資料之存入、讀取、抹除等動 作，且存入之資料在斷電後也不會消失之優點，所以已成 為個人電腦和電子設備所廣泛採用的一種記憶體元件。 典型的可電抹除且可程式唯讀記憶體係以摻雜的多晶 矽製作浮置閘極（Floating Gate)與控制閘極（c〇ntr〇1 Gate)。當記憶體進行程式化(Program)時，注入浮置閘極 的電子會均勻分布於整個多晶矽浮置閘極層之中。然而， f多晶矽浮置閘極層下方的穿隧氧化層有缺陷存在i，就 容易造成元件的漏電流，影響元件的可靠度。 因此，為了解決可電抹除可程式唯讀記憶體元件漏電 ，之問題，目前習知的-種方法是採用—電荷陷入層取代 多晶石夕浮置閘極，此電荷陷入層之材質例如是氮化^。這 種氮化石夕電荷陷入層上下通常各有一層氧化石夕，而形成〆 種包含氧切/氮财/氧㈣(⑽Q)複合介f層在_堆 豐式（Stacked)閘極結構，具有此堆疊式閘極結構之 EEPR0M通稱為氮化矽唯讀記憶體(NR〇M>。 然而，記憶體元件的敏感性相當高，亦即記情 易 受到後續製程的影響。在-般之氮化石夕唯讀記憶體之製輕 1261919 1 3620twf.doc/〇〇6 中，由於製程環境之影響，例如使用電漿(Plasma)、紫外 光(UV)等將會使控制閘極、電荷陷入層或基底受到損宝 而影響元件的可靠度，進而導致記憶體效能降低之問4吾 【發明内容】 ° 有鑑於此，本發明的目的在提出一種非揮發性記情 體，於纪憶胞區上設置一層保護層，以防止閘極與電荷γ 入層遭到IJV光及電漿破壞。 Α可曰 本發明的另一目的為提出一種非揮發性記憶體製造方 法，在製造過程中形成一保護層，用來保護其所覆蓋記情 胞區内的控制閘極與電荷陷入層，使其不受到後 UV光及電漿之谕據。 、、衣枉甲 與其它目的’本發明提出—種非揮發性記憶 由基底、複合介電層、控制閘極與保護層所組成 工介，置於基底上，且此複合介電層包含一底介電 ^-電何人層及-頂介電層，而電荷陷人層之材質可 3:。控制閘極設置於基底上。保護層設置於基底上， 電層，保護層之材f可為氮化梦、介電 介電抗反射材料可為富魏化石夕及富 夕鼠乳化石夕，吸光係數為1.3〜3之間。 本發明之非揮發性記憶體，由 來保護控制_與電荷陷入層 度，並增加記憶體的良率。了叫升雜體的可靠 提生記憶體之製造方法，包括 /、土底此基底包括-記憶胞區及—周邊電路區。接 1261919 1 3620twf.doc/006 著/於胞區上形成多個記憶胞結構，且於周邊電路區 ^形成多個閘極結構。這些記憶胞結構由一底介電層、— ^何陷入層、-頂介電層及—控制閘極；這些閘極結構包 間介電層與-間極。然後於基底上形成—保護層，覆 孤這些圮憶胞結構與這些閘極結構，而保護層材質包括氮 化矽丄介電抗反射材料；介電抗反射材料例如是富矽氧^ 矽及富矽氮氧化矽，其吸光係數為13〜3之間。接著， 於基底上形成一層間介電層，並於基底上形成一圖案化罩 幕層，此圖案化罩幕層覆蓋記憶胞區。然後，移除周邊電 路區之部分層間介電層及保護層，而於閘極結構側壁形成 一間隙壁。 、而且’在上述之非揮發性記憶體之製造方法中，圖案 化導體層’於記憶胞區上形成控制閘極，並於周邊電路區 亡形成閘極之步驟後，可進行一熱回火製程，以補償在進 行>儿積及钱刻等製程時所產生的非晶矽化的問題，回覆原 來結晶狀態。 ^在本發明之非揮發性記憶體的製造方法中，由於在記 t胞區上形成保護層，使得記憶胞區中的控制閘極與電荷 陷入層’在進行後續製程時不會受到UV光及電漿破壞， 因此可以提升記憶體的可靠度，並增加記憶體的良率。 β為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 清參照圖1到圖8，其繪示依照本發明一較佳實施例 1261919 1 3620twf.doc/006 的非揮發性記憶體之製造流程剖面圖。 首先，請參照圖1，提供一基底100，例如為矽基底。 此基底100可區分為一記憶胞區104及一周邊電路區 108。接著，在此記憶胞區1〇4中形成多個摻雜區m， 作為記憶胞的源極/汲極區。然後，在基底1〇〇上形成一 複合介電層128,此複合介電層128包含一底介電層116 一電荷陷入層12〇及-頂介電層124。其中，底介^層ιΐ6 的材質例如魏化發’其形成方法例如是熱氧化法 陷入層12G的材質例如歧化破，其形成方法例如是化風 ^相沈積法。當然，陷人層讀f並秘於氮化石夕: =以是其他具有使電伽人魏之财，例如是氮氧化 :。頂介電層124的材質例如是氧切， 例如是熱氧化法献學氣相_法。 4成的方法 ^後’於複合介電層128上形成1 132 ’以光阻層i32為罩幕 ^阻層 上的複合介電層。 歸周輕路區108 隨後，請參照圖2，移除圖案化之光阻層 100的周邊電路區購上形成一閘介 底 W之材質例如是氧化石夕，其形成二間層 接下來於複合介騎及閘介電層上形成」法。 體層140之材質例如是摻雜多晶石夕140。導 法例如是以臨揚rTn ·+、4办Μ 成^乡雜多晶石夕之方 法形成罐雜之方式，利用化學氣相沈積 接者，凊參照圖3，圖案化該導體層⑽，以在記憶 1261919 1362〇twf.doc/〇〇6 5，1。4内形成控制閘極144，並於周邊電路區108内形 成閘極148。。 以輔=，請參照圖4，進行—熱回火製程細，， 制閘極144及閘極148在進行沉積及爛等製程 2產生的非晶⑪化的問題。在此步驟中，於控制閘極⑷ 及問極^8表面會形成很薄的氧切層152。 接著’請參照圖5 ’於複合介電層124、閘介電層136、 控，閘極144與閘極148上方形成—保護層156，目的在 :4其下，控制閘極與電荷陷人層不受職續製程所影 二而保4層156的材質包括氮切或介電抗反射材料。 介電抗反射材料例如是富魏化賴富魏氧切，吸光 係數在1.3〜3之間。保護層128的形成方法，例如 氣相沉積法。 “接下來，請參照圖6，於保護層156上形成一層間介 電，160,而層間介電層16㈣材質包括氮化石夕、氧化石夕、 氮氧化矽組成的族群，或者是其他的介電材料。其中氧化 石夕例如疋以四乙氧基石夕烧teqs) 為反應氣體源形成之氧化石夕或棚構氧化碎、哪發玻璃 (phosphosilicate glass, PSG)與硼磷矽玻璃 (b〇r〇Ph〇Sph〇Silicate glass，BPSG)。層間介電層 16〇 的形 成方法’依照材質的不同包括化學氣相沉積法與旋轉塗佈 法0 再則’請參照圖7，於層間介電層160上形成一圖案 化光阻層164 ’覆蓋住記憶胞區1〇4。然後，以圖案化 1261919 1 3620twf.doc/006 $阻層164為遮罩’移除部分層間介電層_ =編8之側壁形成間隙壁168。移除部分層= 160及保護層156之方法包括非等向性㈣法 ^ 應性離子蝕刻法。 ^疋反 隨後’請參照圖8,移除記憶胞區1〇4中的光阻層160, 形成-擁有記憶胞區104及周邊電路區⑽的 憶體。後續完成鱗紐記憶體㈣料習知技術麵= 知’在此不再資述。 “、、 枉本貫施例中，由於在記憶胞區上形成控制閘 極，亚於周邊電路區上形成閘極後，進行一熱回火势程，] 以補償在進行沉積及侧等製程時所產生的非晶魏^ 題，回覆原來結晶狀態。 而且’由於在記憶胞區上形成保護層，使得記憶胞區 中的控制閘極與電荷陷入層，在進行後續製程時不會受到 W光及電漿破壞，因此可以提升記憶體的可靠度，並增 加記憶體的良率。此外，層間介電層也可以進—步對控^ 閘極與電荷陷人層進行隔離，同樣具有保護的作用。工 請參照圖8，其繚示依照本發明一較佳實施例的 發性記憶體剖面圖。 此記憶體元件，有一基底100，此基底100包括記憶 胞區104及周邊電路區108兩部分。記憶胞區1〇4包括基 ，1〇〇、複合介電層128、控制閘極144、源極/汲極區112、 氧化層152、保護層156與層間介電層16〇。 複合介電層128設置於基底1〇〇上，此複合介電層128 1261919 1 3620twf.doc/006 内包含底介電層116、電荷陷入層120及頂介電層124。 底介電層116的材質例如是氧化矽；電荷陷入層12()的材 質例如是氮化矽；頂介電層124的材質例如是氧化矽。 控制閘極144設置在複合介電層112上。源極/汲極 區112設置於控制閘極144兩側之基底10()中。氧化層152 設置於控制閘極144上。保護層156覆蓋在複合介電層128 及氧化層152上，其中保護層156的材質包括氮化矽、介 電抗反射材料。介電抗反射材料例如是富矽氧化矽與或富 矽氮氧化矽，吸光係數在1·3〜3之間。層間介電層16〇設 置於保護層156上方，層間介電層160組成的材料包括氮 化矽、氧化矽、氮氧化矽組成的族群，或者是其他的介電 材料。其中氧化石夕例如是以四乙氧基石夕烧 (tetraethylorthosilicate，TEOS)為反應氣體源形成之氧化石夕 或蝴磷氧化矽(BPTE0S)、硼矽玻璃（phosphosilicate glass， PSG)與侧麟石夕玻璃（b〇r〇ph〇sphosilicate glass，BPSG)。 另一方面，周邊電路區108包括基底100、閘介電層 136、閘極148、與間隙壁168。其中，閘介電層136設置 於基底100上。閘極148設置在閘介電層136上。間隙壁 140没置在閘極124兩旁。 於本發明上述實施例中之非揮發性記憶體，因為其結 構包含一保護層，可使非揮發性記憶體記憶胞區中的控制 閘極與電荷陷入層，在製造過程中不受到UV光與電漿的 破壞，因此可以提升記憶體的可靠度，並增加記憶體的良 率〇 1261919 1 3620twf.doc/006 雖然本發明已以較佳實施例揭露如上，鈇 限定本發明，任何熟習此技藝者，在a亚非用以 和範圍内，♦可作此卞夕^ 脫離本發明之精神 ί 作牧更動與潤飾，因此本發明之伴Μ 靶圍當視後附之申請專利範圍所界定者為準。 ”^ 【圖式簡單說明】 圖1至圖8是依照本發明之一較佳實施例之非揮發性 記憶體的製造流程剖面圖。 【主要元件符號說明】 100 : 基底 104 ： 記憶胞區 108 ： 周邊電路區 112 ： 源極/汲極區 116 ： 底介電層 120 ： 電何陷入層 124 ： 頂介電層 128 ： 複合介電層 132、 k Μ4 :光阻層 136 閘介電層 140 導體層 144 控制閘極 148 閘極 152 氧化層 156 保護層 160 層間介電層 164 :間隙壁1261919 1 3620twf.d〇c/006 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a memory and a method of fabricating the same, and more particularly to a non-volatile memory and a method of fabricating the same. [Prior Art] Electrostatic Erasable Programmable Read Only Memory ( eeprom) has the functions of storing, reading, erasing, etc., and The stored data does not disappear after power failure, so it has become a memory component widely used in personal computers and electronic devices. A typical electrically erasable and programmable read-only memory system uses a doped polysilicon to create a floating gate and a control gate (c〇ntr〇1 Gate). When the memory is programmed, the electrons injected into the floating gate are evenly distributed throughout the polysilicon floating gate layer. However, the tunnel oxide layer under the f-polysilicon floating gate layer is defective in i, which easily causes leakage current of the device and affects the reliability of the device. Therefore, in order to solve the problem of electrically erasing the leakage of the programmable read-only memory device, the conventional method is to replace the polycrystalline rock floating gate with a charge trapping layer, and the material of the charge trapping layer is, for example, It is nitriding ^. This type of nitriding charge has a layer of oxidized oxide on the upper and lower sides of the layer, and the formation of the cerium includes oxygen cut/nitrogen/oxygen (tetra) ((10)Q) composite layer in the _ stacked gate structure. The EEPR0M of this stacked gate structure is commonly referred to as a tantalum nitride read-only memory (NR〇M>. However, the sensitivity of the memory element is quite high, that is, the sensation is susceptible to subsequent processes. In the fossil eve reading memory, light 1261919 1 3620twf.doc/〇〇6, due to the influence of the process environment, for example, using plasma, ultraviolet (UV), etc., will cause the control gate and charge to be trapped. Or the substrate is damaged by the damage and affects the reliability of the component, which leads to the decrease of the memory performance. 4 In view of this, the object of the present invention is to propose a non-volatile grammar, in the memory area A protective layer is disposed on the gate to prevent the gate and charge γ from being damaged by IJV light and plasma. Another object of the present invention is to provide a non-volatile memory manufacturing method, which forms a process in the manufacturing process. Protective layer to protect it from being covered The control gate and the charge trapping layer in the sensation cell are not subjected to the post-UV light and the plasma. The cloth, armor and other purposes are proposed by the present invention. The dielectric layer, the control gate and the protective layer are formed on the substrate, and the composite dielectric layer comprises a bottom dielectric layer and a top dielectric layer, and the material of the charge trap layer 3: The control gate is disposed on the substrate, the protective layer is disposed on the substrate, the electrical layer, the protective layer material f can be a nitrided dream, the dielectric dielectric anti-reflective material can be a Fuwei fossil and a Fuxi mouse Emulsified Shi Xi, the absorption coefficient is between 1.3 and 3. The non-volatile memory of the present invention is used to protect the control _ from the charge trapping layer and increase the yield of the memory. The manufacturing method of the body, including /, the bottom of the substrate comprises a - memory cell region and a peripheral circuit region. Connected to 1261919 1 3620twf.doc/006 to form a plurality of memory cell structures on the cell region, and in the peripheral circuit region ^ Forming a plurality of gate structures. These memory cell structures are composed of a bottom dielectric layer, — ^ a trapping layer, a top dielectric layer, and a control gate; these gate structures form an intervening dielectric layer and an interpole. Then a protective layer is formed on the substrate to cover the memory structures and the gate structures. The protective layer material comprises a tantalum nitride dielectric anti-reflective material; the dielectric anti-reflective material is, for example, an yttrium-rich ytterbium oxide and a yttrium-rich yttrium oxynitride, the absorption coefficient of which is between 13 and 3. Then, formed on the substrate An intervening dielectric layer forms a patterned mask layer on the substrate, the patterned mask layer covers the memory cell region, and then removes part of the interlayer dielectric layer and the protective layer of the peripheral circuit region, and the gate electrode The sidewall of the structure forms a spacer. And in the manufacturing method of the non-volatile memory described above, the patterned conductor layer forms a control gate on the memory cell region, and after the step of forming a gate in the peripheral circuit region A thermal tempering process can be performed to compensate for the problem of amorphous deuteration generated during the process of performing the process of "producting" and "money engraving", and to restore the original crystalline state. In the method of manufacturing a non-volatile memory of the present invention, since the protective layer is formed on the t cell region, the control gate and the charge trapping layer in the memory cell region are not subjected to UV light during subsequent processes. And plasma destruction, which can improve the reliability of the memory and increase the yield of the memory. The above and other objects, features and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] Referring to Figures 1 through 8, there are shown cross-sectional views showing a manufacturing process of a non-volatile memory of 1261919 1 3620twf.doc/006 in accordance with a preferred embodiment of the present invention. First, referring to Figure 1, a substrate 100 is provided, such as a germanium substrate. The substrate 100 can be divided into a memory cell region 104 and a peripheral circuit region 108. Next, a plurality of doping regions m are formed in the memory cell region 〇4 as the source/drain regions of the memory cells. Then, a composite dielectric layer 128 is formed on the substrate 1 . The composite dielectric layer 128 includes a bottom dielectric layer 116 , a charge trapping layer 12 , and a top dielectric layer 124 . Here, the material of the underlayer ΐ6 such as Weihuafa is formed by, for example, thermal oxidation of the material of the layer 12G, such as disproportionation, and the formation method is, for example, a chemical vapor deposition method. Of course, the trapping layer reads f and secrets it to the nitrite eve: = so that the other has the power of making electricity, such as nitrogen oxidation:. The material of the top dielectric layer 124 is, for example, oxygen cut, for example, a thermal oxidation method. A 40% method is used to form 1 132 ′ on the composite dielectric layer 128 with the photoresist layer i32 as a composite dielectric layer on the mask layer. Returning to the Zhou light road area 108 Subsequently, referring to FIG. 2, the peripheral circuit area of the patterned photoresist layer 100 is removed to form a material forming a gate W, such as oxidized oxide, which forms a two-layer layer. The composite media is formed on the dielectric layer of the gate and the gate. The material of the bulk layer 140 is, for example, doped polycrystalline stone eve 140. The guiding method is, for example, a method of forming a tank by using a method of forming a tank, using a chemical vapor deposition method, and patterning the conductor layer (10) with reference to FIG. The control gate 144 is formed in the memory 1261919 1362〇twf.doc/〇〇6 5,1. 4, and the gate 148 is formed in the peripheral circuit region 108. . With the auxiliary =, please refer to Fig. 4, the heat tempering process is fine, and the gate electrode 144 and the gate 148 are in the process of performing deposition and ruining. In this step, a very thin oxygen cut layer 152 is formed on the surface of the control gate (4) and the gate electrode 8. Next, please refer to FIG. 5 to form a protective layer 156 over the composite dielectric layer 124, the gate dielectric layer 136, the control gate 144 and the gate 148. The purpose is to: 4, control the gate and the charge trapping The layer is not affected by the occupational process and the material of the 4th layer 156 includes nitrogen cut or dielectric anti-reflective material. The dielectric antireflective material is, for example, a Fuweiweilaifuwei oxygen cut, and the light absorption coefficient is between 1.3 and 3. A method of forming the protective layer 128, such as a vapor deposition method. "Next, please refer to FIG. 6, an interlayer dielectric 160 is formed on the protective layer 156, and the interlayer dielectric layer 16 (4) material includes a group consisting of nitride rock, oxidized oxide, and arsenide oxynitride, or other intermediaries. An electric material, wherein the oxidized stone is formed by a oxidized stone or a oxidized slag, or a phosphite glass (PSG) and a bismuth phosphide glass (b 〇 氧化 疋 疋 四 四 四 四 四 四 四 四 四 四 四 四 四 phosph phosph phosph phosph phosph phosph phosph phosph phosph phosph phosph r〇Ph〇Sph〇Silicate glass, BPSG). The formation method of the interlayer dielectric layer 16〇 includes chemical vapor deposition and spin coating according to the material. 0 Further, please refer to Figure 7, dielectric between layers. A patterned photoresist layer 164' is formed on the layer 160 to cover the memory cell region 〇4. Then, a portion of the interlayer dielectric layer is removed by patterning 1261919 1 3620 twf.doc/006 $ resist layer 164 as a mask. The sidewalls of the braid 8 form a spacer 168. The method of removing the partial layer = 160 and the protective layer 156 includes an anisotropic (four) method of reactive ion etching. ^ 疋 随后 subsequent 'Please refer to Figure 8, remove the memory cell The photoresist layer 160 in 1〇4 forms a memory cell region 104 and peripheral circuits The memory of the area (10). Subsequent completion of the scales of the memory (four) material knowing the technical surface = know 'not to be described here. ',, 枉 贯 施 施 , 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成After forming a gate on the peripheral circuit region, a thermal tempering potential is performed, to compensate for the amorphous state generated during the deposition and side processes, and to return to the original crystalline state. Moreover, since the protective layer is formed on the memory cell region, the control gate and the charge trapping layer in the memory cell region are not damaged by W light and plasma during the subsequent process, thereby improving the reliability of the memory. And increase the yield of the memory. In addition, the interlayer dielectric layer can also isolate the gate and the charge trapping layer in a step-by-step manner, and also has a protective effect. Referring to Figure 8, a cross-sectional view of an active memory in accordance with a preferred embodiment of the present invention is shown. The memory component has a substrate 100 including a memory cell region 104 and a peripheral circuit region 108. The memory cell 1〇4 includes a base, a germanium, a composite dielectric layer 128, a control gate 144, a source/drain region 112, an oxide layer 152, a protective layer 156, and an interlayer dielectric layer 16A. The composite dielectric layer 128 is disposed on the substrate 1 . The composite dielectric layer 128 1261919 1 3620 twf.doc/006 includes a bottom dielectric layer 116, a charge trapping layer 120, and a top dielectric layer 124. The material of the bottom dielectric layer 116 is, for example, ruthenium oxide; the material of the charge trap layer 12 () is, for example, tantalum nitride; and the material of the top dielectric layer 124 is, for example, ruthenium oxide. Control gate 144 is disposed on composite dielectric layer 112. The source/drain regions 112 are disposed in the substrate 10() on both sides of the control gate 144. The oxide layer 152 is disposed on the control gate 144. The protective layer 156 is overlying the composite dielectric layer 128 and the oxide layer 152. The material of the protective layer 156 includes tantalum nitride and a dielectric anti-reflective material. The dielectric antireflective material is, for example, cerium-rich cerium oxide or cerium lanthanum oxynitride, and the light absorption coefficient is between 1-3 and 3. The interlayer dielectric layer 16 is disposed above the protective layer 156. The material composed of the interlayer dielectric layer 160 includes a group consisting of cerium nitride, cerium oxide, cerium oxynitride, or other dielectric materials. Among them, oxidized stone eve, for example, is formed by tetraethoxyorthosilicate (TEOS) as a reaction gas source, or oxidized cerium oxide (BPTE0S), phosphosilicate glass (PSG) and side lining Glass (b〇r〇ph〇sphosilicate glass, BPSG). On the other hand, the peripheral circuit region 108 includes a substrate 100, a gate dielectric layer 136, a gate 148, and a spacer 168. The gate dielectric layer 136 is disposed on the substrate 100. Gate 148 is disposed on gate dielectric layer 136. The spacers 140 are not placed on either side of the gate 124. The non-volatile memory in the above embodiments of the present invention, because the structure comprises a protective layer, can make the control gate and the charge trapping layer in the non-volatile memory memory cell region, and is not subjected to UV light during the manufacturing process. And the destruction of the plasma, so that the reliability of the memory can be improved, and the yield of the memory can be increased. 1261919 1 3620twf.doc/006 Although the present invention has been disclosed in the preferred embodiments as above, the present invention is limited to any of the above. The skilled person, in the context of a sub-African and non-existent, can be used for the purpose of this invention, and the spirit of the present invention is removed from the spirit of the present invention. Therefore, the target of the present invention is defined by the scope of the patent application. Subject to it. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 8 are cross-sectional views showing a manufacturing process of a non-volatile memory according to a preferred embodiment of the present invention. [Description of Main Components] 100: Substrate 104: Memory Cell Area 108 : Peripheral circuit region 112 : source/drain region 116 : bottom dielectric layer 120 : electrical trapping layer 124 : top dielectric layer 128 : composite dielectric layer 132 , k Μ 4 : photoresist layer 136 gate dielectric layer 140 Conductor layer 144 control gate 148 gate 152 oxide layer 156 protective layer 160 interlayer dielectric layer 164: spacer