1260745 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種動態隨機存取記憶體(dynamic random access memory，DRAM)之電容溝渠的製作方法，尤 指一種增加溝渠面積的製作方法。 【先前技術】 隨著各種電子產品朝小型化發展之趨勢，半導體元件設 計的尺寸亦不斷縮小，以符合高積集度、高效能和低耗電 之潮流。以雙倍速同步動態隨機存取記憶體(Double Data Rate-Synchronous Dynamic Random Access Memory， DDR-SDRAM)為例，為提高積集度，溝渠電容結構已成為 業界所廣泛採用之高密度DRAM架構之一。其原理是在半 導體基材中蝕刻出深溝渠並於其内製成溝渠電容，再電連 接垂直型電晶體（vertical transistor)，以有效縮小記憶單元 (memory cell)之尺寸，妥善利用晶片空間。 請參考第1圖至第5圖，其顯示在一半導體基底10上 1260745 形成一深溝渠的習知步驟。首先如第1圖所示，半導體基 底10上已形成有一墊氧化層12以及一氮化矽層14。一般 而言，氮化石夕層14係利用低壓化學氣相沈積(low-pressure chemical vapor deposition, LPCVD)法形成，其厚度約介於 1000至2000埃(入)之間。如第2圖所示，習知製作一深溝 渠之前，需在氮化石夕層14表面上先沈積一 BSG膜16，用 來作為硬遮罩層（hardmask)。一般而言，BSG膜16的厚度 介於7.5k至15k埃之間，硼的濃度約為5.5wt%左右。 如第3圖所示，接著於BSG膜16上形成一圖案化之光 阻層18，且光阻層18具有複數個開口 19用以定義出各深 溝渠之圖案。隨後如第4圖所示，進行一第一乾蝕刻製程， 經由開口 19於BSG膜16及氮化矽層14中蝕刻出一開口 21。如第5圖所示，然後進行第二乾蝕刻製程，利用BSG 膜16為硬遮罩層，再繼續經由開口 21蝕刻墊氧化層12及 半導體基底10，形成深溝渠23。最後再於深溝渠23中依 序形成電容以及垂直型電晶體。 然而隨著製程線寬縮小至0.11微米，在蝕刻、填洞製 程的高寬比（aspect ratio)限制下，溝渠電容的面積也隨之減 少，直接影響到電容的電容值(capacitance)。一般而言，電 1260745 容值的公式可表示如下： C = k 其中，C為電容值，A為極板或電容面積，d為介質厚 度，而k表示介質強度和介質常數的乘積◦當電容值不足 時，會使得儲存在電容内的電何貢訊較難被彳貞測到’造成 讀取操作上的困擾或更新頻率（refresh frequency)的增加， 嚴重影響記憶體的運作效能。因此，在線寬極小的條件下， 如何製作出較大的溝渠電容面積，以有效提高電容的電容 值，實乃當務之急。 【發明内容】 因此本發明之目的在於提供一種增加溝渠面積的製作 方法，以解決習知溝渠電容面積不足的問題。 根據本發明之申請專利範圍中所揭露之增加溝渠面積 的製作方法，係先提供一半導體基底，並於該半導體基底 上形成一墊氧化層以及一氮化矽層。接著於該氮化矽層上 形成沈積一 BSG膜，用來作為硬遮罩層。然後進行一微影 製程，以於BSG膜上形成一光阻層。接著進行一第一乾蝕 刻製程，經由光阻層開口於BSG膜中蝕刻出一開口。隨後 1260745 進行一第二乾蝕刻製程，利用BSG膜為遮罩經由光阻層開 口蝕刻氮化矽層、墊氧化層及半導體基底，形成一深溝渠。 最後再進行一濕蝕刻製程，利用一熱APM(ammonium hydrogen peroxide mixture)溶液結合超音波於45°C溫度中 進一步蝕刻已形成之深溝渠。 由於本發明係利用一 APM溶液並結合超音波姓刻深溝 渠以擴大原有深溝渠之總表面積，因此可有效改善習知因 有限的溝渠面積而影響到電容值之問題。 【實施方式】 如前所述，為了解決溝渠電容面積不足的問題，本發明 係先於半導體基底表面形成一圖案化遮罩層，接著利用圖 案化遮罩層進行姓刻，以形成至少一深溝渠，然後將深溝 渠的底部製作出較寬的空間，使深溝渠的剖面形狀如同一 瓶子，具有頸部和瓶身，亦即所謂的瓶狀深溝渠 (bottle-shaped deep trench)，最後再利用APM溶液並結合 超音波蝕刻瓶狀深溝渠，以使溝渠電容在瓶身部分具有較 大的總表面積，提高電容值，以有效改善習知因有限的溝 渠面積而影響到電容值之問題。 1260745 為了使貴審查委員能更進一步瞭解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助説明用，並非用來對本發明加 以限制者。 請參考第6圖至第10圖。第6圖至第1〇圖為本發明第 一實施例製作一深溝渠之示意圖。如第6圖所示，首先於 半導體基底30表面形成一襯氧化層32，一氮矽化合物層 34堆疊於襯氧化層32上，以及一硼矽玻璃（BSG)層36堆 疊於氮矽化合物層34之上。接著如第7圖所示，形成一圖 案化之光阻層40，覆蓋於硼矽玻璃層36上，用以定義各 深溝渠之位置。隨後進行一第一乾姓刻製程，利用光阻層 40於硼矽玻璃層36中蝕刻出一開口，如第8圖所示。 然後再移除光阻層40，並進行一第二乾蝕刻製程，利 用硼矽玻璃層36為遮罩經由硼矽玻璃層36之開口蝕刻氮 矽化合物層34、襯氧化層32、及半導體基底30，以形成 一深溝渠41，如第9圖所示。其中，值得注意的是，由於 光學接近效應（optic proximity effect)以及钱刻控制等因 素’在第二乾蝕刻製程完成之後，深溝渠41的水平橫截面 牙貝“約略主現橢圓形狀，如第9圖之深溝渠上視圖42所 1260745 示。此外，在本發明之第一實施例中，硼矽玻璃層36、氮 石夕化合物層34和襯氧化層32係構成一圖案化遮罩層38， 而硼矽玻璃層36係為一選擇性製程，在其他情況下，亦可 直接利用氮矽化合物層34與襯氧化層32當做圖案化遮罩 層來進行乾蝕刻製程，形成深溝渠41。 接著如第10圖所示，再進行一濕#刻製程，利用一氨 水-過氣化氫混合溶液(ammonium hydrogen peroxide mixture，APM)並結合超音波震盪來蝕刻深溝渠41，以增加 深溝渠41内壁的總表面積。本發明之濕蝕刻製程的建議參 數條件如下： a· ΑΡΜ溶液之溫度係介於45 °C至68 °C之間； b·超音波功率介於600至800瓦之間； c· APM溶液之蝕刻速度大於1〇埃/1〇分鐘（1〇人/i〇min); 以及 d· APM溶液之氨水-過氧化氬的體積比NH40H:H202:H20 係介於1:1:5〜1:5:50。 由於本發明之濕蝕刻製程係沿著深溝渠41内之半導體基 底30的結晶平面進行蝕刻，故原本呈橢圓截面的深溝渠 41會被蚀刻成一八角形截面狀，如第10圖所示之深溝渠 上視圖43，進而擴大深溝渠41内壁的總表面積。 1260745 請參考第11圖。第11圖為本發明第二實施例製作一瓶 狀深溝渠之示意圖。如第11圖所示，在完成前述之第二乾 蝕刻製程之後，本發明係先於瓶狀深溝渠44之頂部侧壁表 面形成一遮罩層46，然後再利用加熱的APM溶液配合超 音波震盪來直接蝕刻未覆蓋有遮罩層46之瓶狀深溝渠44 侧壁，以形成瓶狀深溝渠44。 本發明第二實施例亦可在瓶狀深溝渠44之頂部側壁表 面形成遮罩層46之後，隨即進行一濕钱刻或乾姓刻製程， 先蝕刻未覆蓋有遮罩層46之瓶狀深溝渠44側壁，以形成 瓶狀深溝渠44，然後再利用加熱的APM溶液配合超音波 震盪沿著結晶平面來蝕刻未覆蓋有遮罩層46之瓶狀深溝 渠44的側壁，以增加瓶狀深溝渠44内壁的總表面積。其 中，遮罩層46可移除於該APM濕蝕刻製程之前，以同時 擴大瓶狀深溝渠44與該頂部側壁之整體總表面積，此外， 遮罩層46亦可移除於該APM濕蝕刻製程之後，用以維持 頂部侧壁之原先面積而只擴大瓶狀深溝渠44之總表面積。 有別於習知技術，本發明係利用一氨水-過氧化氫混合溶 液並結合超音波震盪來蝕刻深溝渠，以擴大原有深溝渠之 總表面積。除此之外，本發明又可應用於在半導體基底上 12 1260745 製作瓶狀深溝渠之方法上。除了可減少習知擴大瓶狀與非 瓶狀深溝渠之複雜步驟，更能有效節省製作瓶狀與非瓶狀 深溝渠之時間與成本。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖至第5圖為習知製作一瓶狀深溝渠方法的製程示意 圖。 第6圖至第10圖為本發明第一實施例製作一深溝渠之示意 圖。 第11圖為本發明第二實施例製作一瓶狀深溝渠之示意圖。 13 1260745 【主要元件符號說明】 10基底 14氮化矽層 18光阻層 21開口 30半導體基底 34氮矽化合物層 38圖案化遮罩層 41深溝渠 43深溝渠上視圖 46遮罩層 12 墊氧化層 16 BSG 膜 19 開口 23 深溝渠 32 襯氧化層 36 硼矽玻璃層 40 光阻層 42 深溝渠上視圖 44 瓶狀深溝渠1260745 IX. Description of the Invention: [Technical Field] The present invention provides a method for fabricating a capacitive trench of a dynamic random access memory (DRAM), and more particularly to a method for increasing the area of a trench. [Prior Art] With the trend toward miniaturization of various electronic products, the size of semiconductor component designs has been shrinking to meet the trend of high integration, high efficiency, and low power consumption. Taking Double Data Rate-Synchronous Dynamic Random Access Memory (DDR-SDRAM) as an example, in order to improve the degree of integration, the trench capacitor structure has become one of the high-density DRAM architectures widely used in the industry. . The principle is to etch a deep trench in a semiconductor substrate and to form a trench capacitor therein, and then electrically connect a vertical transistor to effectively reduce the size of the memory cell and make proper use of the wafer space. Referring to Figures 1 through 5, there is shown a conventional step of forming a deep trench on a semiconductor substrate 10 1260745. First, as shown in Fig. 1, a pad oxide layer 12 and a tantalum nitride layer 14 are formed on the semiconductor substrate 10. In general, the nitride layer 14 is formed by a low-pressure chemical vapor deposition (LPCVD) method having a thickness of between about 1,000 and 2,000 angstroms (in). As shown in Fig. 2, prior to the fabrication of a deep trench, a BSG film 16 is deposited on the surface of the nitride layer 14 as a hard mask. In general, the thickness of the BSG film 16 is between 7.5 k and 15 k angstroms, and the concentration of boron is about 5.5 wt%. As shown in Fig. 3, a patterned photoresist layer 18 is then formed over the BSG film 16, and the photoresist layer 18 has a plurality of openings 19 for defining the pattern of the deep trenches. Subsequently, as shown in Fig. 4, a first dry etching process is performed, and an opening 21 is etched through the opening 19 in the BSG film 16 and the tantalum nitride layer 14. As shown in Fig. 5, a second dry etching process is then performed, and the BSG film 16 is used as a hard mask layer, and the pad oxide layer 12 and the semiconductor substrate 10 are further etched through the opening 21 to form a deep trench 23. Finally, capacitors and vertical transistors are sequentially formed in the deep trenches 23. However, as the process line width is reduced to 0.11 micron, the area of the trench capacitor is reduced under the aspect ratio of the etching and hole filling process, which directly affects the capacitance of the capacitor. In general, the formula for the capacitance value of 1260745 can be expressed as follows: C = k where C is the capacitance value, A is the plate or capacitor area, d is the dielectric thickness, and k is the product of the dielectric strength and the dielectric constant. When the value is insufficient, it will make it difficult for the information stored in the capacitor to be detected as 'causing the trouble of reading operation or the increase of the refresh frequency, which seriously affects the operation efficiency of the memory. Therefore, under the condition that the line width is extremely small, how to make a large drain capacitor area to effectively increase the capacitance value of the capacitor is a matter of urgency. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method of fabricating a trench area to solve the problem of insufficient capacitance of a conventional trench. The method for fabricating the increased trench area disclosed in the scope of the present application is to first provide a semiconductor substrate and form a pad oxide layer and a tantalum nitride layer on the semiconductor substrate. A BSG film is then deposited on the tantalum nitride layer for use as a hard mask layer. A lithography process is then performed to form a photoresist layer on the BSG film. A first dry etching process is then performed to etch an opening in the BSG film through the photoresist layer opening. Subsequently, 1260745 performs a second dry etching process, and the BSG film is used as a mask to etch the tantalum nitride layer, the pad oxide layer and the semiconductor substrate through the photoresist layer to form a deep trench. Finally, a wet etching process is performed to further etch the formed deep trenches by using an APM (ammonium hydrogen peroxide mixture) solution in combination with ultrasonic waves at a temperature of 45 °C. Since the present invention utilizes an APM solution in combination with an ultrasonic surnamed deep trench to enlarge the total surface area of the original deep trench, it is possible to effectively improve the conventional problem of affecting the capacitance value due to the limited trench area. [Embodiment] As described above, in order to solve the problem of insufficient area of the drain capacitor, the present invention forms a patterned mask layer on the surface of the semiconductor substrate, and then uses the patterned mask layer to perform a surname to form at least one deep. Ditch, then make a wider space at the bottom of the deep trench, so that the deep trench has a cross-sectional shape like a bottle, with a neck and a bottle, also known as a bottle-shaped deep trench, and finally The APM solution is combined with the ultrasonic wave etching of the bottle-shaped deep trench, so that the drain capacitor has a large total surface area in the bottle portion, and the capacitance value is increased to effectively improve the conventional capacitance problem due to the limited trench area. 1260745 For a fuller understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. Please refer to Figures 6 to 10. Fig. 6 to Fig. 1 are schematic views showing the construction of a deep trench in the first embodiment of the present invention. As shown in Fig. 6, first, a liner oxide layer 32 is formed on the surface of the semiconductor substrate 30, a ruthenium nitride compound layer 34 is stacked on the liner oxide layer 32, and a boron bismuth glass (BSG) layer 36 is stacked on the nitrogen bismuth compound layer. Above 34. Next, as shown in Fig. 7, a patterned photoresist layer 40 is formed overlying the borosilicate glass layer 36 to define the locations of the deep trenches. A first dry etching process is then performed to etch an opening in the borosilicate glass layer 36 using the photoresist layer 40, as shown in FIG. Then, the photoresist layer 40 is removed, and a second dry etching process is performed to etch the yttrium nitride compound layer 34, the lining oxide layer 32, and the semiconductor substrate through the opening of the borosilicate glass layer 36 by using the borosilicate glass layer 36 as a mask. 30 to form a deep trench 41 as shown in FIG. Among them, it is worth noting that due to factors such as optic proximity effect and money engraving control, after the completion of the second dry etching process, the horizontal cross-section of the deep trench 41 is approximately elliptical in shape, such as Further, in the first embodiment of the present invention, the borosilicate glass layer 36, the nitriding compound layer 34 and the lining oxide layer 32 constitute a patterned mask layer 38. The boron germanium glass layer 36 is a selective process. In other cases, the nitrogen germanium compound layer 34 and the liner oxide layer 32 can be directly used as a patterned mask layer to perform a dry etching process to form a deep trench 41. Then, as shown in FIG. 10, a wet etching process is further performed, and the deep trench 41 is etched by using an ammonia hydrogen peroxide mixture (APM) in combination with ultrasonic oscillation to increase the deep trench 41. The total surface area of the inner wall. The recommended parameters of the wet etching process of the present invention are as follows: a· The temperature of the bismuth solution is between 45 ° C and 68 ° C; b · the ultrasonic power is between 600 and 800 watts;c. The etching rate of the APM solution is greater than 1 〇 / 1 〇 min (1 〇 person / i 〇 min); and the volume ratio of ammonia to argon peroxide in the d· APM solution is 1:1 between NH40H:H202:H20 5~1:5:50. Since the wet etching process of the present invention is etched along the crystal plane of the semiconductor substrate 30 in the deep trench 41, the deep trench 41 which is originally elliptical in cross section is etched into an octagonal cross section. The deep trench upper view 43 as shown in Fig. 10 further enlarges the total surface area of the inner wall of the deep trench 41. 1260745 Please refer to Fig. 11. Fig. 11 is a schematic view showing the manufacture of a bottle-shaped deep trench according to the second embodiment of the present invention. As shown in Fig. 11, after completing the second dry etching process described above, the present invention forms a mask layer 46 on the top side wall surface of the bottle-shaped deep trench 44, and then uses the heated APM solution to match the super-layer. The sound waves are oscillated to directly etch the sidewalls of the bottle-shaped deep trenches 44 that are not covered with the mask layer 46 to form the bottle-shaped deep trenches 44. The second embodiment of the present invention can also form a mask on the top side wall surface of the bottle-shaped deep trenches 44. After layer 46, a wet money engraving or dry engraving process is performed immediately. The sidewalls of the bottle-shaped deep trenches 44 of the mask layer 46 are not covered to form a bottle-shaped deep trench 44, and then the bottle not covered with the mask layer 46 is etched along the crystal plane by using a heated APM solution in conjunction with ultrasonic oscillation. The sidewalls of the deep trenches 44 are formed to increase the total surface area of the inner walls of the deep trenches 44. The mask layer 46 can be removed prior to the APM wet etching process to simultaneously enlarge the bulk of the deep trenches 44 and the top sidewalls. The total surface area, in addition, the mask layer 46 can also be removed after the APM wet etch process to maintain the original area of the top sidewall and only expand the total surface area of the bottle-shaped deep trench 44. Different from the prior art, the present invention utilizes an aqueous ammonia-hydrogen peroxide mixed solution combined with ultrasonic oscillation to etch deep trenches to expand the total surface area of the original deep trenches. In addition, the present invention is also applicable to a method of making a bottle-shaped deep trench on a semiconductor substrate 12 1260745. In addition to reducing the complex steps of expanding bottle-shaped and non-bottle deep trenches, the time and cost of making bottle-shaped and non-bottle-shaped deep trenches can be effectively saved. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the invention are intended to be included in the scope of the present invention. [Simple description of the drawings] Fig. 1 to Fig. 5 are schematic diagrams showing the process of making a bottle-shaped deep trench. 6 to 10 are schematic views showing the fabrication of a deep trench in the first embodiment of the present invention. Figure 11 is a schematic view showing the production of a bottle-shaped deep trench according to the second embodiment of the present invention. 13 1260745 [Description of main components] 10 substrate 14 tantalum nitride layer 18 photoresist layer 21 opening 30 semiconductor substrate 34 nitride compound layer 38 patterned mask layer 41 deep trench 43 deep trench upper view 46 mask layer 12 pad oxidation Layer 16 BSG film 19 opening 23 deep trench 32 lining oxide layer 36 borosilicate glass layer 40 photoresist layer 42 deep trench upper view 44 bottle-shaped deep trench
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