1258662 : 〇%丨 05625 玖、發明說明： 【發明所屬之技術領域】 種判斷-虛擬位址是否於一轉換 本發明提供一判斷方法，尤指_ 對照表内對應至一實體位址的方法。 【先前技術】 ^統巾⑽是―個不可或缺的裝置，而如何有效、 快速的存取記憶_資料是相_域研究者關。4 央處理系統在存取-記憶體_資料時，必須送出 二 ==所欲存取的資料是記憶體中的那—部分，這好像二 像成由巧個記憶單元組成，每個單元都有屬於它們自己的位^ ; 这些，憶？中實際的位址稱作是實體位址(Physical _)。然 而’-般電腦⑽中央處理系統在存取記憶 „實體位址，而是送出—個虛擬位址來表示所欲存 實體位址之間存在著—種轉換方式，可將-虛擬位址 Λ體位址’其巾，這種轉換方式是透過—個轉換對照緩衝儲 ^%ίΓ!ΓΓ^η Lookaside Buffer, ° 性，i有效率憶體是為了使電職統中的記憶體能夠更有彈 轉換舰緩_能可想成是—個大對日絲，對照表的—側是電 =中央處㈣_趣位址’而舰麵另—側是記憶體上的實體位 ，轉換對照_儲存觀範著兩齡址_顏係。當巾央處理系 取—記憶體中某位址的資料時，先與此表中的虛擬位址逐次比 衝餘ί果’再找出對應的實體位址即可進行資料的存取。轉換對照緩 =存器通常是内建於一個快取記憶體(cachemem〇ry)tp，以達到高 、、射的目的。關於轉換對照緩衝儲存器的映射方式，請參考圖一。 1258662 ： 093105625 圖:是具衫種頁容量轉換對照映射 …，…概 位元」，而第三部分^ Ϊ位疋址1轉位址」，第二部分是「索引 :非以單-記憶體做為對應單位，」 串連續的記憶體，同頁的記憶體位 個立。—頁即為- 位址可以看成是這些㈣頁的頁碼；㈣數做，_ ’·標籤比對 的索引。在比對的過程中，、首先利用.立^是某-組相關項目中 器所儲存對賴係的項目输，決料^ 龍緩衝儲存 ’至於每頁内的記憶 位址進行比對，找出所屬的頁碼為何，、因此決定二f11用標鐵比對 照緩衝齡H處理賴崎位址和料位㈣應师。轉換對 體則以直接存取方式即可適當處理。 然而，對於具有多细容量之轉換對 … 並不是固定的，舉例來說，它的容量大小有Ik位ΐ 几以及1M位το等等，圖-所示即為—個犯位 器中四種柯頁容量在轉換對照緩_翻中位===儲存 個化位元頁容量的頁位址具有10個位元數，分別的刀=第一 位元。如果索引位元所欲決定的對侧係項目有64項時，弟個9 位το來表不’因此在弟12至第15位元為索引位元。剩 即標籤比對位址。而-個64k位抑容量的脉址財 分別是彳U 〇位元至第15位元’第16㉔19四個位 最後剩下第20至第31為標籤比對位址。依此類推。 私 請參考圖二。圖二是先前轉換對照緩衝儲存器1〇的方塊圖。轉換 對照緩衝儲存器10具有四個相關記憶體區塊12、四個資料記情體區塊 14和-個多工器16。-虛擬位址中的索引㈣和標籤比對位錄^ 至相關記憶體區塊内，在相關記憶體區中索引位元選出各一記憶體内 容與標籤比對位址相比，並將比較結果輸出至多工器16。同時，索引 位元亦選出各資料記憶體區塊14對應到該索引位元之實體^址，並將 12586621258662 : 〇%丨 05625 玖, invention description: [Technical field] The judgment-virtual address is a conversion method. The present invention provides a judgment method, in particular, a method corresponding to a physical address in the comparison table. [Prior Art] ^The towel (10) is an indispensable device, and how to effectively and quickly access the memory _ data is the phase _ domain researcher. 4 Central processing system in the access-memory_data, must send out two == the data to be accessed is the part of the memory, it seems that the two images are composed of a smart memory unit, each unit Have their own bits ^; these, recall? The actual address in the middle is called the physical address (Physical _). However, the general computer (10) central processing system accesses the memory „physical address, but sends out a virtual address to indicate that there is a conversion method between the desired physical address, and the virtual address Λ The body address 'the towel', this conversion method is through a conversion control buffer storage ^%ίΓ!ΓΓ^η Lookaside Buffer, ° sex, i efficient memory is to make the memory in the electric system more elastic The conversion ship slow _ can be thought of as a big pair of Japanese silk, the comparison table - side is electricity = central (four) _ interesting address 'and the other side of the ship is the physical position on the memory, conversion control _ storage When viewing the data of a certain address in the memory, the data is first compared with the virtual address in the table. The address can be accessed. The conversion control cache is usually built in a cache memory (cachemem〇ry) tp to achieve high, and the purpose of the mapping. Please refer to Figure 1. 1258662 : 093105625 Figure: ..., ... allots", and the third part ^ Ϊ address 1 address 1 transfer address", the second part is "index: non-single-memory as the corresponding unit," serial continuous memory, same page The memory is standing upright. - The page is - the address can be regarded as the page number of these (four) pages; (4) the number, the index of the _ _ label comparison. In the process of comparison, first use the . ^ is a project related to the project stored in the group-related project, and it is determined that the memory buffer address is compared with each other. The reason why the page number belongs to it, therefore, it is decided that the second f11 uses the standard iron to process the Laiqi address and the material level (4) than the control buffer age H. The conversion object can be handled appropriately by direct access. However, for a conversion with a small capacity, it is not fixed. For example, its capacity has an Ik bit number and a 1M bit το, etc., and the figure shows four kinds of sitter The page capacity of the page is converted to 0. The median address === The address of the page storing the capacity of the bit page has 10 bits, and the respective knife = first bit. If there are 64 items in the contralateral system to be determined by the index bit, the 9 bits το are not shown as 'therefore, the 12th to the 15th bits are index bits. The remaining is the label comparison address. And the 64k bit capacity is located in the 彳U 〇 bit to the 15th bit, the 162419 four bits, and the remaining 20th to 31st are the tag alignment addresses. So on and so forth. Please refer to Figure 2 for privacy. Figure 2 is a block diagram of the previous conversion control buffer memory 1〇. The conversion control buffer 10 has four associated memory blocks 12, four data ticks 14 and a multiplexer 16. - the index (4) in the virtual address and the tag alignment record into the relevant memory block, and the index bit in the relevant memory area selects each memory content compared with the tag comparison address and compares The result is output to the multiplexer 16. At the same time, the index bit also selects the entity address of each data memory block 14 corresponding to the index bit, and will 1258662
Jx：. —j 結果輸出至多工器16。 的映器雖能有效的完成虛擬位址細位址 雜’製作成本因此相對提高，另 者，先前二個埠的記憶體來施行，設計複雜度也較高。再 I- = ί 不同頁容量賴料，每—頁位址的容量皆需 要圖一所不的轉換對照緩衝儲存器，如果有四種頁容量即需要 =ΞΤ儲存器侧地，對於應用在=== if二 言，先前技術的硬體會成正比例的增加，並不能 有效的利用硬體來完成虛触址與實體紐的轉換。 【發明内容】 本發明之巾請專利範_揭露—種騎—虛擬位址是否於一轉換 對照，内對應至-實體位輯方法，該虛擬位址係由複數個位元組 成，該轉換對照表包含複數個標籤位址、對應於各娜籤位址的頁型 態以及實體位置’該方法包含··接收該虛擬位址；依據頁觀之優先 次序§又疋該虛擬位址之頁型態；依據所設定之該虛擬位址之頁型態從 該虚擬位址中擷取索引位元及標籤比對位址；將所設定之該虛擬位址 之頁型態及所擷取之標籤比對位址與該轉換對照表中之頁型態及標籤 位址進行比對，·若步驟所設定之該虛擬位址之頁型態及所擷取之標籤 比對位址與該轉換對照表中一組頁型態及標籤位址相符，則據以排列 頁型態之優先次序。 【實施方式】 請參考圖三。圖三係為一虛擬位址32與一轉換對照表34之示意 圖。虛擬位址32包含一標籤比對位址，一索引位元以及一頁位址 I2s8662 l)4 丨修」丨： 0^1056： (Pagf。轉換表34包含紐個f型態，複數個賴位址以及複 數個實體位址。轉換對照表34内的頁型態、標鐵位址以及虛擬位址 都有-定的對應關係。頁位址為一串連續位元，依據頁型態的不同， 頁位址所具有的頁容量也不同。頁·即是表達不·量型態的頁位 址。例如’頁容量可以是lkb(b表示位元），4kb，腿，6伽，馳… 等等，不同頁型態在虛擬位置上所占的位元數皆不相同。索引位元由 數個位το域，时尋找轉換對照表34中與虛齡置概對的資料。 f本發明的較佳實施例中，料位福頁位址前的數個位元，舉例來 說，一個lkb容量大小的頁位址為虛擬位址％中第〇至第9位元； 而如轉換對照表34巾有16個項目（entries)射引位福四位元， ^佈^虛擬位址32中第1G至第13位元；其餘的第14至第&位元 疋標载比對位址。 ^發明⑹々擬位址32與轉換對照表34時，首先依照虛擬位置 开:的頁f.诉索引位元為虛擬位置中的那些位元，再依據索引 侦•叫W丧34中的標籤位址，接著，把標籤比對位址盥桿 戴位址相比’如果找心符合之標籤位關依_標籤位址所對鹿到 的轉換對照表34中頁型態嗔該龍態與絲定義师型能是否 符合。相符合表示虛擬位址32㊣在㈣對照表34中制—對應的實 體位址。 ' 請參考圖四。圖四係為本發明判斷—虛擬位址是否於—轉換對昭 表内對應至-實體紐之方法之流糊。本發明—項重要特色為能夠 針對不同Μ態的虛擬位置做判斷，並且，本發明會將這師型能排 列-料次序，使得本發_判斷過程更為迅速有效率。在步驟⑽ 中接收-虛擬位址。當接收該虛擬位址時，其實並不知道該虛擬位址 ^何《娜，鼠在步驟中，依顧型態之優先次序設定該 虛擬位址之頁龍。所謂頁型紐先:欠序是指在魏 中，不同頁型態出現的次數高低，出現次數愈高的有愈先之優先次 8 1258662 : (.)()3105625 8 H J ί 議丨:: 序’所以’在未知頁型態的情況下，設定所接收虛擬位置為較高優先 次數的頁型態將有比較大比對符合的機率。在步驟2〇〇中雖然依據的 是頁型態之優先次序來設定該接收之虛擬位置之頁型態，但是對同一 個接收的虛擬位置而言，如果第一次所設定的頁型態經比對後失敗， 則必須設定第二次的頁型態，每次所設的頁型態不能與之前重複，舉 例來說，如在接收之虛擬位址中所設之第一優先次序之頁型態比對失 敗，則下次設定第二優先次序之頁型態進行比對，如果又比對不成 功，則再下次設定第三優先次序之頁型態進行比對，依此類推。 當頁型態設定之後，頁位址所占據的位元數為已知，因此，索引 位元和標籤比對位址在虛擬位址内的位置隨之確定。在步驟3⑼中， 依據所設定之該虛擬位址之頁型態從該虛擬位址中擷取索引位元及 標籤比對位址。步驟400根據索引位元找到轉換對照表内的複數個標 籤位址，複數個標筚位址逐一與步驟300所擷取的標籤比對位址做比 對，而且，该複數個標籤位址對應的頁型態與步驟2⑽中設定的頁型 悲比對是否相同，當轉換對照表内的標籤位址和頁型態皆比對相同 時，才認定該接收的虛擬位址於該轉換對照表對應至一實體位址，只 要這兩獅·其巾-槪對不符合，㈣輯失賴情況。如果比 對成功，虛擬位址即可對應到一實體位址，比對流程告一段落，並進 入步驟500，而電腦系統將依據該實體位址順利的存取一記憶體内的 資料。 第-次的比對失敗，有可能是兩種情況，一是在步驟2〇〇中設定 的頁型純錯誤的，所以頁型態比對將不符合。在此情況下，又要進 入步驟200，開始下-次的比對。不過這時步驟所設定的頁型態 -樣參考頁型態的優先次序來設定，但是，對同一虛擬位址已設定過 卻比對不符合的頁型態將不能再於步驟2〇〇中設定。步驟2〇〇至步驟 棚會不斷的循還比對直到比對符合。如果所有的頁型態皆比對過 後’仍然無法比對成功，表示比對紐為第二鋪況：所接收的虛擬 1258662 叫㈡旧丨條Κ 位址亚不在轉換對照表的範圍内，換句話說，該虛擬位址無法於轉換 對照内對應到一實體位址。 在每t次比對成功之後，進入步驟500排列頁型態之優先次序。排 列頁型恶之優先次序的方法在本發明提供三個實施例。在第一個實施 幻之排序方法中’首先將戶斤有的頁型態排列一個初始的先後次序，在 每一乂接收虛擬位址而比對成功時，把該虛擬位址的頁型態提升一級 優先次序，但如果該虛擬位址的頁型態原本已是最高的優先次序，無 f再往上提升，就維持它最優先的次序。舉例來說，全部的頁型態依 =為IK，4K ’ 16K和64K。在其中的一次比對成功的虛擬位址之頁型 態為16K，則16K頁型態的優先次序將往上提升一級，次序變成1K， 16Κ，jK和64Κ，下一次的比對時是1Κ的頁型態比對成功，但1Κ的 頁型悲次序已是最高次序，所以維持不變，次序一樣是1Κ，服，狀 和 64Κ。 在排序方法的第二個實施例係把所有比對記錄中頁型態比對成功 次數最多的放在第一優先次序，其它的依次數做排列。排序方法描述 如下： (I) 計算各個比對過虛擬位址之頁型態的比對成功次數； (II) 依照比對成功次數，依序將各頁型態做排序，比對成功次數 愈多者排列為愈高之優先次序。 如果有兩種或兩種以上頁型態的比對成功次數相同，則這些頁型 態中不計較彼此的優先次序，可擇其中一種來排列。舉例來說，頁型 態1Κ的比對成功次數為12次，4Κ為15次，16Κ為9次，64Κ為12 次，則排列的次序可為4Κ、1Κ、、服或是4Κ、64Κ、1Κ、⑽。 在排序方法中之第三個實施例係使用雙位元計數器（2 bits counter)的排序方法排序頁型態的優先次序，雙位元計數器的排序法 為此領域之習知技藝者所熟悉的排序方法，不在本說明書中描述。以 1258662 ： 09j]〇56：5 十的排序方式為本發明之較佳實施例，其餘的方法_樣可以做為頁刑 態的排序。 ' 請參考圖五。圖五係為本發明可判斷一虛擬位址是否於一轉換 對照表内對應至-實體位址的判斷裝置4()。判斷裝置4()包含一遮罩 選擇模組42、-轉換對照模組5〇以及一次序產生模组44。轉換對昭 模組50 X包含-頁型態比較模組52、一標籤位址比較模、组54以及二 轉換對照記憶體56。遮罩選擇模組42接收—虛擬位址的輸入，並利 用，罩的方式獅献之虛擬舰巾某料元做輸出。在本發明 的實施例中，遮蔽了虛擬位址中的頁位址和標籤比對位址可選擇索引 位元輸出，遮蔽了虛擬位址中的頁位址和索引位元可選擇標籤比對位 址輸出。輸出索引位元至轉換對照模組5〇以作為轉換對照記憶體％ ⑽索引，另外，遮罩選擇模組42也輸出—頁型態訊號至轉換對照 杈組50，作為頁型態比較模組52内的比對之用。 甘轉換對照記憶體56内可視做之前所述之轉換對照表存放的硬體， 二中儲存了複數個標籤他、複數觀魏以及複數個實體位置。標 韻組54用姐較從遮罩騎做42輸__比對位址 置^對照記憶體56 _购紐。《比較模組52用來比較從遮 二j桓組42輸出的頁型態訊號與轉換對照記憶體％内的頁型態。 :仏籤位址tb較模組54和型態味餘52冑崎正確時，轉換對照 f組5〇發出—輯成功的輸出訊號，以及-相關訊號至次序產生模 、.且44。次序纽鎌44絲鋪該頁型態啸餘之比較 =轉換對照記憶體内複數《雙、之級次序，產生次序的方法可以 依^不同的演算法^而本發明的較佳實施射，次序產生模组44實 2述判斷-虛擬位址是否於一轉換對照表内對應至一實體位址方 擇排列頁型態之先後次序。次序產生模組44與遮罩選 型’產生㈣頁魏次序提供輕解模組42依據該頁 心-人序來輸出一虛擬位址之頁型態訊號和部分位元。 1258662 v::‘： ：〇%! 05625 本电明之判斷裝置4Q可以用平行傳輸(paraHel transmiSsi〇n) 的方式將貧料在各個模組之間傳遞，也可以使用序列傳輸（serial transmission)的方式來傳資料。平行傳輸的方式一般來說需要加倍 的硬體’但會有比較快的速度。本發明的較佳實施例中使用序列傳輸 的方式來傳資料’對於多種胃容量的情況下，硬體不需要增加，同時 ，來實現本發明判斷輕4Q所需的記憶體只需要—個埠的記憶體即 可，再者，由於本發明具有次序產生模組44的關係，大大的減少了 比對的_人數和比對的時間，目此，運算效率並不會比先前之轉換對照 緩衝儲存器來的差。 先月ίι的方法雜有效的完成？種頁容量之虛擬位址與實體位址的 映射，但是，由於在硬體上是·平行處理的方絲比對各個不同項 =的位7C ’所f的硬體設備會比較多且複雜，製作成本因此相對提 二而且’這樣的架構需要多個埠的記憶體來施行，辦複雜度也較 南°再者’先驗術巾制衫頁容制虛擬記憶體幾時，需要加 倍的硬體來實現先前之方法，成本A大提升。她於先顧術，本發 =靖-虛難址是否於-轉·^、表_應至—實體位址的方法X 一利用-制頁鶴優先次序的步驟，依據M態比對正確次數的 夕秦來設定-未知頁型態的虛擬位址，有效的減少比對時間，並且， -虛擬位址是否於-轉換對照表内對應至一實體位址的判斷 ft，可用序列傳輸的方式傳遞資料，減少了硬體的複雜度與 本，而且該麟裝置只需使用_讀寫柄記憶斷可，呈有輸 本、效率高的優點。 —成 做：^===專_，所 1258662 【圖式簡單說明】 圖式之簡單說明 圖一係為先前具有多種頁容量轉換對照映射方式之示意圖。 圖二係為先前轉換對照緩衝儲存器之方塊圖。 圖三係為一虛擬位址與一轉換對照表之示意圖。 圖四係為本發明判斷一虛擬位址是否於一轉換對照表内對應至一實體 位址之方法之流程圖。 圖五係為本發明可判斷一虛擬位址是否於一轉換對照表内對應至一實 體位址的判斷裝置之方塊圖。 圖式之符號說明 10 轉換對照緩衝儲存器 12 相關記憶體區塊 14 資料記憶體區塊 16 多工器 32 虛擬位址 34 轉換對照表 40 判斷裝置 42 遮罩選擇模組 44 次序產生模組 50 轉換對照模組 52 頁型態比較模組 54 標籤位址比較模組 56 轉換對照記憶體 58 輸出訊號Jx:. —j The result is output to multiplexer 16. Although the imager can effectively complete the virtual address fine address, the manufacturing cost is relatively high, and the other two memory devices are implemented, and the design complexity is also high. Then I- = ί different page capacity, the capacity of each page address needs to be converted to the comparison buffer memory, if there are four page capacity, you need to = ΞΤ storage side, for the application in = == If the second language, the hardware of the prior art will increase in proportion, and can not effectively use the hardware to complete the conversion of virtual address and entity. SUMMARY OF THE INVENTION The invention claims the patent specification _ disclosure-type riding-virtual address in a conversion control, corresponding to the - physical bit method, the virtual address is composed of a plurality of bits, the conversion control The table includes a plurality of tag addresses, a page type corresponding to each address, and an entity location. The method includes receiving the virtual address. According to the priority order of the page, the page type of the virtual address is further defined. And extracting an index bit and a tag alignment address from the virtual address according to the set page state of the virtual address; setting the page type of the virtual address and the captured tag Comparing the address with the page type and the tag address in the conversion table, and if the step of the virtual address page type and the tag comparison address and the conversion are compared with the conversion When a set of page types and tag addresses in the table match, the page type is prioritized accordingly. [Embodiment] Please refer to Figure 3. Figure 3 is a schematic diagram of a virtual address 32 and a conversion look-up table 34. The virtual address 32 contains a tag alignment address, an index bit and a page address I2s8662 l) 4 丨"": 0^1056: (Pagf. The conversion table 34 contains a new f-type, a plurality of The address and the plurality of physical addresses. The page type, the standard address, and the virtual address in the conversion table 34 have a corresponding correspondence. The page address is a string of consecutive bits, according to the page type. Differently, the page address has different page capacity. The page is the page address that expresses the non-type type. For example, the page capacity can be lkb (b means bit), 4kb, leg, 6 gamma, Chi ... and so on, different page types occupy different numbers of bits in the virtual position. The index bit is divided into several bits το field, and the data in the conversion table 34 is compared with the virtual age. In a preferred embodiment of the invention, the number of bits preceding the address of the page is, for example, a page address of a lkb size is the ninth to the ninth of the virtual address %; In the table 34, there are 16 items (entries) to shoot the position four bits, ^ cloth ^ virtual address 32 in the 1st to 13th bits; the remaining 14th to & bit 疋 labeling the address. ^Invention (6) virtual address 32 and conversion table 34, first according to the virtual location: page f. v. index bit is the bit in the virtual location, According to the index detection, the label address of the 34 is deleted, and then the label is compared with the address of the address of the mast, and the address of the label is determined by the label. According to the page type in Table 34, whether the dragon state and the wire definition type match can be met. The coincidence indicates that the virtual address 32 is in the (four) comparison table 34 corresponding to the physical address. ' Please refer to Figure 4. Figure 4 For the determination of the invention - whether the virtual address is in - the conversion of the method corresponding to the - entity in the mapping table. The present invention - an important feature is to be able to make judgments for different virtual positions, and the present invention This class can be arranged in order to make the _judgment process more efficient and efficient. In step (10), the virtual address is received. When the virtual address is received, the virtual address is not known. He "Na, the mouse in the step, according to the priority of the pattern set The page address of the virtual address. The so-called page type New Zealand: Under-order refers to the number of occurrences of different page types in Weizhong, the higher the number of occurrences, the higher the priority 8 1258662 : (.)()3105625 8 HJ ί Discussion:: In the case of an unknown page type, setting the received virtual position to a higher priority number of page types will have a greater chance of matching. In step 2〇〇 Although the page type of the received virtual position is set according to the priority of the page type, for the same received virtual position, if the first set page state fails after comparison, The second page state must be set, and the page state set each time cannot be repeated before. For example, if the page type alignment of the first priority set in the received virtual address fails, Then, the page pattern of the second priority is set for comparison next time. If the comparison is unsuccessful, the page pattern of the third priority is set next time for comparison, and so on. When the page type is set, the number of bits occupied by the page address is known, so the position of the index bit and the tag alignment address within the virtual address is determined. In step 3 (9), the index bit and the tag alignment address are retrieved from the virtual address according to the set page state of the virtual address. Step 400 finds a plurality of tag addresses in the conversion table according to the index bits, and the plurality of tag addresses are compared with the tag comparison addresses captured in step 300 one by one, and the plurality of tag addresses correspond to each other. Whether the page type is the same as the page type comparison set in step 2 (10), and when the tag address and the page type in the conversion table are the same, the received virtual address is determined in the conversion table. Corresponding to a physical address, as long as the two lions, their towel-槪 pair does not match, (4) the case of ignorance. If the comparison is successful, the virtual address can correspond to a physical address, the comparison process ends, and the process proceeds to step 500, and the computer system smoothly accesses the data in the memory according to the physical address. The first-time comparison fails. There may be two cases. One is that the page type set in step 2〇〇 is purely wrong, so the page type comparison will not match. In this case, it is again necessary to proceed to step 200 to start the next-to-time comparison. However, the page type-like reference page type set by the step is set in the priority order. However, the page type that has been set for the same virtual address but does not match the matching will not be set in step 2〇〇. . Step 2 〇〇 to the step The shed will continue to follow the comparison until the match is met. If all the page types are compared, the comparison is still not successful, indicating that the comparison is the second situation: the received virtual 1258662 is called (2) the old Κ Κ 亚 亚 亚 亚 亚 亚 亚 亚In other words, the virtual address cannot correspond to a physical address in the conversion control. After each t-alignment is successful, the process proceeds to step 500 to prioritize the page states. A method of prioritizing page faults provides three embodiments in the present invention. In the first implementation of the magic sorting method, 'the first page order of the households is arranged in an initial order, and when each virtual address is received and the comparison is successful, the page type of the virtual address is taken. Raise the first-level priority, but if the page state of the virtual address is already the highest priority, no f is promoted, and it maintains its highest priority. For example, all page states are = IK, 4K '16K and 64K. In the case where the page number of the successful virtual address is 16K, the priority of the 16K page type will be upgraded one level, the order becomes 1K, 16Κ, jK and 64Κ, and the next comparison is 1Κ. The page type comparison is successful, but the page order of the 1Κ is the highest order, so it stays the same, and the order is the same, 1st, servant, and 64Κ. In the second embodiment of the sorting method, the most prioritized page type comparisons in all alignment records are placed in the first priority order, and the other sequential numbers are arranged. The sorting method is described as follows: (I) Calculate the number of successful comparisons of the page types of each virtual address; (II) Sort the page types according to the number of successful matches, and compare the success times. The more people are ranked as higher priority. If there are two or more page types whose alignment success times are the same, then these page types do not care about each other's priorities, and one of them can be arranged. For example, if the page type 1Κ has 12 matches, 4 is 15, 16 is 9, and 64 is 12, the order can be 4Κ, 1Κ, or 4Κ, 64Κ, 1Κ, (10). The third embodiment in the ranking method prioritizes the page type using a two-bit counter sorting method, which is familiar to those skilled in the art. The sorting method is not described in this specification. The sorting manner of 1258662:09j]〇56:5 is a preferred embodiment of the present invention, and the remaining methods can be used as a sort of page sentence. ' Please refer to Figure 5. Figure 5 is a judging device 4() for determining whether a virtual address corresponds to a physical address in a conversion table. The judging device 4() includes a mask selection module 42, a conversion control module 5A, and an order generation module 44. The conversion module 50 X includes a page type comparison module 52, a tag address comparison mode, a group 54 and a binary conversion control memory 56. The mask selection module 42 receives the input of the virtual address, and uses the cover to make a virtual material of the lion's virtual ship to be output. In an embodiment of the present invention, the page address and the tag alignment address in the virtual address are masked, and the index bit output is masked, and the page address and the index bit in the virtual address are masked. Address output. The index index element is output to the conversion control module 5〇 as the index of the conversion control memory % (10), and the mask selection module 42 also outputs the page type signal to the conversion control group 50 as the page type comparison module. The comparison within 52 is used. The Gan conversion control memory 56 can be regarded as the hardware stored in the conversion table described above, and the second file stores a plurality of tags, a complex view, and a plurality of physical positions. The standard rhyme group 54 uses the sister to do 42 losses from the mask ride __ comparison address set ^ control memory 56 _ buy New Zealand. The comparison module 52 is used to compare the page state signals output from the mask group 42 and the page state in the conversion control memory %. When the address tb is more correct than the module 54 and the type of flavor 52 is not correct, the conversion control group f sends a successful output signal, and the - correlation signal to the order generation mode, and 44. Comparison of the order of the 镰 44 丝 该 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The generation module 44 determines whether the virtual address is in the order of the page layouts corresponding to a physical address in a conversion table. The sequence generation module 44 and the mask selection 'generate' (four pages) page order provide the light solution module 42 to output a page address signal and a partial bit of a virtual address according to the page-human order. 1258662 v::': :〇%! 05625 The device 4Q can transmit the poor material between the modules in parallel transmission (paraHel transmiSsi〇n), or use serial transmission. Ways to pass the information. Parallel transmission generally requires double the hardware' but at a faster rate. In the preferred embodiment of the present invention, the data is transmitted by means of sequence transmission. In the case of a plurality of gastric volumes, the hardware does not need to be increased, and at the same time, the memory required for the determination of the light 4Q of the present invention is only required. The memory can be used. Furthermore, since the present invention has the relationship of the order generation module 44, the number of comparisons and the time of the comparison are greatly reduced. Therefore, the operation efficiency is not buffered compared with the previous conversion. The difference between the storage. The method of the first month ίι is effectively completed? The mapping between the virtual address and the physical address of the page capacity, but because the hardware is a parallel processing of the square wire than the hardware device of the different items = bit 7C 'f, the hardware device will be more and more complicated, The cost of production is relatively high, and 'such an architecture requires a lot of memory to implement. The complexity is also higher than that of the South. In addition, the 'pre-tested towel's page capacity is virtual memory. When it needs to double the hardware. To achieve the previous method, the cost A is greatly improved. She is the first to follow the skill, the hair = the Jing-virtual address is in the - turn · ^, the table _ should be - the method of the physical address X - the use of - the priority of the pager, the correct number of times according to the M state Xi Qin to set the virtual address of the unknown page type, effectively reduce the comparison time, and - whether the virtual address is in the - conversion table corresponding to a physical address ft, the available sequence transmission Passing the data reduces the complexity and the hardware of the hardware, and the device can only use the _ read/write handle memory, which has the advantages of high cost and high efficiency. —成做:^===专营_,1258662 [Simple description of the schema] Brief description of the schema Figure 1 is a schematic diagram of the previous mapping method with multiple page capacity conversions. Figure 2 is a block diagram of the previous conversion control buffer memory. Figure 3 is a schematic diagram of a virtual address and a conversion table. Figure 4 is a flow chart of a method for determining whether a virtual address corresponds to a physical address in a conversion table. Figure 5 is a block diagram of a judging device for determining whether a virtual address corresponds to a real address in a conversion table. DESCRIPTION OF SYMBOLS 10 Conversion Control Buffer Memory 12 Related Memory Block 14 Data Memory Block 16 Multiplexer 32 Virtual Address 34 Conversion Comparison Table 40 Judging Device 42 Mask Selection Module 44 Sequence Generation Module 50 Conversion control module 52 page type comparison module 54 tag address comparison module 56 converts the comparison memory 58 output signal