1257923 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於藉由施用其上具有窗口的抑制層 來抑制陶瓷在燒結過程中之收縮的方法。本發明不需要在 心製後移除抑制層，從而避免習知技術中可能對陶瓷之表 面平整度造成破壞，且亦簡化了處理程序而得以降低製造 成本。因此，藉由本發明製造了具有高品質的多層陶瓷。 【先前技術】 為滿足現代電子產品輕、薄及小之要求，互連電路板必 不可少。互連電路板係電性或機械性互相連接的電子電 路，或係由組合成-配置許多極小電路組件所形成的子系 統:該等電路組件可在實體上加以隔離並相互鄰接地安裝 於單個互連電路板中以電性互相連接及/或藉由該互連電 路板而得以延伸。 在互連電路板中，複合電子電路通常需要使用多個絕緣 的介電層來分離導體層。穿過介電物且互料電層之導電 性路徑稱為通孔。該多層結構使得電路更緊湊且佔用更少 在製造多層電路的各種方法中，美國專利第4,654,〇95號 所述之方法係藉由共燒多個陶兗薄帶介電物，#中在該等 陶究薄帶介電物上之異質材料（例如，電阻器、電容器或:導 體）上已經印财金屬㈣孔，該等金屬㈣孔延伸穿過介 電層以互連各個導電層。依所設計地堆疊該等介電層，並 在適當溫度及μ力下將其堆録—起，且接著經燒製以驅 97232.doc 1257923 走陶瓷生胚中的有機物，例如黏合劑及增塑劑。由此燒結 並緻密化所有陶兗及異質材料。該方法具有如下優點：僅 執行一次燒製，節省製造時間及勞動力，並限制金屬導體 ::擴散以防止導電層之間發生短路。然而，因為陶瓷與異 貝材料之間的燒結收縮行為不—冑，所以難以控制燒製條 件。另外，在組裝較大及複雜電路時因對位不良所引起的 χ-γ維度不確定性尤其非吾人所要。 見在成乎所冑白勺I缩均係在z方向上加以控制而得以抑 制X-Y維度收縮。美國專利第5,085,72〇號（E· L Du p〇nt de127. The invention relates to a method for suppressing shrinkage of a ceramic during sintering by applying a suppressing layer having a window thereon. The present invention eliminates the need to remove the suppression layer after the core is made, thereby avoiding the possibility of damage to the surface flatness of the ceramic in the prior art, and also simplifying the processing procedure to reduce the manufacturing cost. Therefore, a multilayer ceramic having high quality is manufactured by the present invention. [Prior Art] In order to meet the requirements of light, thin and small in modern electronic products, interconnected circuit boards are indispensable. An interconnect circuit board is an electronic circuit that is electrically or mechanically interconnected, or a subsystem formed by combining - configuring a plurality of very small circuit components: the circuit components can be physically isolated and mounted adjacent to each other in a single The interconnect boards are electrically interconnected and/or extended by the interconnect board. In interconnected circuit boards, composite electronic circuits typically require the use of multiple dielectric layers to separate the conductor layers. The conductive path through the dielectric and the interconnected electrical layer is referred to as a via. The multilayer structure makes the circuit more compact and occupies less. In the various methods of fabricating a multilayer circuit, the method described in U.S. Patent No. 4,654, No. 95 is by co-firing a plurality of ceramic ribbon dielectrics. The metal (four) holes have been printed on the heterogeneous material (e.g., resistor, capacitor or: conductor) on the thin strip dielectric, and the metal (four) holes extend through the dielectric layer to interconnect the respective conductive layers. The dielectric layers are stacked as designed and stacked at an appropriate temperature and pressure, and then fired to drive 97232.doc 1257923 to remove organic matter in the ceramic green body, such as adhesives and additions. Plasticizer. This sinters and densifies all ceramics and heterogeneous materials. This method has the advantage of performing only one firing, saving manufacturing time and labor, and limiting metal conductors :: diffusion to prevent short circuits between the conductive layers. However, since the sintering shrinkage behavior between the ceramic and the meta-bean material is not 胄, it is difficult to control the firing condition. In addition, the uncertainty of the χ-γ dimension caused by poor alignment when assembling large and complex circuits is especially undesirable. It can be seen that the reduction of the X-direction is suppressed in the z-direction. US Patent No. 5,085,72 (E·L Du p〇nt de
Nemours and Company)^ ^ m ^ 551305067#u (InternationalNemours and Company)^ ^ m ^ 551305067#u (International
Business Machines C〇rporation)中揭示了該等方法，其中該等 案併入本文中以供參考。 在美國專利第5,085,720號中，陶竟生胚之頂部及底部各 力有釋放層以形成「二明治」結構ώ在燒溶及燒結過 程中，將單向壓力施加至該釋放層之表面，該釋放層之多 孔性為”生耗揮發性崎提供了逸^特1為釋放 層不會在燒製時收縮’所以陶曼生胚之χ_γ收縮得到抑制。 然而，釋放層覆蓋㈣生胚之頂部及底部表面，且在燒結 後必須將其移除以在陶㈣上印刷及燒製導體、電阻器及 電谷裔。因此，該方法夕士士 套之成本上升。另外，釋放層内所含 有的無機黏合劑滲人生胚、及釋放層之接觸角、黏度、孔 隙率及孔徑大小都會影響移除釋放層過程中陶竞表面的平 整度，且容易使電路印刷難以進行及H現缺陷。當製 造大量陶瓷層時（例如6層以上）， 由於藉由將釋放層施加至 97232.doc 1257923 生胚之頂部及底部所產生的力分佈不均衡，所以介電體之 中間層仍會收縮（意即，於生胚頂部及底部上之力與中間層 上之力相當不同）。 -美國專利第5J3M67號描述了抑制介電體之χ_γ收縮的 二種途徑。就第-種途徑而言，將約束力施加至介電體之 外4邊緣以提供揮發物之開放逸出路徑及氧氣之進入路 徑。就第二種途徑而言，藉由使用共延多孔遷板或藉由將 乳洋力施加至介電體之整個表面來將共延力施加至該表 面。就第三種途徑而言，藉由使用在燒製過程中不收縮或 不膨脹的多孔性接觸薄板來將摩擦力施加至生胚上。該接 =薄板包括多孔性組成’如具有燒製時保持多孔性^融 。至陶竟_L、熱穩定且具有連續機械完整性/剛性等性質， 則被選定為該多孔性組成。接觸薄板 尺寸，且由此限制陶究部分的收縮。燒結後，“Π破 ^陶竟表面的適當移除程序（例如’抛光及刮研）來移除接觸 ^反。然而’上述三種途径都有缺點。例如，因為第一種 途控使用—固定物所產生的重量來抑制收縮’且Μ力在介 電體上分佈不均衡，所以其容易導致陶 :電路形狀及陶究表面之平整度。第二種及第三種I; 要^燒製後進行移除步驟，成本增加，且其表面亦受破壞。 為了解決上述問題，本發明提出一種用 結過程中之收縮的新顧古土 、,— 丨市川无在k 之品質。 11方法’以郎約成本並改良陶究產品 【發明内容】 97232.doc 1257923 蝥明概述 化本發明主要係關於—種用於抑制陶竟在燒結過程中之收 ': = :，該等陶竟包括—介電部分及一異質材料部分， 方法包括如下步驟： U)提供一整體結構，該整體結構包括·· 包括至少-介電層之_介電體，其中該至少—介電層包 料=少—作龍域，其巾該❹區域設置有至少-異質材 模二案及且該異質材料圖案包括至少一異質材料組件及/或 —女置於介電體之頂部的_抑制層，該抑制層包括至少一 :^其中該介電層之作用區域的邊緣在垂直方向上均落 任5亥囪口内； (Μ燒製該整體結構；及 (c)沿-切割線單-化該整體結構以提供該等陶究，其中該 =割線設置在窗口邊緣與作用區域邊緣之間所形成的 區域内。 發明詳述說明 本發明提供m抑制”在燒結過程中之收縮的方 法，該方法較佳施用於藉由使用習知導電金屬、電阻器、 電谷☆導體、電感器、晶片或模組來製造多層陶究電路， 及在其製造過程中施用。根據本發明之方法具有如下優 點.抑制了陶究燒結過程中的χ·γ維度收縮，及避免在燒製 後移除抑制層而得以防止可能破壞表面平整度。 參見圖1，根據本發明之陶竟！包括介電部分⑽異質材 97232.doc 1257923 2部分12。介電部分11包括複數個介電層，在該等複數個 二電層上之異質材料部分12(例如，電阻器、電容器、導體、 電感器、晶片或模組）上已設置有金屬化通孔，該等金屬化 通孔延伸穿過介電體以互連不同介電層上之各種異質材 ^ /、貝材料σ卩分12包括表面黏著之主動組件或模組121、 通孔122及嵌入式組件或模組123。可在燒製介電層後將安 置於最外介電層之表面上的表面黏著之主動組件或模組 製造於介電層上，或將其與介電層共燒。通孔122係穿 過介電部分11以互連異質材料部分12的導電路徑。將介電 打孔且以導電材料（通常為銀）來填充以提供通孔 122。將嵌入式組件或模組123嵌入於介電層中，且藉由通 孔122在不同層上互連。藉由包含多個層，異質材料互連可 刀佈於’丨電層上及/或介電層内。因為現在可在三個維度上 安置異質材料，所以介電層内之異質材料互連使容納電路 所需的區域得以最小化。 根據本發明之方法的步驟係提供包括介電體3及抑制 層22的整體結構2(參見圖2至圖4)。 參見圖2及圖4，介電體3包括至少一介電層21。介電層21 包括至少一作用區域211，作用區域211上設置有至少一異 貝材料圖案212，且該異質材料圖案212包括至少一異質材 料組件及/或模組2121。燒製後，介電層構成陶瓷的介電部 勿，且異質材料圖案構成陶瓷的異質材料部分。根據本發 明之異質材料組件及/或模組2121包括電阻器、電容器、導 體、電感器、晶片或模組以形成異質材料圖案212。在本發 97232.doc 1257923 明之一較佳實施例中，入 各 ;1電層包括複數個作用區域211，且 母一作用區域211均係用扒制^ * η且 ”糸用於製造一陶瓷之一部分。 參見圖2及圖3，抑制 22勺赵$丨、 】㈢22女置於介電體3的上方。抑制層 2 2匕括至少^一窗口 λ Α ± ^ ^ , ’丨電層之作用區域211的邊緣2111 在垂直方向上均落在窗口 ^ 圖案212。 4 口 221内，以暴露介電層之異質材料 在本發明之一實施例中，作用卩妁9 n夕、息蜂+ + τ作用&域211之邊緣在垂直方向 t洛在抑制層的“内（未顯示）。在本發明之另-實施例 /稷數個作用區域213的邊緣作為-整體均落在抑制層的 固口内，例如窗口 221(如圖4所示）。 在本發明之一較佳實施例中，介電體3包括至少兩個介電 層。其中任一介電層之作用區域211之邊緣2111在垂直方向 上均落在抑制層22之窗口 221内。當提供至少兩個介電層 時，根據本發明<方法具有製造多層陶莞之能力。每一介 電層之異質材料圖案構成電路之一部分，且藉由通孔互連 其它介電層之異質材料圖案，而形成了完整電路。 在本务明之另一較佳實施例中，介電體3進一步包括安置 於η電層之間的抑制層23。抑制層23包括至少一窗口 23 1， 且每一介電層之作用區域之邊緣2111亦在垂直方向上均落 在抑制層23之窗口 23 1内。抑制層23之窗口 23 1可大於或小 於抑制層22之窗口 221。較佳地介電體3中抑制層23之窗口 23 1的大小及位置與安置於介電體3上方的抑制層22之窗口 221的大小及位置相同。藉由在介電體3中施加抑制層23， 根據本發明之方法可用於製造具有六層以上介電層之多層 97232.doc -10- 1257923 陶=，且其仍能避免燒結過程中的χ-γ維度上的收縮。 ’|電體之"電層之間所施加的抑制層之厚度（Li)較佳不 比相4於抑制層而安置於該抑制層下方之介電層上所設置 1質材料圖案的厚度⑹薄，且更佳地，Ll等於L2(Ll=L2) 以增強整體結構之均勻性。 在本發明之另一較佳實施例中，整體結構2進-步包括安 電體3之底部的抑制層24。較佳地，抑制層24包括至 ,、 且"電層之作用區域21丨之邊緣2ιιι在垂直 方向上句落在抑制層24之窗口 241内。將兩個抑制層分別安 置在介電體的頂部及底部以形成-「三明治」結構，從而 抑制X Y4度上的收縮。若安置於介電體之底部的抑制層不 ^有任何=，則可將其保留以作為陶竟產物的底部。另 -：面’若安置於介電體之底部的抑制層具有窗口，則藉 單匕少驟（例如，下文所述之單一化步驟）將其自陶究產 物移除。 、安置於彳電體之頂部或底部的抑制層之厚度（L3)與具有 或不具有任何抑制層的介電體之厚度⑹相關。若^之 比小於約3.5’則整體結構在χ_γ維度上的收縮率將小於約 〇.5%°介電體之總厚度⑹與安置於介電體之頂部或底部的 抑制層之厚度⑹之比（WL3)較佳小於約1〇。 在本發明之一較佳實施例中，整體結構2進-步包括覆蓋 層25及抑制層26。覆蓋層25係安置於抑制層22上，且抑制 層％安置於覆蓋層25上。覆蓋層係由介電材料或任何其它 適當材料組成。較佳地，抑制層26包括至少一窗口 261，且 97232.doc 1257923 介電層之作用區域211之邊緣2111在垂直方向上均落在抑 制層26之自口 261内。覆蓋層25及抑制層26保護介電體3使 其在燒製過程_免於接觸模具。可將覆蓋層25保存在陶竞 產物上，或可將其自陶竟產物移除。若將覆蓋層25保存在 陶究產物上’則可在其上安置用作表面黏著之主動組件或 模組的異貝材料圖案，例如異質材料組件及/或模組。 此外，整體結構2較佳包括覆蓋層27及抑制層以。覆蓋層 27係安置於具有或不具有抑制層以之介電體3的底部，且抑 制層28係安置於覆蓋層27之下方。抑制層較佳包括至少 一窗口281 ’且介電層之作用區域211之邊緣2111在垂直方 向上均洛在抑制層28之窗口 281内。覆蓋層27及抑制層聰 護介電體以使其在燒製過程中免於接觸模具。可將覆蓋層 27保存在陶£產物上，或可將其自陶$產物移除。 根據本發明，可按如下方式層壓介電層及抑制層以形成 整體結構··-抑制層（設置於介電體之頂部）_在介電體中交 替的m層介電層及_抑制層一抑制層(設置於介電體之底 部）。更佳使m層介電層及n層抑制層交替形成介電體。 在本發明之一較佳實施例中，將最短長度為[的抑制層打 孔以在其上形成至少-窗口（參見圖5)。該窗口可以任何形 狀存在於具有直徑c之外接圓中，相鄰外接圓之間的距離為 a’且最外窗口與抑制層之邊緣之間的距離為b，其中 c<〇.5L，a>G.le’ b>G.le。根據本發明，每—外接圓之直徑 均可不相Θ，其限制條件為1於暴露異質材料圖案的適 當位置之窗口係設置於介電層上。 97232.doc -12· 1257923 根據本叙明’介電體的介電層可藉由此項技術中已知之 2習知方式來製備，且其可由（例如）分散於可揮發性固態 ^ 片丨中的細碎陶瓷固體顆粒及可燒結之無機黏合劑 之混合物組成。在燒製過程中，在聚合黏合劑揮發後，介 電體之無機組份在加熱至一^夠高溫度時開始燒結。在燒 結過程中，顆粒狀多孔性介電體經歷結構變化，包括粒度 :大及孔隙形狀、大小與數目變化。燒結通常引起孔隙率 P牛低’且導致顆粒壓坯緻密化。 陶瓷固體粒 本勒明中所使用之介電體中的陶兗固體粒之組成可為任 可習知之組成。只要固體相對於系統中之其它材料呈化學 惰性，組成本身就不直接關鍵。陶竟固體粒之實例包括無 2金屬（通*為金屬氧化物）、高嫁點無機固體及高軟化點玻 。另外，可基^其介電性及熱膨脹性來選擇陶竟固體粒。 因此，可選擇該等材料之混合物以與其所施用之任何基材 的熱膨脹特徵相匹配。 無機黏合劑 根據本發明之無機黏合劑之組成可為任何習知之組成。 =相對於系統中的其它材料呈化學惰性，且其具有如下適 田的物里特/·生.（1)其燒結溫度適當地低於陶莞固體粒之燒 結溫度；且（2)其在所使料燒製溫度下經《滞流動燒結 機構或液態燒結機構。摘m仏 钱構適用於本發明之無機黏合劑通常為 破璃，具體而言為在燒製争結晶或非結晶性玻璃。 聚合黏合劑 97232.doc 1257923 、將無機黏合劑及陶竟固體粒分散於聚合黏合劑中。視情 況將聚合黏合劑盥1 曰 v 一八匕材枓化合，例如增塑劑、脫模劑、 分散劑、剝離劑及淵濕劑。此項技術中已知之用於製造陶 瓷的任何聚合黏合劑皆適用於本發明。 介電體 :可將任何習知介電體用於本發明。例如，介電體係由陶 竞固體粒、無機黏合劑及聚合黏合劑組成之介電層形成， 在該等介電層上之異質材料圖案已設置有金屬化通孔，該 等金屬化通孔延伸穿過介電層以互連各種異質材料圖案。 介電體通常包括玻璃、陶t系統及玻璃_陶_亮系統。 玻璃及陶瓷系統的主要組份為氧化鋁(Αία。。為了降低 氧化I呂的燒結溫度及維持整個系統的高頻率，通常添加玻 璃組份’其包括 κ2〇、B2〇3、Si〇2、Ca〇、Ba〇、Sr〇或 v2〇5 及其混合物。 璃陶兗系統的主要組份為—系列Mg_A1_si& Ct A⑷ 材料#為藉由加熱非晶系破璃所產生的陶兗晶體。 抑制層 抑制層係由任何可抑制介電體在燒結過程中收縮的材料 、成抑制層包括兩燒結溫度抑制層及低燒結溫度抑制 層〇 (1)高燒結溫度抑制層： 高燒結溫度抑制層包括Μ薄帶，例如氧键（在>140(rc 的溫度燒結）（參見圖6)。普通的低介電性低燒結溫度陶变在 約850°C燒結。在低燒結溫度陶:£開始燒結的溫度下，高燒 97232.doc -14- 1257923 結溫度抑制層沒有收縮，這是因為還沒有達到其更高的燒 結溫度。利用高燒結溫度抑制層未在約85〇。。於χ_γ維度上 收縮，以阻礙及抑制低燒結溫度陶竟的χ-γ維度收縮。二堯 結溫度抑制層可為（例如）美國專利第5,〇85,72〇號中的釋放 層，其包括分散於可揮發性有機介質中的細碎非金屬顆 粒。然而’當將釋放層用於本發明時，無需考慮無機黏合 劑的渗透及釋放層的接觸角，且亦無需在燒製後執行移除 步驟。美國專利第5，13〇,〇67號中的接觸薄板亦可用作本發 明之高燒結溫度抑制層，且其包含氧化銘、玻璃或非結晶 性玻璃/陶瓷的多孔性未加工薄板。 (2)低燒結溫度抑制層： 不同於（1)中所述的高燒結溫度抑制層，低燒結溫度抑制 層中♦加有強輔助組份以降低抑制層之燒結溫度（參見圖 7)。即，在低燒結溫度陶瓷開始燒結之前，低燒結溫度抑 制層已I凡成燒結。當低燒結溫度抑制層開始燒結時，其 X γ收縮叉到不會在此溫度範圍内收縮之低燒結溫度陶瓷 之阻礙及抑制。此時，（1)中所述的高燒結溫度抑制層之作 用由低燒結温度陶瓷來擔任。當溫度上升至低燒結溫度陶 究開始燒結的溫度時，低燒結溫度抑制層已經完成燒結且 不再收縮，從而阻礙及抑制低燒結溫度陶瓷在χ_γ維度上的 收縮例如，當將氧化鋁視為低燒結溫度抑制層時，強輔 助、、且伤可為氧化釩或其它組份，氧化釩的含量較佳為約1重 量％至約1〇重量％。 如則所述’除了將抑制層安置於介電體之頂部及底部 97232.doc -15- 1257923 外，亦可將其安置於介電層之間。因為抑制層在燒結過程 中不會收縮，所以藉由抑制層與介電層之間的黏合玻璃所 產生的黏合效應或藉由施加壓力，抑制層阻礙並抑制了介 電體及其中所含有的介電層之χ-γ維度上之收縮。 根據本發明之方法的步驟（b)為燒製整體結構。 根據本發明之方法，不論在燒製過程中是否施加了壓 力，皆可使用黏合玻璃，以幫助介電層與抑制層間的結合。 該領域中施加單向壓力於整體結構之暴露表面之習知方 法均適用於本發明。該壓力足以使抑制層接觸介電層，且 大體上導致所有的收 '縮皆發生在垂直於整體結構的z _方向 上。即在燒製過程中，介電層之χ_γ維度沒有發生收縮。 黏合玻璃應在不施加壓力的情況下使用。可將黏合玻璃 直接添加至抑制層及/或介電層之材料中，或其可為存在於 抑制層與介電層之間的黏合玻璃層形式。t將黏合玻璃直 接添加至抑制層之材料中時，其含量既不應過高以導致抑 制層在燒結過程中發生收縮，亦不應過低而不能提供足夠 之黏合效應。抑制層包括約i Wt%至約i 〇心之黏合玻璃， 且較佳為約i %至約6%。以在氧仙（Al2Q3)抑制層中添加爛 矽酸鹽玻璃為例，硼矽酸鹽玻璃的較佳含量為以硼矽酸鹽 玻璃及氧化！呂之總重量計W重量％至約1G重量％之間。當 將黏合玻璃施加至介電層之表面上時，黏合玻璃較佳心 蓋作用區域。黏合玻璃層之製備係、藉由將玻璃顆粒溶解於 適當溶劑中以作為油墨，且將其印刷在介電層或抑制層 上’或藉由直接塗覆、濺鍍沈積或氣相沈積將其添加至介 97232.doc _ 16 _ 1257923 電層與抑制層之間。此外，可在施加塵力的情況下使用黏 合玻璃（層）。可視過程需要來選擇不同的黏合破璃。 在本發明中，視情況將黏合玻璃添加至介電層與抑制層 之間以進行黏合。較佳將黏合玻璃添加至具有窗口的抑制 層之表面上’且接著將抑制層施加至介電層上，從而減少 黏合玻璃的用量且黏合玻璃不會直接與異f材料圖案接 觸。因此，黏合玻璃與介電層或抑制層之間的交互作用不 會直接發生於仙區域内。在燒結過程巾，部分黏合之玻 璃炼化並擴散至介電層中，以將抑制層與介電層黏合在一 起。 «本發明之方法可料製造具有或不具有預燒耐火基 板月襯之陶究電路。背襯可經金屬化或未經金屬化。在經 王屬化的it形下’其可預燒製或未預燒製。若使用基板背 :則將”電體置放於基板背襯上，然後置放抑制層。接 著，將整個組合體置放於抑制模具或壓模内以進行燒製。 右不使用基板月相見，則將抑制層置放於介電體之頂部及底 部。 、，據本發明之方法的步驟（c)為沿切割線單-化整體結構 、提ί、陶瓷，其中切割線設置於窗口邊緣與作用區域邊緣 矣門所化成的區域内。單一化方法已為熟習此領域者所熟 例如’藉由鑛、切割、雷射切割或分割來進行整體結 構之早一化。 根據本發明之方法較佳進一步包括步驟⑷：沿介電層之 用區域的邊緣單一化整體結構。若作為整體的複數個作 97232.doc 1257923 用區域213之邊緣均在垂直方向上落在窗口 221内，則藉此 單一化每一陶兗。 本發明具有許多優點：（1)因為抑制層之χ_γ維度上沒有 發生收縮，所以藉由黏合玻璃之存在或施加壓力而阻礙或 抑制了整體結構之收縮。(2)無需在燒製後移除抑制層，從 而完全避免在先前技術中由於移除多孔接觸薄板或釋放層 所導致的發生於介電層之表面上的破壞。藉由本發明之方 · 法所製造的陶瓷之表面非常光滑（表面粗糙度Κ<〇·2微 米）。所製造的電容器、電阻器或覆晶積體電路具有更精確 馨 的尺寸。藉此可避免移除的成本。（3 )抑制層之窗口可提供 在燒製整體結構時所產生的氣體之逸出路徑。（4)因為使用 抑制層將整體結構與模具隔離，所以防止了整體結構接觸 模具所導致的污染。⑺可藉由在介電體之介電層之間施加 具有窗口之抑制層來製造多達六層以上的多層陶瓷。可 將異質材料直接設置於待燒製之介電層上。 根據本發明所製造之陶瓷可塗覆/施加有鎳/錫層，且接著 將積體電路、多層陶瓷電路或電阻器SMD設置在其表面 _ 上。接著確定良率。 【實施方式】 ’ 、巧疋以下貫例僅為說明之目的，而不希望限制本發明之 範_。 實例1 將介電層之材料組份（ca_A1_si)或抑制層之材料組份（氧 化鋁及硼矽酸鹽玻璃）分別置於球磨桶中，添加水以將固體 97232.doc -18- 1257923 含量維持至約65重量％。將該等組份研磨至_.8微米之平 ^粒子大，。進一步添加聚乙稀醇(PVA)(其為有機黏合劑) I聚乙二醇（PEG)(其為增塑劑）以形成_衆液，藉由刮刀& 型機而形成具有80微米厚之介電層。用於製造扣:制層之方 法類似於介電層之製造方法。 曰The methods are disclosed in Business Machines C〇rporation, which is incorporated herein by reference. In U.S. Patent No. 5,085,720, the top and bottom of each of the ceramics have a release layer to form a "two Meiji" structure. During the dissolution and sintering process, a one-way pressure is applied to the surface of the release layer. The porosity is "the production of volatile slag provides a liberation of the layer 1 is that the release layer does not shrink during firing" so the χ γ shrinkage of the Tauman embryo is suppressed. However, the release layer covers (4) the top and bottom surfaces of the green embryo, And after sintering, it must be removed to print and fire conductors, resistors and electric grain on the ceramics. Therefore, the cost of the method is increased. In addition, the inorganic binder contained in the release layer is contained. The contact angle, viscosity, porosity and pore size of the infiltrated human embryo and the release layer will affect the flatness of the surface of the ceramics during the process of removing the release layer, and it is easy to make the circuit printing difficult and H. When manufacturing a large number of ceramic layers. At the time (for example, 6 or more layers), since the force distribution generated by applying the release layer to the top and bottom of 97232.doc 1257923 embryo is not balanced, the middle layer of the dielectric still receives (That is, the force on the top and bottom of the embryo is quite different from the force on the intermediate layer.) - US Patent No. 5J3M67 describes two ways to inhibit the χ-γ contraction of the dielectric. Applying a binding force to the 4 edges of the dielectric to provide an open escape path for the volatiles and an oxygen entry path. For the second approach, by using a coextensive porous plate or by using a A force is applied to the entire surface of the dielectric to apply a co-expansion force to the surface. In the third approach, friction is applied by using a porous contact sheet that does not shrink or expand during firing. On the end of the embryo. The connection = thin plate including the porous composition 'has the porosity to maintain porosity when fired. To the ceramic _L, heat stable and has continuous mechanical integrity / rigidity, etc., is selected as the porous Sexual composition. Contact the sheet size, and thus limit the shrinkage of the ceramic part. After sintering, the appropriate removal procedure (such as 'polishing and scraping) of the surface of the ceramic is removed to remove the contact. However, the above three approaches have drawbacks. For example, because the first type of control uses the weight generated by the fixture to suppress shrinkage and the force distribution on the dielectric is uneven, it is easy to cause the shape of the circuit and the flatness of the surface. The second and third types of I; the removal step after firing, the cost increases, and the surface is also damaged. In order to solve the above problems, the present invention proposes a new Gu Gu Tu, which is used in the process of knotting, and the quality of the city. 11 Method 'Large cost and improve ceramic products 【Inventive content】 97232.doc 1257923 概述明 Overview The present invention is mainly concerned with the use of a kind to suppress the recovery of Tao in the sintering process ': = :, The method includes the following steps: U) providing a unitary structure including: a dielectric body including at least a dielectric layer, wherein Material = less - for the dragon domain, the towel region is provided with at least - a heterogeneous material mold case and the heterogeneous material pattern comprises at least one heterogeneous material component and / or - the female is placed on the top of the dielectric body The suppression layer includes at least one of: wherein the edge of the active region of the dielectric layer is in the vertical direction of the 5th opening; (the firing of the integral structure; and (c) the single-cut along the cutting line The overall structure provides such a ceramic, wherein the = secant is disposed in a region formed between the edge of the window and the edge of the active region. DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for suppressing shrinkage during sintering, which Preferably the method is applied by The multilayer conductive circuit is fabricated by a conventional conductive metal, a resistor, an electric grid ☆ conductor, an inductor, a wafer or a module, and is applied during its manufacture. The method according to the invention has the following advantages: inhibits sintering The χ·γ dimension shrinks in the process, and avoids removing the suppression layer after firing to prevent possible damage to the surface flatness. Referring to Figure 1, the ceramic according to the present invention includes a dielectric portion (10) heterogeneous material 97232.doc 1257923 2 Part 12. Dielectric portion 11 includes a plurality of dielectric layers disposed on heterogeneous material portions 12 (eg, resistors, capacitors, conductors, inductors, wafers, or modules) on the plurality of second electrical layers Metallized vias extending through the dielectric to interconnect the various heterogeneous materials on the different dielectric layers, or the material σ, 12 including surface mount active components or modules 121, The through hole 122 and the embedded component or module 123. The surface active component or module disposed on the surface of the outermost dielectric layer can be fabricated on the dielectric layer after firing the dielectric layer, or Co-firing with the dielectric layer. Through hole 1 22 is passed through the dielectric portion 11 to interconnect the conductive paths of the heterogeneous material portion 12. The dielectric is perforated and filled with a conductive material, typically silver, to provide vias 122. Embedding the embedded component or module 123 In the dielectric layer, and interconnected on different layers by vias 122. By comprising a plurality of layers, the heterogeneous material interconnects can be disposed on the 'electrical layer and/or the dielectric layer. The heterogeneous material is disposed in three dimensions such that the heterogeneous material interconnects within the dielectric layer minimize the area required to accommodate the circuit. The steps of the method according to the present invention provide an integral comprising dielectric 3 and suppression layer 22. Structure 2 (see Figures 2 to 4). Referring to Figures 2 and 4, the dielectric body 3 includes at least one dielectric layer 21. The dielectric layer 21 includes at least one active region 211, and the active region 211 is provided with at least one different The shell material pattern 212, and the heterogeneous material pattern 212 includes at least one heterogeneous material component and/or module 2121. After firing, the dielectric layer constitutes a dielectric portion of the ceramic, and the pattern of the foreign material constitutes a portion of the heterogeneous material of the ceramic. The heterogeneous material component and/or module 2121 in accordance with the present invention includes a resistor, capacitor, conductor, inductor, wafer or module to form a pattern of heterogeneous material 212. In a preferred embodiment of the present invention, 97232.doc 1257923, each of the electrical layers includes a plurality of active regions 211, and the parent-acting regions 211 are both made of tantalum and are used to fabricate a ceramic. As shown in Fig. 2 and Fig. 3, 22 spoons of Zhao 丨, ( (3) 22 women are placed above the dielectric body 3. The suppression layer 2 2 includes at least one window λ Α ± ^ ^ , '丨The edge 2111 of the active area 211 falls in the vertical direction of the window ^ pattern 212. In the four ports 221, the heterogeneous material exposing the dielectric layer is used in one embodiment of the present invention to act as a The edge of the + τ action & field 211 is "inside" (not shown) of the suppression layer in the vertical direction t. In the other embodiment of the present invention, the edges of the plurality of active regions 213 are all-integrated within the solidified portion of the suppression layer, such as window 221 (shown in Figure 4). In a preferred embodiment of the invention, dielectric 3 includes at least two dielectric layers. The edge 2111 of the active region 211 of any of the dielectric layers falls within the window 221 of the suppression layer 22 in the vertical direction. When at least two dielectric layers are provided, the < method according to the present invention has the ability to produce a multilayer ceramic. The heterogeneous material pattern of each dielectric layer forms part of the circuit and interconnects the heterogeneous material pattern of the other dielectric layers through the vias to form a complete circuit. In another preferred embodiment of the present invention, the dielectric body 3 further includes a suppression layer 23 disposed between the η electrical layers. The suppression layer 23 includes at least one window 23 1, and the edge 2111 of the active region of each dielectric layer also falls within the window 23 1 of the suppression layer 23 in the vertical direction. The window 23 1 of the suppression layer 23 may be larger or smaller than the window 221 of the suppression layer 22. Preferably, the size and position of the window 23 1 of the suppression layer 23 in the dielectric body 3 are the same as the size and position of the window 221 of the suppression layer 22 disposed above the dielectric body 3. By applying the suppression layer 23 in the dielectric body 3, the method according to the invention can be used to fabricate a multilayer 97232.doc -10- 1257923 ceramic having more than six dielectric layers, and which still avoids defects during sintering. - Shrinkage in the gamma dimension. The thickness (Li) of the suppression layer applied between the 'Electrical Body' is preferably no more than the thickness of the 1st material pattern disposed on the dielectric layer disposed under the suppression layer in the phase 4 (6) Thin, and more preferably, L1 is equal to L2 (Ll = L2) to enhance the uniformity of the overall structure. In another preferred embodiment of the invention, the unitary structure 2 further comprises a suppression layer 24 at the bottom of the electrical body 3. Preferably, the suppression layer 24 includes to, and the edge 2 ι of the active layer 21 of the electrical layer falls within the window 241 of the suppression layer 24 in the vertical direction. The two suppression layers are respectively placed on the top and bottom of the dielectric to form a "sandwich" structure, thereby suppressing shrinkage at X Y4. If the suppression layer disposed at the bottom of the dielectric body does not have any =, it may be retained as the bottom of the ceramic product. Another -: face' If the suppression layer disposed at the bottom of the dielectric body has a window, it is removed from the ceramic product by a single step (e.g., the singulation step described below). The thickness (L3) of the suppression layer disposed on the top or bottom of the tantalum electrode is related to the thickness (6) of the dielectric body with or without any suppression layer. If the ratio of ^ is less than about 3.5', the shrinkage of the overall structure in the χ_γ dimension will be less than about 〇.5% of the total thickness of the dielectric (6) and the thickness of the suppression layer (6) disposed at the top or bottom of the dielectric. The ratio (WL3) is preferably less than about 1 Torr. In a preferred embodiment of the invention, the unitary structure 2 further includes a cover layer 25 and a suppression layer 26. The cover layer 25 is disposed on the suppression layer 22, and the suppression layer is disposed on the cover layer 25. The cover layer is composed of a dielectric material or any other suitable material. Preferably, the suppression layer 26 includes at least one window 261, and the edge 2111 of the active region 211 of the dielectric layer of 97232.doc 1257923 falls vertically within the self-port 261 of the suppression layer 26. The cover layer 25 and the suppression layer 26 protect the dielectric body 3 from being exposed to the mold during the firing process. The cover layer 25 can be stored on the pottery product or it can be removed from the pottery product. If the cover layer 25 is deposited on the ceramic article, then a pattern of different shell materials, such as a heterogeneous material component and/or module, can be placed thereon as an active component or module for surface adhesion. Further, the unitary structure 2 preferably includes a cover layer 27 and a suppression layer. The cover layer 27 is disposed on the bottom of the dielectric body 3 with or without the suppression layer, and the suppression layer 28 is disposed below the cover layer 27. The suppression layer preferably includes at least one window 281' and the edge 2111 of the active region 211 of the dielectric layer is in the vertical direction within the window 281 of the suppression layer 28. The cover layer 27 and the suppression layer are shielded from the dielectric body to protect it from contact with the mold during the firing process. The cover layer 27 can be stored on the pottery product or it can be removed from the pottery product. According to the present invention, the dielectric layer and the suppression layer can be laminated in such a manner as to form a monolithic structure, the suppression layer (provided on the top of the dielectric), the m-layer dielectric layer and the _ suppression in the dielectric body. A layer-inhibiting layer (disposed on the bottom of the dielectric). More preferably, the m-layer dielectric layer and the n-layer suppression layer are alternately formed into a dielectric body. In a preferred embodiment of the invention, the suppression layer of the shortest length is [perforated to form at least a window thereon (see Figure 5). The window may exist in any shape having a diameter c outside the circle, the distance between adjacent circumscribed circles is a' and the distance between the outermost window and the edge of the suppression layer is b, where c < 〇.5L, a> ;G.le' b>G.le. In accordance with the present invention, the diameter of each of the circumscribed circles may be non-contradictory, with a constraint that the window of the appropriate location for exposing the pattern of the heterogeneous material is disposed on the dielectric layer. 97232.doc -12· 1257923 According to the present description, a dielectric layer of a dielectric can be prepared by a conventional method known in the art, and can be, for example, dispersed in a volatile solid state sheet. It consists of a mixture of finely divided ceramic solid particles and a sinterable inorganic binder. During the firing process, after the polymeric binder is volatilized, the inorganic component of the dielectric begins to sinter when heated to a temperature high enough. During the sintering process, the particulate porous dielectric undergoes structural changes including particle size: large and pore shape, size and number. Sintering generally causes a porosity P cow low and results in densification of the particle compact. Ceramic Solid Particles The composition of the ceramic slab solid particles in the dielectric used in the present invention may be any conventional composition. As long as the solid is chemically inert with respect to other materials in the system, the composition itself is not directly critical. Examples of ceramic solid particles include no metal (pass* is a metal oxide), high-margin inorganic solids, and high softening point glass. In addition, the ceramic solid particles can be selected based on their dielectric properties and thermal expansion properties. Thus, a mixture of such materials can be selected to match the thermal expansion characteristics of any of the substrates to which they are applied. Inorganic Binder The composition of the inorganic binder according to the present invention may be any conventional composition. = chemically inert with respect to other materials in the system, and which has the following suitable properties: (1) the sintering temperature is suitably lower than the sintering temperature of the ceramic solid particles; and (2) The material is fired at a temperature through a "stagnation flow sintering mechanism or a liquid sintering mechanism. The inorganic binder suitable for use in the present invention is usually a glass, specifically a crystallization or amorphous glass. Polymeric adhesive 97232.doc 1257923, the inorganic binder and the ceramic solid particles are dispersed in the polymeric binder. Polymeric binders, such as plasticizers, mold release agents, dispersants, release agents and agglomerates, may be combined, as the case may be. Any polymeric binder known in the art for making ceramics is suitable for use in the present invention. Dielectric: Any conventional dielectric can be used in the present invention. For example, the dielectric system is formed of a dielectric layer composed of Tao Jing solid particles, an inorganic binder, and a polymeric binder, and the heterogeneous material pattern on the dielectric layers has been provided with metalized through holes, and the metalized through holes Extending through the dielectric layer to interconnect various patterns of heterogeneous materials. Dielectrics typically include glass, ceramic systems, and glass-ceramic-bright systems. The main component of the glass and ceramic system is alumina (Αία. In order to reduce the sintering temperature of the oxidized Ilu and maintain the high frequency of the whole system, a glass component is usually added, which includes κ2〇, B2〇3, Si〇2. Ca〇, Ba〇, Sr〇 or v2〇5 and mixtures thereof. The main component of the glass pottery system is—Series Mg_A1_si& Ct A(4) Material # is a ceramic crystal produced by heating amorphous glass. The layer suppression layer is composed of any material capable of suppressing shrinkage of the dielectric during sintering, and the suppression layer includes two sintering temperature suppression layers and a low sintering temperature suppression layer 〇 (1) high sintering temperature suppression layer: the high sintering temperature suppression layer includes Tantalum ribbons, such as oxygen bonds (in > 140 (temperature sintering of rc) (see Figure 6). Ordinary low dielectric low sintering temperature ceramics sintered at about 850 ° C. At low sintering temperatures Tao: £ start At the sintering temperature, the high temperature 97232.doc -14-1257923 junction temperature suppression layer does not shrink because the higher sintering temperature has not been reached. The high sintering temperature suppression layer is not about 85 Å. In the χ γ dimension Shrink to hinder The 烧结-γ dimension shrinkage of the low sintering temperature is achieved. The enthalpy junction temperature suppression layer can be, for example, a release layer in U.S. Patent No. 5, 〇85,72, which is dispersed in a volatile organic medium. Finely divided non-metallic particles. However, when the release layer is used in the present invention, it is not necessary to consider the penetration of the inorganic binder and the contact angle of the release layer, and it is not necessary to perform the removal step after firing. U.S. Patent No. 5,13 The contact sheet in 〇, No. 67 can also be used as the high sintering temperature suppression layer of the present invention, and it comprises a porous unprocessed sheet of oxidized, glass or amorphous glass/ceramic. (2) Low sintering temperature suppression Layer: Unlike the high sintering temperature suppression layer described in (1), a strong auxiliary component is added to the low sintering temperature suppression layer to lower the sintering temperature of the suppression layer (see Fig. 7). That is, the ceramic at a low sintering temperature. Before the sintering starts, the low sintering temperature suppressing layer has been sintered. When the low sintering temperature suppressing layer starts to be sintered, its X γ shrinks the fork to the hindrance and inhibition of the low sintering temperature ceramic which does not shrink in this temperature range. Time,( The action of the high sintering temperature suppression layer described in 1) is performed by a low sintering temperature ceramic. When the temperature rises to a temperature at which the sintering temperature starts to be sintered, the low sintering temperature suppression layer has been sintered and no longer shrinks, thereby Obstructing and suppressing the shrinkage of the low sintering temperature ceramic in the χ_γ dimension. For example, when alumina is regarded as a low sintering temperature suppression layer, strong assist, and the damage may be vanadium oxide or other components, and the content of vanadium oxide is preferably From about 1% by weight to about 1% by weight. If the 'repression layer is placed on the top and bottom of the dielectric body 97232.doc -15-1257923, it can also be placed between the dielectric layers. Since the suppression layer does not shrink during sintering, the adhesion layer is inhibited by the adhesion of the adhesion layer between the layer and the dielectric layer or by applying pressure, the inhibition layer inhibits and inhibits the dielectric and the contents thereof. The shrinkage of the dielectric layer in the γ-γ dimension. Step (b) of the method according to the invention is to fire the monolithic structure. In accordance with the method of the present invention, an adhesive glass can be used to assist in the bonding between the dielectric layer and the suppression layer, whether or not pressure is applied during the firing process. Conventional methods of applying unidirectional pressure to the exposed surface of the unitary structure in the art are suitable for use in the present invention. This pressure is sufficient to cause the suppression layer to contact the dielectric layer and generally causes all of the shrinkage to occur in the z-direction perpendicular to the overall structure. That is, during the firing process, the χγ dimension of the dielectric layer does not shrink. Adhesive glass should be used without applying pressure. The bonded glass may be directly added to the material of the suppression layer and/or the dielectric layer, or it may be in the form of an adhesive glass layer existing between the suppression layer and the dielectric layer. t When the bonded glass is directly added to the material of the suppressing layer, the content thereof should not be too high to cause the inhibiting layer to shrink during the sintering process, nor should it be too low to provide a sufficient bonding effect. The inhibiting layer comprises from about i Wt% to about i-bonded glass, and preferably from about i% to about 6%. For example, adding strontium silicate glass to the oxygen dioxide (Al2Q3) suppression layer, the preferred content of borosilicate glass is borosilicate glass and oxidation! The total weight of Lu is between W% by weight and about 1% by weight. When the bonded glass is applied to the surface of the dielectric layer, the bonded glass preferably has a capping area. The adhesive glass layer is prepared by dissolving the glass particles in an appropriate solvent as an ink and printing it on the dielectric layer or the suppression layer' or by direct coating, sputter deposition or vapor deposition. Added to the 97232.doc _ 16 _ 1257923 between the electrical layer and the suppression layer. In addition, the adhesive glass (layer) can be used under the application of dust. The visual process needs to choose different bonding and breaking glass. In the present invention, an adhesive glass is optionally added between the dielectric layer and the suppression layer for bonding. Preferably, the bonded glass is added to the surface of the suppressing layer having the window' and then the inhibiting layer is applied to the dielectric layer to reduce the amount of bonded glass and the bonded glass does not directly contact the pattern of the different f material. Therefore, the interaction between the bonded glass and the dielectric or inhibiting layer does not occur directly in the fairy region. In the sintering process, the partially bonded glass is refining and diffusing into the dielectric layer to bond the suppression layer to the dielectric layer. The method of the present invention is capable of producing a ceramic circuit with or without a pre-fired refractory substrate. The backing may be metallized or unmetallized. It may be pre-fired or not pre-fired under the genus of the king. If the back of the substrate is used: the "electric body is placed on the substrate backing, and then the suppression layer is placed. Then, the entire assembly is placed in a suppression mold or a stamper for firing. See, the suppressing layer is placed on the top and bottom of the dielectric body. According to the method (c) of the method of the present invention, the monolithic structure, the ceramic, and the ceramic are cut along the cutting line, wherein the cutting line is disposed on the window. The area formed by the edge and the edge of the active area. The singulation method has been cooked for the prior art, for example, by mineral, cutting, laser cutting or segmentation. Preferably, the method further comprises the step (4) of singulating the overall structure along the edge of the region of the dielectric layer. If the plurality of edges of the region 213 as a whole are 97232.doc 1257923, the edges of the region 213 fall vertically within the window 221, then In this way, each of the ceramics is singulated. The present invention has many advantages: (1) because the shrinkage layer has no shrinkage in the χγ-dimensional dimension, the whole is hindered or suppressed by the presence or pressure of the bonded glass. Shrinkage of the structure. (2) It is not necessary to remove the suppression layer after firing, thereby completely avoiding the damage occurring on the surface of the dielectric layer caused by the removal of the porous contact sheet or the release layer in the prior art. The surface of the ceramic made by the method is very smooth (surface roughness Κ < 〇 2 μm). The fabricated capacitor, resistor or flip chip circuit has a more precise size, thereby avoiding removal. The cost of the (3) suppression layer window can provide the escape path of the gas generated when the whole structure is fired. (4) Since the suppression structure is used to isolate the overall structure from the mold, the overall structure is prevented from contacting the mold. (7) It is possible to manufacture up to six or more layers of ceramic by applying a window-inhibiting layer between dielectric layers of a dielectric. The heterogeneous material can be directly disposed on the dielectric layer to be fired. The ceramic manufactured according to the present invention may be coated/applied with a nickel/tin layer, and then an integrated circuit, a multilayer ceramic circuit or a resistor SMD is placed on its surface _. Next, the yield is determined. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention. Example 1 The material component of the dielectric layer (ca_A1_si) or the material component of the suppression layer (alumina and boron) The tellurite glass was placed in a ball mill barrel separately, and water was added to maintain the solid content of 97232.doc -18-1257923 to about 65% by weight. The components were ground to a size of _.8 micrometers. Further adding polyethylene glycol (PVA) (which is an organic binder) I polyethylene glycol (PEG), which is a plasticizer, to form a liquid, formed by a doctor blade and a machine having a thickness of 80 μm Dielectric layer. The method used to make the buckle: the layer is similar to the method of manufacturing the dielectric layer.
每一介電層⑽公分χ1〇公分）均包括Μ個面積&公分X 1 :分之，用區域，且每-作用區域之間的距離為〇.65公 ^最外作龍域與介電層之邊緣之間的距離為2公 分。每一作用區域均設置有異質材料圖案。 形成窗口。每 口之間的距離 間的距離為1.2 藉由直接將抑制層（10公分Χίο公分）打孔而 一窗口均具有1公分χ1公分之面積，且每一窗 為〇·65公分，且最外窗口與抑制層之邊緣之 公分。 按如下方式排序及層壓介電層及抑制層：一抑制層（安置 於’I電體之頂部多層介電層_一抑制層（安置於介電體之 底部）。抑制層之厚度為L3,且介電體之總厚度為L4。 此貫例中所使用的燒製條件為約300°C下燒製約24至約 38小時以移除有機黏合劑，且接著在約880°C下燒製約30分 鐘。接著，將樣品冷卻並依照所印刷之電路直接切割。 里測整體結構在不同的L3及乙4值下的χ-γ維度收縮率並 將其列在表1中： 97232.doc -19- 1257923 表1 L4/L3 ^YrniWi%) 0.0 0.1 3.1 4.4 0.8 4.8 Γο^ 6.4 1.4 6.6 1.6 11.0 3.8 燒製後，沿窗口之邊緣單一化陶瓷。 表1顯示：當WL3之比小於3.m，整體結構在χ_γ維度上 的收縮率小於約0.5%。 實例2 ® 根據類似於實m中所述的方法來製造具有約3〇〇微米厚 度之介電體與具有約145微米#度及約1〇微米厚度之抑制 層。將145微米抑制層安置於介電體之頂部及底部，且職 米抑制層係用於安置在介電體之介電層之間。 每一介電層（10公分x10公分）均包括25個面積公分χΐ 、刀的作用區支或’且每一作用區域之間的距離為公 t^最外作用區域與介電層之邊緣之間的距離為公 鲁 刀母作用區域均設置有一異質材料圖案。 ^由直接將抑制層（10公分xl0公分）打孔而形成窗口。每‘ 一窗口均具有1公分xl公分之面積，且每一窗口之間的距離· 為65 A刀，且最外窗口與抑制層之邊緣之間的距離為i ·2 公分。 下方式層壓介電層及抑制層以形成整體結構··一抑 制層(145¼米’其係安置於介電體之頂部)_5層介電層及m 97232.doc -20- 1257923 層10 m抑制層，其中介電層與抑制層交替互疊-一抑制層 (145U米，其係安置於介電體之底部）。 *測該整體結構在不同m值下的X-Y維纟收縮帛，並將其 列於表2中： ^ 表2 X-Y收縮率(％) 1.84 _ 1 1.77 Γ 1.69 表2顯不：安置於介電體内之抑制層（10微米）可將整體結 構在X Υ、、隹度上的收縮率由降低至1.69。义。 實例3 除了抑制層包括…/。之硼矽 、、 #敗®敬哨外，根據糊似於貫例 斤述的方法來製造具有約_微米厚度之介電體及且 約250微米厚度之抑制層。該等抑制層係用 電 上以作為帛一及第三抑制層。 ；丨電體 ^等介電層⑽公分心公分）包括25個面積…公分 八" 母作用£域之間的距離均為〇_65公 二取：作用區域與介電層之邊緣之間的距離為 刀。母-作用區域均設置有一異質材料圖案。 一：由㈣抑制層(1。公分，公分)打孔而形成窗口。每 囪口均具有1公分XI公分之面積，且一办 均為0·65公分，且最外窗盘固口之間的距離 u公分。取外固與抑制層之邊緣之間的距離為 量測該整體結構在不同η值下的χ_γ維度收縮率，並將其 97232.doc -21 - 1257923 列於表3中： η Χ-Υ收縮率(％) — 0 0.68 — 2 0.28 4 0.36 6 0.48 表3顯示：添加硼矽酸鹽玻璃可有效抑制χ_γ維度收縮率。 儘管已說明及描述了本發明之實施例，但是熟習此項技 術者仍可進行各種修正及改良。因此，所描述之本發明之 實施例僅為說明而無限定意義。吾人希望並未將本發明限 制於所說明之特定形式，且希望所有未脫離本發明之精神 及範缚的修正皆處於隨附申請專利範圍所界定的範_内。 【圖式簡單說明】 圖1展示陶瓷之分解透視圖； 圖2展示根據本發明之一實施例的整體結構之分解透視 圖， 圖3展示根據本發明之一實施例的整體結構之截面圖； 圖4展示根據本發明之一實施例的整體結構之俯視圖； 圖5展不根據本發明之一實施例的抑制層之俯視圖，其中 L為忒抑制層之最短長度，。為每一窗口之外接圓的直徑，& 為相鄰外接圓之間的距離，且b為最外側窗口與該抑制層之 邊緣之間的距離； 、.圖6展示高燒結溫度抑制層及低燒結溫度陶竟之溫度相 對於收縮率的曲線圖； 圖7展不低燒結溫度抑制層及低燒結溫度陶瓷之溫度相 97232.doc -22- 1257923 對於收縮率的曲線圖。 【主要元件符號說明】 1 陶瓷 2 整體結構 3 介電體 11 介電部分 12 異質材料部分 21 介電層 22 、 23 、 24 、 26 、 28 抑制層 25 > 27 覆蓋層 121 表面黏著之主動組件或模組 122 通孔 123 敗入式組件或模組 211 、 213 作用區域 212 異質材料圖案 221 、 231 、 241 、 窗口 26卜 281 2111 作用區域之邊緣 2121 異質材料組件及/或模組 97232.doc -23-Each dielectric layer (10) centimeters χ1〇 cm) includes an area & centimeter X 1 : divided into regions, and the distance between each - active region is 〇.65 gong ^ the most external dragon domain and media The distance between the edges of the electrical layer is 2 cm. Each active area is provided with a pattern of heterogeneous material. Form a window. The distance between each mouth is 1.2. By directly punching the suppression layer (10 cm Χίο cm), one window has an area of 1 cm χ 1 cm, and each window is 〇·65 cm, and the outermost The cent of the window and the edge of the suppression layer. The dielectric layer and the suppression layer are ordered and laminated as follows: a suppression layer (disposed on the top dielectric layer of the 'I electrical body - a suppression layer (disposed at the bottom of the dielectric body). The thickness of the suppression layer is L3 And the total thickness of the dielectric body is L4. The firing conditions used in this example are about 300 ° C for 24 to about 38 hours to remove the organic binder, and then at about 880 ° C. The burn was constrained for 30 minutes. Next, the sample was cooled and cut directly according to the printed circuit. The χ-γ dimensional shrinkage of the overall structure at different L3 and B values was measured and listed in Table 1: 97232 .doc -19- 1257923 Table 1 L4/L3 ^YrniWi%) 0.0 0.1 3.1 4.4 0.8 4.8 Γο^ 6.4 1.4 6.6 1.6 11.0 3.8 After firing, singulate the ceramic along the edge of the window. Table 1 shows that when the ratio of WL3 is less than 3. m, the shrinkage of the overall structure in the χ_γ dimension is less than about 0.5%. Example 2 ® A dielectric having a thickness of about 3 Å and a suppression layer having a thickness of about 145 μm and a thickness of about 1 μm were produced according to a method similar to that described in the real m. A 145 micron suppression layer is disposed on the top and bottom of the dielectric body, and a barrier layer is disposed between the dielectric layers of the dielectric. Each dielectric layer (10 cm x 10 cm) includes 25 area centimeters, the active area of the knife or 'and the distance between each active area is the outermost active area and the edge of the dielectric layer. The distance between the two is set to a heterogeneous material pattern in the active area of the male knives. ^ A window is formed by directly punching the suppression layer (10 cm x 10 cm). Each 'one window has an area of 1 cm x 1 cm, and the distance between each window is 65 A, and the distance between the outermost window and the edge of the suppression layer is i · 2 cm. The dielectric layer and the suppression layer are laminated in the following manner to form a monolithic structure. A suppression layer (1451⁄4 m' is placed on top of the dielectric body)_5 dielectric layer and m 97232.doc -20- 1257923 layer 10 m The suppression layer, wherein the dielectric layer and the suppression layer alternately overlap each other - a suppression layer (145 U meters, which is disposed at the bottom of the dielectric). * Measure the XY dimensional shrinkage 该 of the overall structure at different values of m and list it in Table 2: ^ Table 2 XY shrinkage (%) 1.84 _ 1 1.77 Γ 1.69 Table 2 shows: Placed in dielectric The inhibitory layer (10 micron) in the body reduces the shrinkage of the overall structure on X Υ and 隹 to 1.69. Righteousness. Example 3 except that the suppression layer included .../. In addition to the boron bismuth, and the annihilation of the whistle, a dielectric layer having a thickness of about _micron and a suppression layer having a thickness of about 250 μm were produced according to the method of paste. The suppression layers are electrically used as the first and third suppression layers.丨Electrical body ^ etc. Dielectric layer (10) cm centimeters) including 25 areas ... cm 8 " The distance between the mother and the field is 〇 _65 取 2: between the active area and the edge of the dielectric layer The distance is the knife. The mother-acting regions are each provided with a pattern of a heterogeneous material. One: A window is formed by punching holes in (4) suppression layers (1 cm, cm). Each chimney has an area of 1 cm XI cm, and each one is 0·65 cm, and the distance between the outermost window discs is u cm. The distance between the outer solid and the edge of the suppression layer is measured by measuring the χ_γ dimensional shrinkage of the overall structure at different η values, and its 97232.doc -21 - 1257923 is listed in Table 3: η Χ-Υ shrinkage Rate (%) — 0 0.68 — 2 0.28 4 0.36 6 0.48 Table 3 shows that the addition of borosilicate glass can effectively suppress the shrinkage of the χγγ dimension. While the embodiments of the invention have been illustrated and described, it will be understood that Therefore, the described embodiments of the invention are merely illustrative and not limiting. The invention is not intended to be limited to the specific forms disclosed, and it is intended that all modifications that come within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows an exploded perspective view of a ceramic; Figure 2 shows an exploded perspective view of the overall structure in accordance with one embodiment of the present invention, and Figure 3 shows a cross-sectional view of the overall structure in accordance with one embodiment of the present invention; 4 shows a top view of an overall structure in accordance with an embodiment of the present invention; and FIG. 5 shows a top view of a suppression layer in accordance with an embodiment of the present invention, where L is the shortest length of the antimony suppression layer. For each window, the diameter of the circle is & is the distance between adjacent circumscribed circles, and b is the distance between the outermost window and the edge of the suppression layer; Figure 6 shows the high sintering temperature suppression layer and The graph of the temperature of the low sintering temperature of the ceramics versus the shrinkage rate; Figure 7 shows the temperature of the sintering temperature suppression layer and the low sintering temperature ceramic phase 97232.doc -22-1257923 for the shrinkage rate. [Main component symbol description] 1 Ceramic 2 Overall structure 3 Dielectric body 11 Dielectric portion 12 Heterogeneous material portion 21 Dielectric layer 22, 23, 24, 26, 28 Suppressive layer 25 > 27 Active layer on surface of cap layer 121 Or module 122 through hole 123 defeated component or module 211, 213 active area 212 heterogeneous material pattern 221, 231, 241, window 26 281 2111 edge of the active area 2121 heterogeneous material component and / or module 97232.doc -twenty three-