1257752 玖、發明說明： 【發明所屬之技術領域】 本發明有關驅動電路（driver circuit)，尤有關於一種具 有平行（parallel)驅動架構的驅動電路。 【先前技術】 第1圖係一習知的雷射二極體（laser diode，LD)驅動電 路。參考第1圖，於1998年，Lucent (美國專利文獻弟 6,021，143號）揭露一種雷射二極體的驅動電路1〇〇，包含 至少一增益級（gain stage)l 10與一輸出級120。增益級11〇 包含二個電阻113、114、一對差動放大器（differential amplifier)lll 以及一電流源 ii2(current source)。輸出級 120包含一電阻124、一對差動放大器121、一雷射二極體 123以及一電流源122。特別的是，該增益級110的增益 與供應至雷射二極體123的驅動電流有關聯性。所以，由 於該增益級110與輸出級120的電流源112、122共同受控 制’因此’從增益級11 〇的增益便可以追縱到驅動電流的 大小。也就是，在需要相對低電流的環境，增益（或差動電 壓VDIFF)會相對較低以防止過度驅動輸出級。另一方面， §需要相對高電流的環境，能提高增益以提供足夠的差動 電壓Vdiff去驅動輸出級。 然而’隨著深次微米製程（deepsub-micr〇npr〇cess)的 發展，晶片的工作電壓越來越低。對差動電壓VDKF的控 制有可能造成電流源122在線性區工作。另外，增益級i 1〇 要驅動輸出級120時，可以利用調整電流源丨12與調整提 升電阻（pull-up resistor)li3、114的阻值大小來達成目的。 1257752 表示電流源112 π 3、11 4的阻值 一般而言，當差動電壓Vdiff越來越大時 的電流也越來越大，但仍須配合調整電阻 大小來控制差動電壓VDIFF。 【發明内容】 有鐾於上述問題，本發明之目的為提供 驅動架構的驅動電路，藉由平行驅動架構， 需求，產生大小差距有數倍之多的驅動電流 一種具有平行 並依據使用者 為達成上述目的，本發明之具有平行驅動架構的驅動 電路’由多數組彼此並聯的驅動器所組成來產生一第 出電流與-第二輸出電流。每一組驅動器包含一開關、： 控制電塵產生單元與一驅動單元。每一開關係接收一開關 控制l°控制電壓產生單元係經由前述開關連接於一電 c源並接&對差動信號後產生—組輸出電壓。驅動翠 元係接收前述控制電壓產生單元所輸出之輸出㈣，並根 據該輸出電壓在第一輸出端產生一第一驅動電流，以及在 第二輸出端產生一第二驅動電流。其中，每一組驅動器之 驅動單元之前述第—輸出端互相連接藉以產生前述第一 輸出電流，且每 '一 ija 11¾ 3S JU, ^ 、、且驅動為之驅動單元之前述第二輸出端 互相連接藉以產生前述第二輸出電流。 由於目前深次微米製程的快速發展，晶片的工作電壓 越來越低’若驅動負载之電流量大小差距10肖以上，一 般習知的驅動電路即絲達到要求。本發明之具有平行驅 動架構的驅動電路，利用簡單的硬體配置，即可達到電流 1257752 量言段變的目的。，同時，本發明亦呈古丁以 〜 才尽敛明亦具有不增加電路佈局面積 與省電的優點。 兹配合下列圖示、實施例之詳細說明及中請專利範 圍，將上述及本發明之其他目的與優點詳述於後。 【實施方式】 第2圖係本發明之具有平行驅動架構的驅動電路的架 構方塊圖。參考第2圖，具有平行驅動架構的驅動電路2〇〇 係由N(N為大於1的正整數）組彼此並聯的驅動器所組 成，每一組驅動器又包含一控制級2〇n與一驅動級21n (Ηκλγ，n為正整數）。控制級2〇n接收一組差動信號後產 生一組輸出電壓，且每個控制級20η之電源均由一單獨之 開關y2η控制。驅動級21 η接收相對應之控制級的輸 出電壓’並分別於第一、第二輸出端輸出第一、第二驅動 $流。每個驅動級21η之第一輸出端互相連接且第二輸出 端互相連接，用以產生-第-輸出電流1丨與-第二輸出電 流12 ’藉以驅動負載251、252。 第3圖係本發明之第一實施例的電路圖。以下詳細說 明此電路結構。 ° ^ ° ^如第3圖所示，第一實施例之具有平行驅動架構的驅動 電路300係由開關311、321、以及二組彼此並聯的驅動器 所組成’第一組驅動器包含控制級310與驅動級33〇，第 二組驅動器則包含控制級320與驅動級340。p通道金氧 半（PMOS)電晶體311、321作為各組驅動器的開關，用以 1257752 啟動或停置該組驅動器。控制級3 10包含二個電阻3 12、 313、一對放大器314以及一電流源315，用以產生一對輸 出電壓VDIFFi 。控制級320包含二個電阻322、323、一 對放大器324以及一電流源325，用以產生一對輸出電壓 Vdiff2。每個控制級接收至少一信號（或一組差動信號），並 根據該信號產生一組輸出電壓。驅動級3 3 0包含電流源3 3 1 與一對差動放大器332，驅動級340包含電流源341與一 對差動放大器342。每對差動放大器332(342)接收相對應 之輸出電壓，並產生第一驅動電流與第二驅動電流I"、 l2i(I12、122)。之後，利用第一驅動電流Ι11+Ι2ι以驅動負載 25卜利用第二驅動電流ii2 + l22以驅動負載252。每個驅動 級均有一第一輸出端％與一第二輸出端n2。其中，每一 組驅動器的控制級310、320分別經由PMOS電晶體311、 321連接至一電壓源Vdd，每一組驅動器的驅動級330、34〇 之第一輸出端N!與第二輸出端n2均相互連接後，形成輸 出端01與02。 根據本發明，若要產生較大的輸出電流h、l2，就必 須同時將節點B1、B2的電壓拉低（或接地）以導通pM〇S 電晶體3 11、321，進而同時啟動二組驅動器。另一方面， 若只要產生較小的輸出電流L、l2，則只須將節點B1或節 點B2的電壓拉低（或接地），以導通其相對應的pM〇s電晶 體，進而啟動相對應的驅動器。當任一節點B丨、B2的電 壓被拉高導致相對應的PM〇s電晶體關閉，使得流經其相 1257752 對應的控制級之電流量為零’進而關閉相對應的驅動器。 因此’本發明亦具有省電的功能。 依此，本發明透過此種平行架構與設有不㈣流源的 各組驅動器，可依使用者需求’多層級（muhMevei)地控制 電流量。X ’本發明基於此平行架構，利用不同的平行路 徑來驅動不同的驅動級，因&，不僅可透過電流源315、 325,亦可透過提升電阻312、313、322、323大小的配置， 以對驅動電路300的驅動能力進行適當的控制。 值得/主思的疋，二組驅動器的提升電阻3丨2、3 13以 及提^餘322、323的大小未必要相同，可依使用者需 求去α计仁疋，控制級配置不同阻值的提升電阻會形成 不同的輸出電壓VDIFF1、vDIFF2，進而對驅動電路3G〇的驅 動能力造成不同的影響。本發明主要是利用pM〇s電晶體 3 21的V通的數量（或是驅動器啟動的組數）來控制輸 出電流I!、12的電流量，另外，由節點VB也能微調輸出 電流L的電流量，然而程度上，遠不如由pM〇s電晶 體的導通的數量來控制輸出電流Irl2的電流量來的直接。 本實施例的負載251、252是以電阻作為例子，但其 他的元件，例如雷射二極體等也可以作為負載。另一方 面，在本實施例中是以PM〇s電晶體311、321作為啟動 驅動器的開關’亦可以使用n通道金氧半電晶體(NM〇s)或傳輸 閘(transmission gate)等作為開關。 第4圖係本發明之第二實施例的電路圖。如第4圖所 示’第一貝施例之具有平行驅動架構的驅動電路4〇〇與第一 10 1257752 實施例的驅動電路300的結構類似，只是在控制級的電路 部分有差異，其他與第一實施例相同的電路不再贅述。控 制級410包含二個電阻312、313、二個電流源315、416以及一 對放大器414，用以產生一對輸出電壓。控制級 包含二個電阻322、323、二個電流源325、426以及一對放大 器424，用以產生一對輸出電壓VdifF2。所以，第二實施 例與第一實施例之間的差異在於，第二實施例係利用一對 放大器結合一對電流源的結構來取代一對差動放大器結 合一個電流源的結構。 第5圖係本發明之第三實施例的電路圖。如第5圖所 示’第三實施例之具有平行驅動架構的驅動電路5〇〇與第二 貫施例的驅動電路400的結構也類似，只是在控制級的電 路部分有差異，其他與第二實施例相同的電路不再贅述。 控制級510包含四個電阻312、313、517、518以及一對放大器 414’用以產生一對輸出電壓Vdiffi。控制級520包含四個 電阻322、323、527、528以及一對放大器424，用以產生 一對輸出電壓VDIFF2。 本實施例利用電阻517、518來取代 電流源315、416，以及利用電阻527、528來取代電流源325、 426，藉以提高控制級整體的速度。 第6圖係本發明之第四實施例的電路圖。如第6圖所 示，第四實施例之具有平行驅動架構的驅動電路600與第二 實施例的驅動電路400的結構也類似，只是在控制級的電 路部分有差異，其他與第二實施例相同的電路不再贅述。 控制級610包含三個電阻312、313、517以及一對放大器414， 1257752 用以產生一對輸出電壓Vdiffi。控制級620包含三個電阻 322、323、527以及一對放大器424，用以產生一對輪出 電壓VDIFF2。第三實施例與第四實施例中皆利用電阻來替 代電晶體以提南控制級整體的速度。 因應晶片的工作電壓越來越低的趨勢，本發明之具有 平行驅動架構的驅動電路，利用簡單的硬體配置，即可達 到電流量調變的目的，並且，亦具有不增加電路佈局面積 與省電的優點。 ' 以上雖以貫施例說明本發明，但並不因此限定本發明 之fe圍，只要不脫離本發明之要旨，該行業者可進行各種 變形或變更。 【圖式簡單說明】 第1圖係一習知的雷射二極體（丨aser diode，LD)驅動電 路ο 第2圖係本發明之具有平行驅動架構的驅動電路的架 構方塊圖。 第3圖係本發明之第一實施例的電路圖。 第4圖係本發明之第二實施例的電路圖。 第5圖係本發明之第三實施例的電路圖。 第6圖係本發明之第四實施例的電路圖。 圖號說明： 100 雷射二極體的驅動電路 123雷射二極體 11 〇 增益級 12 1257752 120 輸出級 200、300、400具有平行驅動架構的驅動電路 500、600具有平行驅動架構的驅動電路 20η、3 10、320、410、420 控制級 510、520、610、620 控制級 2 In、33 0、340、43 0、440 驅動級 530、540、630、640 驅動級 221〜22η 開關 251、252 負載 311、321 PMOS 電晶體 113、114、124、312、313、322、323 電阻 517、518、527、528 電阻 111、 121、332、342、314、324 差動放大器 414、424放大器 112、 122、315、325、331、341、416、426 電流源 131257752 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit, and more particularly to a drive circuit having a parallel drive architecture. [Prior Art] Fig. 1 is a conventional laser diode (LD) driving circuit. Referring to FIG. 1, in 1998, Lucent (U.S. Patent No. 6,021,143) discloses a laser diode driving circuit 1 comprising at least one gain stage 10 and an output stage 120. . The gain stage 11A includes two resistors 113, 114, a pair of differential amplifiers 111, and a current source ii2 (current source). The output stage 120 includes a resistor 124, a pair of differential amplifiers 121, a laser diode 123, and a current source 122. In particular, the gain of the gain stage 110 is related to the drive current supplied to the laser diode 123. Therefore, since the gain stage 110 and the current sources 112, 122 of the output stage 120 are jointly controlled, the gain from the gain stage 11 可以 can be traced to the magnitude of the drive current. That is, in environments where relatively low currents are required, the gain (or differential voltage VDIFF) will be relatively low to prevent overdriving the output stage. On the other hand, § requires a relatively high current environment to increase the gain to provide enough differential voltage Vdiff to drive the output stage. However, with the development of deep sub-micron processes (deep sub-micr〇npr〇cess), the operating voltage of the wafer is getting lower and lower. Control of the differential voltage VDKF has the potential to cause the current source 122 to operate in the linear region. In addition, when the gain stage i 1 〇 is to drive the output stage 120, the magnitude of the resistance of the current source 丨12 and the pull-up resistors li3, 114 can be adjusted. 1257752 indicates the resistance of the current source 112 π 3, 11 4 Generally speaking, when the differential voltage Vdiff is getting larger and larger, the current is getting larger and larger, but the magnitude of the adjustment resistor must be used to control the differential voltage VDIFF. SUMMARY OF THE INVENTION In view of the above problems, the object of the present invention is to provide a driving circuit for a driving architecture. With a parallel driving architecture, a driving current having a size difference of several times is generated in a parallel manner and is achieved according to a user. In view of the above, the driving circuit of the present invention having a parallel driving architecture is composed of a plurality of arrays of drivers connected in parallel to each other to generate an output current and a second output current. Each set of drivers includes a switch, a control dust generating unit and a drive unit. Each open relationship receives a switch control. The control voltage generating unit is connected to a power source via the aforementioned switch, and generates a set of output voltages after the differential signal. The driving system receives the output (4) outputted by the control voltage generating unit, and generates a first driving current at the first output according to the output voltage, and generates a second driving current at the second output. The first output terminals of the driving units of each group of drivers are connected to each other to generate the first output current, and each of the second output terminals of the driving unit is driven by each of the ija 113⁄4 3S JU, ^ , and The connection is used to generate the aforementioned second output current. Due to the rapid development of the current deep micron process, the operating voltage of the wafer is getting lower and lower. If the current amount of the driving load is less than 10 xiao, the conventional driving circuit is required to meet the requirements. The driving circuit with parallel drive architecture of the present invention can achieve the purpose of variable current 1257752 with a simple hardware configuration. At the same time, the present invention also exhibits the advantages of not having an increase in circuit layout area and power saving. The above and other objects and advantages of the present invention will be described in detail with reference to the accompanying drawings. [Embodiment] Fig. 2 is a block diagram showing the structure of a drive circuit having a parallel drive architecture of the present invention. Referring to FIG. 2, a driving circuit 2 having a parallel driving architecture is composed of drivers in which N (N is a positive integer greater than 1) are connected in parallel with each other, and each group of drivers further includes a control stage 2〇n and a driving. Level 21n (Ηκλγ, n is a positive integer). The control stage 2〇n receives a set of differential signals to produce a set of output voltages, and the power supply of each control stage 20n is controlled by a separate switch y2η. The driver stage 21 η receives the output voltage ' of the corresponding control stage and outputs the first and second driving $ streams at the first and second outputs, respectively. The first output terminals of each of the driver stages 21n are connected to each other and the second output terminals are connected to each other for generating a -first output current 1" and a second output current 12' to drive the loads 251, 252. Figure 3 is a circuit diagram of a first embodiment of the present invention. This circuit structure is explained in detail below. ° ^ ° ^ As shown in Fig. 3, the drive circuit 300 having the parallel drive architecture of the first embodiment is composed of switches 311, 321 and two sets of drivers connected in parallel with each other. 'The first set of drivers includes the control stage 310 and The driver stage 33A, the second group of drivers includes a control stage 320 and a driver stage 340. The p-channel gold oxide half (PMOS) transistors 311, 321 act as switches for each group of drivers for 1257752 to start or stop the set of drivers. Control stage 3 10 includes two resistors 3 12, 313, a pair of amplifiers 314, and a current source 315 for generating a pair of output voltages VDIFFi. Control stage 320 includes two resistors 322, 323, a pair of amplifiers 324, and a current source 325 for generating a pair of output voltages Vdiff2. Each control stage receives at least one signal (or a set of differential signals) and produces a set of output voltages based on the signals. The driver stage 323 includes a current source 3 3 1 and a pair of differential amplifiers 332. The driver stage 340 includes a current source 341 and a pair of differential amplifiers 342. Each pair of differential amplifiers 332 (342) receives a corresponding output voltage and generates a first drive current and a second drive current I", l2i (I12, 122). Thereafter, the first drive current Ι11+Ι2ι is used to drive the load 25 to utilize the second drive current ii2 + l22 to drive the load 252. Each driver stage has a first output terminal % and a second output terminal n2. The control stages 310, 320 of each group of drivers are respectively connected to a voltage source Vdd via the PMOS transistors 311, 321 , and the first output terminals N! and the second output terminals of the driving stages 330, 34 of each group of drivers After n2 are connected to each other, the output terminals 01 and 02 are formed. According to the present invention, in order to generate a large output current h, l2, the voltages of the nodes B1, B2 must be pulled low (or grounded) to turn on the pM〇S transistors 3 11, 321 to simultaneously activate the two sets of drivers. . On the other hand, if only a small output current L, l2 is generated, the voltage of the node B1 or the node B2 must be pulled low (or grounded) to turn on the corresponding pM〇s transistor, thereby starting the corresponding Drive. When the voltage of any of the nodes B丨, B2 is pulled high, the corresponding PM〇s transistor is turned off, so that the amount of current flowing through the corresponding control stage of its phase 1257752 is zero', and the corresponding driver is turned off. Therefore, the present invention also has a power saving function. Accordingly, the present invention can control the electric current by the multi-level (muhMevei) according to the user's demand through the parallel structure and the sets of drivers provided with the (four) flow source. X 'The present invention is based on this parallel architecture, using different parallel paths to drive different driver stages, because &, not only through the current source 315, 325, but also through the configuration of the lifting resistors 312, 313, 322, 323 size. The drive capability of the drive circuit 300 is appropriately controlled. It is worthwhile/considered that the lifting resistors 3丨2, 313 and the size of the 322 and 323 of the two sets of drivers are not necessarily the same, and can be adjusted according to the user's requirements. The control level is configured with different resistance values. The boosting resistors form different output voltages VDIFF1, vDIFF2, which in turn have different effects on the driving capability of the driving circuit 3G. The present invention mainly utilizes the number of V-channels of the pM〇s transistor 3 21 (or the number of groups activated by the driver) to control the amount of current of the output currents I!, 12, and the node VB can also fine-tune the output current L. The electrical current, however, is much less straightforward than the amount of conduction of the output current Irl2 by the amount of conduction of the pM〇s transistor. The loads 251, 252 of this embodiment are exemplified by resistors, but other components such as a laser diode or the like can also be used as a load. On the other hand, in the present embodiment, the switch that uses the PM〇s transistors 311 and 321 as the start driver can also use an n-channel metal oxide semiconductor (NM〇s) or a transmission gate as a switch. . Figure 4 is a circuit diagram of a second embodiment of the present invention. As shown in FIG. 4, the drive circuit 4 of the first embodiment having a parallel drive architecture is similar to the structure of the drive circuit 300 of the first 10 1257752 embodiment, except that there is a difference in the circuit portion of the control stage. The same circuits of the first embodiment will not be described again. Control stage 410 includes two resistors 312, 313, two current sources 315, 416, and a pair of amplifiers 414 for generating a pair of output voltages. The control stage includes two resistors 322, 323, two current sources 325, 426 and a pair of amplifiers 424 for generating a pair of output voltages VdifF2. Therefore, the difference between the second embodiment and the first embodiment is that the second embodiment uses a configuration in which a pair of amplifiers are combined with a pair of current sources in place of a pair of differential amplifiers combined with a current source. Fig. 5 is a circuit diagram of a third embodiment of the present invention. As shown in FIG. 5, the structure of the drive circuit 5A having the parallel drive architecture of the third embodiment is similar to that of the drive circuit 400 of the second embodiment, except that the circuit portion of the control stage is different, and the other The same circuits in the second embodiment will not be described again. Control stage 510 includes four resistors 312, 313, 517, 518 and a pair of amplifiers 414' for generating a pair of output voltages Vdiffi. Control stage 520 includes four resistors 322, 323, 527, 528 and a pair of amplifiers 424 for generating a pair of output voltages VDIFF2. This embodiment utilizes resistors 517, 518 in place of current sources 315, 416, and resistors 527, 528 in place of current sources 325, 426, thereby increasing the overall speed of the control stage. Figure 6 is a circuit diagram of a fourth embodiment of the present invention. As shown in FIG. 6, the drive circuit 600 having the parallel drive architecture of the fourth embodiment is similar in structure to the drive circuit 400 of the second embodiment, except that there is a difference in the circuit portion of the control stage, and other and second embodiments. The same circuit will not be described again. Control stage 610 includes three resistors 312, 313, 517 and a pair of amplifiers 414, 1257752 for generating a pair of output voltages Vdiffi. Control stage 620 includes three resistors 322, 323, 527 and a pair of amplifiers 424 for generating a pair of wheel-out voltages VDIFF2. In the third embodiment and the fourth embodiment, resistors are used instead of the transistors to increase the overall speed of the control stage. In response to the trend that the operating voltage of the wafer is getting lower and lower, the driving circuit with the parallel driving architecture of the present invention can achieve the purpose of current quantity modulation by using a simple hardware configuration, and also has no increase in circuit layout area. The advantages of power saving. The invention is described above by way of example, and the invention is not limited thereto, and various modifications and changes can be made by those skilled in the art without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a conventional laser diode (LD) driving circuit. Fig. 2 is a block diagram showing the structure of a driving circuit having a parallel driving structure of the present invention. Figure 3 is a circuit diagram of a first embodiment of the present invention. Figure 4 is a circuit diagram of a second embodiment of the present invention. Fig. 5 is a circuit diagram of a third embodiment of the present invention. Figure 6 is a circuit diagram of a fourth embodiment of the present invention. Figure number description: 100 laser diode drive circuit 123 laser diode 11 〇 gain stage 12 1257752 120 output stage 200, 300, 400 drive circuit 500, 600 with parallel drive architecture with parallel drive architecture drive circuit 20η, 3 10, 320, 410, 420 control stages 510, 520, 610, 620 control stage 2 In, 33 0, 340, 43 0, 440 drive stage 530, 540, 630, 640 drive stage 221 ~ 22n switch 251, 252 load 311, 321 PMOS transistor 113, 114, 124, 312, 313, 322, 323 resistors 517, 518, 527, 528 resistors 111, 121, 332, 342, 314, 324 differential amplifier 414, 424 amplifier 112, 122, 315, 325, 331, 341, 416, 426 current source 13