JP2006054756A - Output drive circuit and method for controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LVDS drive circuit for improving the maximum operation frequency of the LVDS drive circuit, thereby preventing voltage not lower than breakdown voltage from being applied to a low-voltage transistor by using a low-voltage transistor of which the voltage is lower than the power supply voltage for a switching transistor. <P>SOLUTION: In the output drive circuit, a PMOS level shifter circuit 18 and an NMOS level shifter circuit 19 of which the breakdown voltage is reduced to voltage (e.g. 1.8V), as compared with the power supply voltage (e.g. 2.5V) of PMOS transistors 4, 6 and NMOS transistors 5, 7 in a switching circuit 14 and which can output logical L and H levels to be supplied to the gates G of the PMOS transistors 4, 6 and the NMOS transistors 5, 7 and an output switching circuit 20 for interrupting or connecting an output pass are added, and a current control circuit 8 is controlled in a common-mode circuit 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an output drive circuit of a receiver circuit and a control method of the output drive circuit, and particularly improves the maximum operating frequency of the drive circuit by using a switching transistor having a withstand voltage lower than the power supply voltage, and more than the low withstand voltage of the switching transistor. The present invention relates to an output drive circuit configured to prevent the voltage from being applied and a method for controlling the output drive circuit.

  Conventionally, Patent Document 1 discloses a circuit structure that can lower the breakdown voltage of a MOS transistor in an output stage as a voltage output circuit including a level shift circuit. This voltage output circuit outputs, as an output signal, one of three types of voltages of output H level VCC, output L level VEE, and intermediate level VM based on two input signals input to the input terminal. FIG. 6 shows a circuit configuration disclosed in Patent Document 1. In FIG.

  In FIG. 6, input signals S 1 and S 2 input to two input terminals 1 and 2 are converted into two decode signals by a decode circuit including an inverter 21, a NAND gate circuit 22 and a NOR gate circuit 23. One of them is supplied to the first level shift circuit 24, and the other is supplied to the second level shift circuit 25. Both the input signals S1 and S2 are signals that change between the logic L level GND (0V) and the logic H level VDD (5V). The inverter circuit 21, NAND gate circuit 22, and NOR gate circuit 23 operate between GND (0V) and VDD (5V).

  The first level level shift circuit 24 converts the input GND (0 V) level or VDD (5 V) level signal into a GND (0 V) level or output H level VCC (40 V) signal and converts it to the H side (Pch). This is applied to the gate of the output transistor 28. On the other hand, the second level level shift circuit 25 converts the input GND (0 V) level or VDD (5 V) level signal into an output L level VEE (−40 V) or VDD (5 V) signal and converts it to the L side ( Nch) applied to the gate of the output transistor 29.

  The source of the H-side output transistor 28 is connected to the output H level power supply voltage VCC, and the source of the L side output transistor 29 is connected to the output L level power supply voltage VEE. The drain of the H-side output transistor 28 and the drain of the L-side output transistor 29 are connected, and this connection point is connected to the output terminal 3. An output signal S3 is output from the output terminal 3.

  Further, a switch circuit in which another Pch and Nch transistors 26 and 27 are connected in series is connected between the intermediate level VM (2.5 V) and the output terminal 3. The gate of the Pch transistor 26 is connected to the gate of the L side output transistor 29, and the gate of the Nch transistor 27 is connected to the gate of the H side output transistor 28.

  According to the circuit configuration as described above, the output signal S3 obtained at the output terminal 3 by the combination of the H or L level of the two input signals S1 and S2 is one of the potentials of VCC, VEE, and VM. become.

  For example, as shown in FIG. 6, if the first input signal S1 is L level, the input signal of the first level shift circuit 24 becomes H level regardless of the second input signal S2, and the second The input signal of the level shift circuit 25 becomes L level. As a result, both the H-side output transistor 28 and the L-side output transistor 29 are turned off. On the other hand, both the Pch transistor 26 to which the L level signal is input to the gate and the Nch transistor 27 to which the H level signal is input to the gate are turned on. Accordingly, the potential of the output signal S3 at this time is the intermediate potential VM.

  When the first input signal S1 is at the H level, the input signal of the first level shift circuit 24 and the input signal of the second level shift circuit 25 are both at the H level or L according to the second input signal S2. Become a level. That is, if the second input signal S2 is H level, the input signals of the first and second level shift circuits 24 and 25 are both L level, and if the second input signal S2 is L level, The input signals of the first and second level shift circuits 24 and 25 both become H level. In the former case, the H-side output transistor 28 is turned on and the L-side output transistor 29 is turned off, so that the potential of the output signal S3 at this time is VCC. In the latter case, since the H-side output transistor 28 is turned off and the L-side output transistor 29 is turned on, the potential of the output signal S3 at this time is VEE. In either case, since either one of the Pch transistor 26 and the Nch transistor 27 is turned off, the intermediate potential VM and the output terminal 3 are cut off.

  According to the operation as described above, the range of the voltage applied to the gate of the H-side output transistor 28 is GND (0 V) to VCC (40 V), which is half of the conventional (−40 V to 40 V). Similarly, the voltage range applied to the gate of the L-side output transistor 29 is VEE (−40 V) to VDD (5 V), which is a voltage close to half of the conventional voltage (−40 V to 40 V). Therefore, it is disclosed that the breakdown voltage of both the transistors 28 and 29 can be greatly reduced, and accordingly the chip area and power consumption of the integrated circuit can be reduced.

  Further, FIG. 7 discloses a configuration of an input / output drive circuit for LVDS (Low Voltage Differential Signal) as an output drive circuit. FIG. 7 shows a circuit configuration of a general LVDS drive circuit conventionally used. LVDS is a kind of high-speed serial data transmission standard for connection between devices such as computers, and its input / output circuit can transmit a 655 Mbit / S signal through a twisted pair wire of a maximum length of 25 m. This method is characterized in that it is less susceptible to electromagnetic radiation noise and ground potential difference between electronic devices by adopting a differential signal format, and its output is a current drive format as shown in FIG. 7 and its amplitude is about 3.5 mA. (The differential signal amplitude is 250 to 450 mV), which is extremely small, and has a configuration suitable for reducing the power consumption and noise of the device.

  Specifically, A, B, C, and D are input terminal signals supplied to the gates of the PMOS transistors 4 and 6 and the NMOS transistors 5 and 7 indicating the output stage constituting the switching circuit 14. A pair of PMOS transistors 4 and 6 and NMOS transistors 5 and 7 in a CMOS configuration are connected in series with the drains of the PMOS transistors 4 and 6, respectively, and the drains of the NMOS transistors 5 and 7, respectively. The sources of the NMOS transistors 5 and 7 are connected in common to form a bridge configuration.

  A current control circuit 8 is connected between the commonly connected sources of the PMOS transistors 4 and 7 and the power supply voltage VCC, and a current source circuit 9 is connected between the commonly connected sources of the NMOS transistors 5 and 7 and the ground potential VEE. Has been. The output taken from the commonly connected drains of the CMOS transistors 4, 5 and 6, 7 is supplied to the load 13 constituting the receiver circuit 17, and the CMOS transistor 6, the CMOS transistor 6 The output midpoint voltage taken from the midpoint of the resistor 12 connected between the commonly connected drains 7 is supplied to one input terminal of the differential amplifier circuit 10 and supplied to the other input terminal of the differential amplifier circuit 10. The reference voltage VREF is supplied from the reference voltage source 11. The output of the differential amplifier circuit 10 constituting the comparator controls the current of the current source control circuit 8 so that the amplitude of the differential output voltage of the switching circuit 14 is 250 to 450 mV and the drive current amplitude is about 3.5 mA. Is controlling.

  The output voltage between the commonly connected drains of the switching circuit 14 used in the LVDS drive circuit 16 configured as described above, that is, the common voltage (voltage between X) is selected to be about 1.2V (the standard is (There are several types, not necessarily 1.2V), and in order to stack MOS transistors in a multistage configuration with the switching circuit 14 and the current source circuit 9, it is necessary to set the power supply voltage higher than 1.2V. . Therefore, it is necessary to use a high breakdown voltage transistor for the LVDS drive circuit 16. For this reason, high-breakdown-voltage transistors are used as PMOS transistors and NMOS transistors used in the switching circuit 16.

The voltage output circuit having the configuration shown in Patent Document 1 described above uses two level shifters based on two input signals input to the input terminal, and outputs an output H level VCC, an output L level VEE, and an intermediate level VM. Thus, one of the three voltages is output to the output terminal 3 as an output signal, and the withstand voltage of the two transistors 28 and 29 for output can be lowered. Although it is disclosed that the power consumption can be reduced, the voltage range applied to the gate of the H-side output transistor 28 is GND (0V) to VCC (40V), and the conventional voltage is −40V to 40V. A MOS transistor for high withstand voltage of 40 V is used even if it is half of that.
JP 2000-49584 A (FIG. 1) Electronic information communication handbook, 6 groups, integrated circuit, 6-2 edition, high-speed technology, pages 682 to 683, LVSD

  The feature of the LVDS drive circuit shown in FIG. 7 is a low-amplitude output, and the output voltage does not fully swing in the range of the power supply voltage. For this reason, it is not necessary to use a high breakdown voltage transistor for all transistors used in the IC circuit. Generally, a high breakdown voltage MOS transistor has a lower switching speed than a low breakdown voltage MOS transistor. The maximum operating frequency of the LVDS drive circuit 16 is defined by the PMOS and NMOS transistors 4, 5, 6, and 7 of the switching circuit 14, and the PMOS and NMOS transistors 4, 5, 6, and 7 of the switching circuit 14 are defined. The problem is that the use of a high-breakdown-voltage transistor does not increase the maximum operating frequency of the general LVDS drive circuit 16.

  The present invention has been made to solve the above-described problems. The problem to be solved by the present invention is to improve the maximum operating frequency by using a low breakdown voltage transistor as a transistor of a switching circuit in an LVDS drive circuit. I can do it. The reason why the maximum operating frequency is improved by using this low breakdown voltage MOS transistor as compared with the high breakdown voltage MOS transistor is that (1) the gate area of the MOS transistor is reduced, and the gate capacitance can be reduced. Increases switching speed. (2) The gm of the MOS transistor is improved, and the ability to flow current is improved. (3) This is because, for example, the switching speed is increased by reducing the fluctuation width of the gate voltage of the MOS transistor.

  According to a first aspect of the present invention, a switching circuit that outputs current in a reverse direction to a load is supplied to four transistors having a pair of CMOS transistors as a bridge configuration, and a current source that supplies current to the switching circuit. In an output drive circuit comprising a circuit and a common mode circuit that is controlled from the midpoint of the CMOS and controls the current of the current source circuit, a logic L is applied to the same polarity transistor of the pair of CMOS transistors constituting the switching circuit. A PMOS level shifter and an NMOS level shifter for supplying an input changing between a level and a logic H level, and an output switching circuit for controlling on and off of an output provided between the switching circuit and the load. Four transistors are composed of transistors with a withstand voltage lower than the voltage of the current source. Is obtained by the output drive circuit, characterized in that the.

  According to a second aspect of the present invention, an input signal is supplied to four transistors having a pair of CMOS transistors as a bridge configuration, and a current that supplies current to the switching circuit is output. In a method for controlling an output drive circuit comprising a circuit and a common mode circuit that is controlled from the midpoint of the CMOS and controls the current of the current source circuit, transistors having the same polarity of the pair of CMOS transistors constituting the switching circuit A PMOS level shifter and an NMOS level shifter for supplying an input that changes between a logic L level and a logic H level, and an output switching circuit for controlling on and off of an output provided between the switching circuit and the load, The four transistors of the switching circuit are connected to a transistor with a breakdown voltage lower than the voltage of the current source In the operating state of the switching circuit, the common mode circuit and the output switching circuit are in the operating state, and the output from the logic L level to the logic H level is output from the PMOS level shifter and the NMOS level shifter. This is a method for controlling the output drive circuit.

  According to a third aspect of the present invention, there are provided a switching circuit for supplying an input signal to four transistors having a pair of CMOS transistors in a bridge configuration and outputting a current in a reverse direction to a load, and a current source for supplying a current to the switching circuit. In a method for controlling an output drive circuit comprising a circuit and a common mode circuit that is controlled from the midpoint of the CMOS and controls the current of the current source circuit, transistors having the same polarity of the pair of CMOS transistors constituting the switching circuit A PMOS level shifter and an NMOS level shifter for supplying an input that changes between a logic L level and a logic H level, and an output switching circuit for controlling on and off of an output provided between the switching circuit and the load, The four transistors of the switching circuit are connected to a transistor with a breakdown voltage lower than the voltage of the current source It is composed of a star, and when the switching circuit is in the standby state, or when the power is turned on, the current source circuit, the common mode circuit and the output switching circuit are set to the non-operating state and the logic L level is output from the PMOS level shifter. The output drive circuit control method is characterized in that a logic H level is output from a level shifter.

  According to the present invention, in the LVDS drive circuit, by using a low breakdown voltage transistor as the MOS transistor of the switching circuit, the gate area of the MOS transistor of the switching circuit can be reduced, the gate capacitance can be reduced, and the switching speed can be increased. I can do it. In addition, since the gate voltage fluctuation width is reduced, the switching speed is increased, so that the gm of the MOS is improved, the current flowing capability is also improved, and the maximum operating frequency can be increased.

  The configuration of the output drive circuit and the output drive circuit control method of the present invention will be described below with reference to FIGS. FIG. 1 is an output drive circuit diagram showing an embodiment of the present invention, FIG. 2 is an output drive circuit diagram for explaining the operation when transitioning from the operating state of the present invention to the standby state, and FIG. 3 is from the standby state of the present invention. FIG. 4 is an output drive circuit diagram for explaining the operation when the power is turned on according to the present invention, and FIG. 5 is a flowchart for explaining the operational state of the present invention. is there. In the following description, parts corresponding to those in FIGS. 6 and 7 are denoted by the same reference numerals.

  First, an LVDS drive circuit that supplies a low-amplitude voltage to the receiver circuit 17 as the output drive circuit 16 of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 18 denotes a PMOS transistor level shifter to which an audio input signal is supplied from input terminals S3 and S4 via a decoder or the like. Similarly, reference numeral 19 denotes an NMOS transistor level shifter to which an audio input signal is supplied from input terminals S5 and S6 via a decoder or the like. The PMOS transistor level shifter 18 outputs a logic H level output A = 2.5V and a logic L level B = 0.7V. The NMOS transistor level shifter 19 outputs a logic H level output C = 1.8V and a logic L level B = 0V. The outputs A and B from the PMOS transistor level shifter 18 are supplied to the gates G of the PMOS transistors 4 and 6 constituting the switching circuit 14, respectively. Similarly, outputs C and D from the NMOS transistor level shifter 19 are supplied to the gates G of the NMOS transistors 5 and 7 constituting the switching circuit 14, respectively.

  The switching circuit in FIG. 1 will be described in detail below. A, B, C, and D are supplied to the gates of PMOS transistors 4 and 6 and NMOS transistors 5 and 7 indicating the output stage constituting the switching circuit 14. The PMOS transistors 4 and 6 and the NMOS transistors 5 and 7 having a CMOS configuration, which are input signals, are connected in series with the drains of the PMOS transistors 4 and 6 and the drains of the NMOS transistors 5 and 7, respectively. And the sources of the NMOS transistors 5 and 7 are commonly connected to each other to form a bridge configuration.

  A current control circuit 8 is connected between the commonly connected sources of the PMOS transistors 4 and 6 and the power supply voltage VCC, and a current source circuit 9 is connected between the commonly connected sources of the NMOS transistors 5 and 7 and the ground potential VEE. Has been. The output extracted from the commonly connected drains of the PMOS transistors 4 and 5 and the NMOS transistors 6 and 7 constituting the CMOS transistor is supplied to the load 13 constituting the receiver circuit 17 via the switching transistors 20A and 20B for switching the output path. The differential amplifying circuit 10 converts the midpoint voltage of the output that is supplied and taken out from the midpoint of the resistor 12 connected between the commonly connected drains of the PMOS transistors 4 and 5 and the commonly connected drains of the NMOS transistors 6 and 7. The reference voltage VREF is supplied from the reference voltage source 11 to the other input terminal of the differential amplifier circuit 10 that is supplied to one input terminal. The output of the differential amplifier circuit 10 constituting the comparator controls the current of the current source control circuit 8, the voltage between the points X is 1.2V, and the amplitude of the differential output voltage of the switching circuit 14 at the load 13 is 350 mVpp. It is controlled to become. That is, a common mode circuit 15 using the switching circuit 14 is configured.

  In the above-described configuration, when the output drive circuit 16 is in an operating state, the common mode circuit 15 is operating. Therefore, the voltage between both drain connection points of the switching circuit 14 in the CMOS configuration is 1.2 V ± 350 mVpp. . Therefore, no overvoltage is applied between the source and drain of each of the transistors 4, 5, 6, and 7 in the switching circuit 14 for low withstand voltage. The gates G of the transistors 4, 5, 6 and 7 of the switching circuit 14 for low withstand voltage are connected to the gates G of the PMOS transistors 4 and 6 having the same polarity in the CMOS configuration and the NMOS transistors 5 and 7 having the same polarity. Signals output from two PMOS level shifter circuits 18 and NMOS level shifter circuits 19 that change from a logic L level to a logic H level are input.

  Two types of PMOS and NMOS level shifter circuits 18 and 19 are prepared for PMOS and NMOS, and the audio level input signal supplied to the respective PMOS level shifter circuit 18 and NMOS level shifter circuit 19 is used as the PMOS level shifter circuit 18. Is in the range of 2.5V to 0.7V, and the level shifter circuit 19 for NMOS converts the voltage from 0V to 1.8V. These first and second level shifter circuits 18 and 19 prevent the overvoltage from being applied to the gate voltages of the transistors 4, 5, 6 and 7 of the switching circuit for low withstand voltage. Further, between the drains of the respective transistors which are the output terminals of the pair of CMOS transistors 4, 5, 6 and 7 and the load (receiver circuit) 13, the sources and drains of the NMOS transistors 20 A and 20 B serving as the output switching circuit 20 are electrically connected. That is, it is in an “on” state.

  Next, the operation when the output drive circuit 16 is switched from the operating state to the standby state will be described with reference to FIGS. 2 and 5A.

  When switching from the operating state to the standby state, as shown in the first step S1, if the gate voltage is 0.7V in the case of the PMOS transistors 4 and 6, and 1.8V in the case of the NMOS transistors 5 and 7, the second step is applied. As shown in S2, all the switching transistors 4, 5, 6, and 7 of the switching circuit 14 are turned on. In this state, an overvoltage is not applied to the gates G of the switching transistors 4, 5, 6 and 7 with low breakdown voltage.

  Next, the output switching circuit 20 including the NMOS transistors 20A and 20B is turned OFF as in the third step S3. Unless this state is set, it is necessary to restrict the receiver circuit 17 side, so that the path between the output drive circuit 16 and the receiver circuit 17 is blocked. Further, as shown in the fourth step S4, the common mode circuit 15 is turned off so that no current flows from the current control circuit 8 to which the power supply voltage VCC (2.5 V) is supplied. In this state, power consumption can be reduced to zero, and no overvoltage is applied between the source S and drain D of the switching transistors 4, 5, 6, and 7 of the low-voltage switching transistor circuit 14.

The case of transition from the standby state to the operating state will be described with reference to FIGS. 3 and 5B. In the standby state, the switching transistors 4, 5, 6, and 7 of the switching circuit 14 are all ON, and the switching transistors 20A and 20B of the output switching circuit 20 are OFF, as shown in the standby state from the operation in FIG. In addition, since the common mode circuit 15 is OFF, no current flows from the current source circuit 9. From this state, first, as shown in the first step ST1, the common mode circuit 15 is turned on, and the current from the current source circuit 9 is controlled by the current control circuit 8 so that the current flows through the switching circuit 14. If the common mode circuit 15 is turned on first, 1.2 V is applied to the output point X, so that no overvoltage is applied between the source and drain of the switching transistor 14 for low withstand voltage.
Next, as shown in the second step ST2, the NMOS transistors 20A and 20B of the output switching circuit 20 are turned on. In the next third step ST3, the gate G of each of the switching transistors 4, 5, 6 and 7 for low withstand voltage is applied from the logic L level to the logic H level (L: 0.7V) via the PMOS level shifter 18 and the NMOS level shifter 19. , H: 2.5V) and (L: 0V, H: 1.8V).

  Further, the case where the power is turned on will be described with reference to FIGS. 4 and 5C. When the power supply voltage is turned on, as shown in the first step STE1 in FIG. 5C, only the power supply voltage VCC is not applied, and other control signals are input first. In the next second step STE2, the signal state is as shown in FIG. All are set in the standby state as described in the above. This state is infinitely equal to the standby state, and no overvoltage is applied to the low breakdown voltage switching transistors 4, 5, 6, and 7. In the next third step STE2, a voltage is applied to the power supply VCC next.

According to the LVDS drive circuit described above, the maximum operating frequency is improved by using a low breakdown voltage transistor as the switching transistor. That is, by using a low breakdown voltage switching transistor, the maximum operating frequency is improved compared to a high breakdown voltage transistor.
(A) The gate area is reduced, the gate capacitance can be reduced, and the switching speed is increased.
(B) The gm of the MOS is improved, and the ability to flow current is improved.
(C) The switching speed is increased by reducing the fluctuation range of the gate voltage.
Can be mentioned. The three items described above will be described in more detail below.

  (A) From the equation (1) shown below, it can be seen that the gate capacitance C decreases as the gate area S decreases. (In actuality, since the film thickness is reduced by lowering the withstand voltage, it cannot be obtained by simple calculation, but there is no problem considering that the change amount of the gate capacitance S> the change amount of the height d.) From equation (2), it can be seen that if the gate capacitance C is reduced, the charge / discharge time of the gate capacitance C is shortened and the switching speed is increased.

C = ε × k × S / d (1)
T = C × V / I (2)
Here, C: capacitance of gate, ε: relative permittivity of vacuum, k: relative permittivity, S: area, d: height.

  (B) From equation (3) below, it can be seen that the source-to-solenoid voltage Id increases as the transconductance (gain) gm increases (in this case, the gate voltage Vgs and the threshold voltage Vth are considered to be constant). It can be seen that the ability to flow current is improved.

gm = Id / Vgs−Vth (3)
Here, gm: transconductance, Id: source-drain current, Vgs: gate voltage, and Vth: threshold voltage.

  (C) From the following equations (4) and (5), it can be seen that when the power supply voltage VCC is small, both the rise time Tf and the fall time Tr are small and the switching speed is high.

Tr = VCC / Rr (4)
Tf = VCC / Rf (5)
Here, Tr: rise time, Tf: fall time, Rr: rise time slope, Rf: fall time slope, VCC: power supply voltage.

  In the above configuration, the configuration for controlling the power supply voltage VCC and the current control circuit 8 and the output switching circuit is not shown. However, the software of the microcomputer (CPU) included in the LVDS drive circuit or the hardware of the switching control circuit of the MOS configuration Switching control can be easily performed.

It is a circuit diagram which shows one example of the operating state of the output drive circuit of the circuit of this invention. FIG. 5 is a circuit diagram for explaining an operation when the output drive circuit according to the present invention is switched from an operation state to a standby state. FIG. 4 is a circuit diagram for explaining an operation when the output drive circuit of the present invention is switched from a standby state to an operation state. FIG. 4 is a circuit diagram for explaining an operation when power is turned on according to the present invention. 4 is a flowchart of the output drive circuit of the present invention. It is a circuit diagram which shows one example of a conventional output drive circuit. It is a circuit diagram which shows the other example of a form of the conventional output drive circuit.

Explanation of symbols

  4, 6 ... PMOS transistors, 5, 7 ... NMOS transistors, 8 ... Current control circuit, 9 ... Current source circuit, 10 ... Differential amplifier circuit, 11 ... Reference source, DESCRIPTION OF SYMBOLS 12 ... Resistance, 13 ... Load, 14 ... Switching circuit, 15 ... Common mode circuit, 16 ... Output drive circuit, 17 ... Receiver circuit, 18 ... Level shifter circuit for PMOS 19 ... NMOS level shifter circuit

Claims (6)

An input signal is supplied to four transistors having a pair of CMOS transistors as a bridge configuration, and outputs a current in the reverse direction to the load; a current source circuit that supplies current to the switching circuit; In an output drive circuit comprising a common mode circuit which is configured to take out from the middle point and control the current of the current source circuit,
A PMOS level shifter and an NMOS level shifter for supplying an input changing between a logic L level and a logic H level to the same polarity transistors of the pair of CMOS transistors constituting the switching circuit;
An output switching circuit for controlling on / off of an output provided between the switching circuit and the load;
Equipped
An output drive circuit characterized in that the four transistors of the switching circuit are composed of transistors having a breakdown voltage lower than the voltage of the current source. The pair of CMOS transistors is constituted by a series circuit in which the drains of a PMOS transistor and an NMOS transistor are connected to each other, and the switching circuit having a bridge configuration in which the sources of the pair of PMOS transistors and the sources of the pair of NMOS transistors are connected to each other. ,
A current control circuit connected between a connection point between the sources of the PMOS transistors in the bridge configuration and a hot power supply;
The current source circuit connected between a connection point between the sources of the NMOS transistors in the bridge configuration and the ground;
The common mode circuit comprising: a differential amplifier circuit for supplying an output taken out from a connection point connecting drains of the pair of CMOS transistors to the load and comparing a midpoint voltage of the output with a reference voltage; ,
Comprising
2. The output drive circuit according to claim 1, wherein the current of the current control circuit of the current source circuit is controlled by a comparison output of the differential amplifier circuit of the common mode circuit. An input signal is supplied to four transistors having a pair of CMOS transistors as a bridge configuration, and outputs a current in the reverse direction to the load; a current source circuit that supplies current to the switching circuit; In a control method of an output drive circuit comprising a common mode circuit which is configured to control a current of the current source circuit by taking out from a middle point,
A PMOS level shifter and an NMOS level shifter for supplying an input changing between a logic L level and a logic H level to the same polarity transistors of the pair of CMOS transistors constituting the switching circuit;
An output switching circuit that performs on / off control of an output provided between the switching circuit and the load;
Comprising
The four transistors of the switching circuit are composed of transistors having a withstand voltage lower than the voltage of the current source. In the operation state of the switching circuit, the common mode circuit and the output switching circuit are in the operation state and the PMOS level shifter And a method for controlling an output drive circuit, wherein the NMOS level shifter outputs the logic L level to the logic H level.   In the operating state of the switching circuit, the logic L level of the PMOS level shifter is set to 0.7V, the logic H level is set to 2.5V, the logic L level of the NMOS level shifter is set to 0V, and the logic H level is set. 4. The method of controlling an output drive circuit according to claim 3, wherein the voltage is 1.8V. An input signal is supplied to four transistors having a pair of CMOS transistors as a bridge configuration, and outputs a current in the reverse direction to the load; a current source circuit that supplies current to the switching circuit; In a control method of an output drive circuit comprising a common mode circuit which is configured to control a current of the current source circuit by taking out from a middle point,
A PMOS level shifter and an NMOS level shifter for supplying an input changing between a logic L level and a logic H level to the same polarity transistors of the pair of CMOS transistors constituting the switching circuit;
An output switching circuit that performs on / off control of an output provided between the switching circuit and the load;
Comprising
The four transistors of the switching circuit are composed of transistors having a withstand voltage lower than the voltage of the current source, and the current source circuit, the common mode circuit, and the power source are switched from the operation state of the switching circuit to the standby state or when the power is turned on. A control method for an output drive circuit, wherein the output switching circuit is set to a non-operating state, the logic L level is output from the PMOS level shifter, and the logic H level is output from the NMOS level shifter. The logic level of the PMOS level shifter is set to 0.7V and the logic level of the NMOS level shifter is set to 1.8V from the operating state of the switching circuit to the standby state. 5. A method for controlling an output drive circuit according to 5.

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