TWI257067B - Apparatus and method for renaming a data block within a cache - Google Patents
Apparatus and method for renaming a data block within a cacheInfo
- Publication number
- TWI257067B TWI257067B TW092128965A TW92128965A TWI257067B TW I257067 B TWI257067 B TW I257067B TW 092128965 A TW092128965 A TW 092128965A TW 92128965 A TW92128965 A TW 92128965A TW I257067 B TWI257067 B TW I257067B
- Authority
- TW
- Taiwan
- Prior art keywords
- block
- cache lines
- logic
- execution logic
- renaming
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6028—Prefetching based on hints or prefetch instructions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/405,980 US7111125B2 (en) | 2002-04-02 | 2003-04-02 | Apparatus and method for renaming a data block within a cache |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200421175A TW200421175A (en) | 2004-10-16 |
TWI257067B true TWI257067B (en) | 2006-06-21 |
Family
ID=32850634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092128965A TWI257067B (en) | 2003-04-02 | 2003-10-20 | Apparatus and method for renaming a data block within a cache |
Country Status (4)
Country | Link |
---|---|
US (1) | US7111125B2 (zh) |
EP (1) | EP1465077B1 (zh) |
CN (1) | CN100461135C (zh) |
TW (1) | TWI257067B (zh) |
Families Citing this family (29)
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US6658552B1 (en) * | 1998-10-23 | 2003-12-02 | Micron Technology, Inc. | Processing system with separate general purpose execution unit and data string manipulation unit |
US20070038984A1 (en) * | 2005-08-12 | 2007-02-15 | Gschwind Michael K | Methods for generating code for an architecture encoding an extended register specification |
US9367465B2 (en) * | 2007-04-12 | 2016-06-14 | Hewlett Packard Enterprise Development Lp | Method and system for improving memory access performance |
US8122195B2 (en) | 2007-12-12 | 2012-02-21 | International Business Machines Corporation | Instruction for pre-fetching data and releasing cache lines |
US9164690B2 (en) * | 2012-07-27 | 2015-10-20 | Nvidia Corporation | System, method, and computer program product for copying data between memory locations |
US9547553B1 (en) | 2014-03-10 | 2017-01-17 | Parallel Machines Ltd. | Data resiliency in a shared memory pool |
US9781027B1 (en) | 2014-04-06 | 2017-10-03 | Parallel Machines Ltd. | Systems and methods to communicate with external destinations via a memory network |
US9690713B1 (en) | 2014-04-22 | 2017-06-27 | Parallel Machines Ltd. | Systems and methods for effectively interacting with a flash memory |
US9594688B1 (en) | 2014-12-09 | 2017-03-14 | Parallel Machines Ltd. | Systems and methods for executing actions using cached data |
US9529622B1 (en) | 2014-12-09 | 2016-12-27 | Parallel Machines Ltd. | Systems and methods for automatic generation of task-splitting code |
US9781225B1 (en) | 2014-12-09 | 2017-10-03 | Parallel Machines Ltd. | Systems and methods for cache streams |
US9753873B1 (en) | 2014-12-09 | 2017-09-05 | Parallel Machines Ltd. | Systems and methods for key-value transactions |
US9632936B1 (en) | 2014-12-09 | 2017-04-25 | Parallel Machines Ltd. | Two-tier distributed memory |
US9639473B1 (en) | 2014-12-09 | 2017-05-02 | Parallel Machines Ltd. | Utilizing a cache mechanism by copying a data set from a cache-disabled memory location to a cache-enabled memory location |
TWI590053B (zh) * | 2015-07-02 | 2017-07-01 | 威盛電子股份有限公司 | 選擇性預取實體接續快取線至包含被載入分頁表之快取線 |
US10067713B2 (en) | 2015-11-05 | 2018-09-04 | International Business Machines Corporation | Efficient enforcement of barriers with respect to memory move sequences |
US10152322B2 (en) * | 2015-11-05 | 2018-12-11 | International Business Machines Corporation | Memory move instruction sequence including a stream of copy-type and paste-type instructions |
US10042580B2 (en) | 2015-11-05 | 2018-08-07 | International Business Machines Corporation | Speculatively performing memory move requests with respect to a barrier |
US9996298B2 (en) | 2015-11-05 | 2018-06-12 | International Business Machines Corporation | Memory move instruction sequence enabling software control |
US10126952B2 (en) | 2015-11-05 | 2018-11-13 | International Business Machines Corporation | Memory move instruction sequence targeting a memory-mapped device |
US10346164B2 (en) | 2015-11-05 | 2019-07-09 | International Business Machines Corporation | Memory move instruction sequence targeting an accelerator switchboard |
US10241945B2 (en) | 2015-11-05 | 2019-03-26 | International Business Machines Corporation | Memory move supporting speculative acquisition of source and destination data granules including copy-type and paste-type instructions |
US10331373B2 (en) * | 2015-11-05 | 2019-06-25 | International Business Machines Corporation | Migration of memory move instruction sequences between hardware threads |
US10140052B2 (en) | 2015-11-05 | 2018-11-27 | International Business Machines Corporation | Memory access in a data processing system utilizing copy and paste instructions |
CN111782273B (zh) * | 2020-07-16 | 2022-07-26 | 中国人民解放军国防科技大学 | 一种提高重复程序执行性能的软硬件协同缓存装置 |
CN112286577B (zh) * | 2020-10-30 | 2022-12-06 | 上海兆芯集成电路有限公司 | 处理器及其操作方法 |
US12050915B2 (en) * | 2020-12-22 | 2024-07-30 | Intel Corporation | Instruction and logic for code prefetching |
US11853237B2 (en) * | 2021-11-19 | 2023-12-26 | Micron Technology, Inc. | Input/output sequencer instruction set processing |
CN117640262B (zh) * | 2024-01-26 | 2024-04-09 | 杭州美创科技股份有限公司 | 数据资产隔离方法、装置、计算机设备及存储介质 |
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US6915415B2 (en) * | 2002-01-07 | 2005-07-05 | International Business Machines Corporation | Method and apparatus for mapping software prefetch instructions to hardware prefetch logic |
US7080211B2 (en) * | 2002-02-12 | 2006-07-18 | Ip-First, Llc | Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory |
US7380103B2 (en) * | 2002-04-02 | 2008-05-27 | Ip-First, Llc | Apparatus and method for selective control of results write back |
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-
2003
- 2003-04-02 US US10/405,980 patent/US7111125B2/en not_active Expired - Lifetime
- 2003-10-20 TW TW092128965A patent/TWI257067B/zh not_active IP Right Cessation
- 2003-12-15 EP EP03257873.4A patent/EP1465077B1/en not_active Expired - Lifetime
-
2004
- 2004-01-14 CN CNB200410001593XA patent/CN100461135C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1465077A3 (en) | 2007-12-05 |
EP1465077B1 (en) | 2018-05-09 |
CN100461135C (zh) | 2009-02-11 |
US7111125B2 (en) | 2006-09-19 |
TW200421175A (en) | 2004-10-16 |
US20030229763A1 (en) | 2003-12-11 |
EP1465077A2 (en) | 2004-10-06 |
CN1514374A (zh) | 2004-07-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |