TWI256560B - A system with dynamic adjustable coprocessor numbers - Google Patents
A system with dynamic adjustable coprocessor numbersInfo
- Publication number
- TWI256560B TWI256560B TW093117161A TW93117161A TWI256560B TW I256560 B TWI256560 B TW I256560B TW 093117161 A TW093117161 A TW 093117161A TW 93117161 A TW93117161 A TW 93117161A TW I256560 B TWI256560 B TW I256560B
- Authority
- TW
- Taiwan
- Prior art keywords
- coprocessor
- plural
- coprocessors
- instructions
- main processor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093117161A TWI256560B (en) | 2004-06-15 | 2004-06-15 | A system with dynamic adjustable coprocessor numbers |
US11/041,302 US20050278504A1 (en) | 2004-06-15 | 2005-01-25 | System capable of dynamically arranging coprocessor number |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093117161A TWI256560B (en) | 2004-06-15 | 2004-06-15 | A system with dynamic adjustable coprocessor numbers |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200540642A TW200540642A (en) | 2005-12-16 |
TWI256560B true TWI256560B (en) | 2006-06-11 |
Family
ID=35461860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093117161A TWI256560B (en) | 2004-06-15 | 2004-06-15 | A system with dynamic adjustable coprocessor numbers |
Country Status (2)
Country | Link |
---|---|
US (1) | US20050278504A1 (zh) |
TW (1) | TWI256560B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101872336B (zh) * | 2010-05-31 | 2011-12-21 | 浙江大学 | 基于主从架构的协处理器高效执行的装置 |
US9183614B2 (en) * | 2011-09-03 | 2015-11-10 | Mireplica Technology, Llc | Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets |
US10606587B2 (en) * | 2016-08-24 | 2020-03-31 | Micron Technology, Inc. | Apparatus and methods related to microcode instructions indicating instruction types |
US11263014B2 (en) * | 2019-08-05 | 2022-03-01 | Arm Limited | Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4994961A (en) * | 1983-04-18 | 1991-02-19 | Motorola, Inc. | Coprocessor instruction format |
-
2004
- 2004-06-15 TW TW093117161A patent/TWI256560B/zh active
-
2005
- 2005-01-25 US US11/041,302 patent/US20050278504A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW200540642A (en) | 2005-12-16 |
US20050278504A1 (en) | 2005-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2429554A (en) | Method and apparatus to vectorize multiple input instructions | |
HK1070964A1 (en) | Method of communicating across an operating system | |
WO2007021704A3 (en) | Application acceleration using heterogeneous processors | |
WO2005008410A3 (en) | Programmable processor and method with wide operations | |
WO2004006060A3 (en) | Statically speculative compilation and execution | |
TW200705266A (en) | System and method wherein conditional instructions unconditionally provide output | |
GB2481567A (en) | Unpacking packed data in multiple lanes | |
MY137496A (en) | Aliasing data processing registers | |
WO2002037264A3 (en) | Reconfigurable processing system and method | |
ATE475930T1 (de) | Verzweigungsbefehl für einen mehrfachverarbeitungsprozessor | |
GB201213316D0 (en) | Exploiting an architected last-use operand indication in a computer system operand resource pool | |
TW200707178A (en) | Reducing power by shutting down portions of a stacked register file | |
BRPI0608750A2 (pt) | método e sistema emitir e processar instruções superescalar e vliw misturadas | |
IES20080198A2 (en) | A processor | |
WO2006094196A3 (en) | Method and apparatus for power reduction in an heterogeneously- multi-pipelined processor | |
TW200636581A (en) | Methods and apparatus for instruction set emulation | |
TW200506718A (en) | Multi-pipe dispatch and execution of complex instructions in a superscalar processor | |
GB0328542D0 (en) | Data element size control within parallel lanes of processing | |
US8028150B2 (en) | Runtime instruction decoding modification in a multi-processing array | |
TW200509612A (en) | Data packet arithmetic logic devices and methods | |
GB2436499A (en) | Evalutation unit for single instruction, multiple data execution engine flag registers | |
WO2006012305A3 (en) | Bank assignment for partitioned register banks | |
TWI256560B (en) | A system with dynamic adjustable coprocessor numbers | |
WO2006075286A3 (en) | A processor and its instruction issue method | |
WO1999031579A3 (en) | Computer instruction which generates multiple data-type results |