1255508 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種多晶石夕薄膜之製作方法，應用於薄膜電晶體， 斗寸別瓦指一種可提高晶粒均勾性之多晶矽薄膜之製作方法。 【先前技術】 有鑑於未來主動式矩陣液晶顯示器及有機發光二極體顯示器是使 用低溫多晶㈣膜電晶體技術，而現今低溫多晶㈣膜電晶體彼此間 具有電性良好但雛不均勻之問題，級善通道間多晶”膜之不均 勻丨月况隶大目;f示疋控制多晶石夕晶粒的尺寸與分佈距離。 2000年韓國漢城大學曾提出—種多晶_膜的製作方法，乃利用 紹金屬之高反射率來當作側向成長之金屬冷源。請依序參照第iA〜W 圖所不’其製作流程是先在氧化層基板1〇上鑛上8〇奈米（⑽）厚之 非晶㈣膜丨！，接著，用紐12作上阻擋層_後，崎子佈值機佈 值η離子（第1A圖），在原佈值位置上鑛上2〇〇〇 308奈米時’具95 %以上之反射率）後再去掉光阻12，由於二屬= ’、（子之反射率及‘熱性質，在準分子雷射退火後，紹金屬13所在地 謂為冷源，而融、熔非晶碎薄膜u將以此冷源向外結晶成長，至和相 础之結晶晶粒碰撞為止（第1B、1(：圖）。 古此法可有效控制晶粒在—維方向之成長，但其所作出之晶粒結晶 方向，只屬於-維方向，並無法準確控制至 =法達到晶粒結晶大小一致之要求，對於控制通二 以達凡件之均勻性目的仍無法掌控。 曰年％國漢城大學則利用空氣較基板難導熱之原理，來製作多 ΐ膜成長之薄膜電晶體。如第2圖所示，此方法所製作的多晶石夕 用’是在基板20上先錢上50奈米厚之金屬犧牲層，然後，利 】兒水，匕學氣相沉積（Ρ獅）方式在·。c沉積ι〇〇奈米心 G R士者，在28〇(：沉積80奈米之非晶石夕薄膜22,在450°C下去氫 區止準分子雷射退火時氫爆的發生，再沉積—層薄氧化層23 〇σ曰、退火導致浮動（floating)非晶石夕層之斷裂，最後，將金 5 1255508 屬犧牲層_掉，此時會露出空氣間隙（air gap) 24，再進行準八子 ==火，_空氣較基板2Q難導熱之原理，基板2g處會帶走二 :…、里’形成-冷源，此時料從冷源處向内沿著空氣間隙24結 曰a ° -维=所=出之晶粒似.維方向延伸，無法達至均勻性要求之 j或者二維方向，在製程中’空氣間隙上之薄膜層間，易因薄膜間 、祕係數不同而導致準分子雷射退火時，造成薄膜間材料岸力不 …2薄部呈現中空狀態’紐_出現裂痕影響製程穩定度。 炫石夕在ϋ 明人也曾以氮氧切(碰)作為吸熱層，來增加融 合夕在、、、口日日日守之尺寸。請依序參照第3A〜3D圖所示，其 在基板30底部成長氮氧化碎吸埶層&彳第 了 Γ作為絕緣層32,可阻隔吸議===; 緩融炫卿成小晶粒結晶，進-步增加大晶 叩同^月匕，而後’在絕緣層32上先沉基棒狀之非晶石夕層33 (第 分子雷射退火後，此層將先變成多_ J 50不未之非晶石夕層35，在第二次準分子雷概，藉由 自4之誘導及底部吸熱層31之作用，將使得非晶石夕層35結晶成大曰 粒之多晶矽層36(第況圖）。然 曰、、口日日曰曰 ^程度，但仍細獅在另雖方、ir=、可輕10微米⑽） 【發明内容】 反 f作t以m題，本發明的主要目的在於提供―種多日日日A«之 成長則排列之導熱層當作冷源，誘使非晶⑪薄膜結晶 伽，藉以大體上解決先前技術存在之缺失。 控制多的在於提供—種多㈣薄膜之製作方法，可透過 可改盖：曰的結晶程度，以控制多晶矽薄膜達到電性均勻，進而 文^夕日曰矽溥膜電晶體之電性。 包含==的广务明所揭露之多晶㈣膜之製作方法， I百先’提供—基板，'紐，於基板上a積吸熱層， 6 I2555〇8 上沉積絕緣層，再沉積非晶石夕薄膜於絕緣層上，且 稭由心緣料1¾絕吸熱層對於_子結晶成_ 則排列之導熱層作為冷源，最後進 制用儿積規 之源的t心再結晶往外成長，並形成為晶粒以規則性排列 將導熱層去除’而此步驟並不會影響多晶石夕 性，於疋，可以有效控膜電晶體之多晶㈣膜通道内的 j數目以及晶界數目，並可以穩定的控制薄膜電晶體之電性，而改 善整個驅誠路元狀均自性，在產業上雜大_倾。1255508 IX. Description of the invention: [Technical field of the invention] The present invention relates to a method for producing a polycrystalline stone film, which is applied to a thin film transistor, and a polycrystalline silicon film which can improve the uniformity of crystal grains. How to make it. [Prior Art] In view of the future, active matrix liquid crystal displays and organic light-emitting diode displays use low-temperature polycrystalline (tetra) film transistor technology, and today's low-temperature polycrystalline (tetra) film transistors have good electrical properties but are not uniform. The problem is that the polycrystalline film between the channels is not uniform. The film is not uniform. The size and distribution distance of the polycrystalline stone are controlled. In 2000, Seoul University of Korea proposed a polycrystalline film. The production method is to use the high reflectivity of the metal as a metal source for lateral growth. Please refer to the iA~W diagram in sequence. The production process is first on the oxide substrate 1 Nano ((10)) thick amorphous (four) membrane 丨!, and then, with the New 12 as the upper barrier _, the value of the scorpion cloth value η ion (1A), at the original cloth value position on the mine 2〇 〇〇 308 nm when 'have more than 95% reflectivity' and then remove the photoresist 12, due to the two genus = ', (child's reflectivity and 'thermal properties, after excimer laser annealing, Shao Metal 13 location It is called a cold source, and the molten and melted amorphous film u will crystallize outward from this cold source. , until the collision with the crystal grains of the phase (1B, 1 (:). This method can effectively control the growth of grains in the -dimensional direction, but the crystal grain direction of the grain is only - dimensional The direction, and can not accurately control to = the method to achieve the same crystal grain size requirements, for the control of the second to achieve the uniformity of the pieces of the purpose can not be controlled. In the year of the National University of Seoul, the use of air than the substrate is difficult to conduct heat, To make a multi-film grown thin film transistor. As shown in Fig. 2, the polycrystalline stone produced by this method is a 50 nm thick metal sacrificial layer on the substrate 20, and then, Children's water, drop-off vapor deposition (Ρ )) way in · c deposit 〇〇 〇〇 nano heart GR, at 28 〇 (: deposit 80 nm of amorphous stone eve film 22, at 450 ° C down In the hydrogen region, the hydrogen explosion occurs during the laser annealing of the quasi-molecule, and the redeposition of the thin oxide layer 23 〇σ曰, annealing causes the fracture of the floating amorphous layer, and finally, the gold 5 1255508 is a sacrificial layer _ Drop, the air gap will be exposed at this time, and then the quasi-eight son == fire, _ empty Compared with the principle that the substrate 2Q is difficult to conduct heat, the substrate 2g will take away two:..., in the 'formation-cold source, at this time, the material is cooled from the cold source to the inside along the air gap 24 a ° - dimension = = The grain appears in the dimension direction and cannot reach the uniformity requirement j or the two-dimensional direction. During the process, the film layers on the air gap are prone to excimer laser annealing due to different film and secret coefficients. The surface of the material between the films is not... 2 thin parts appear hollow state 'New_ cracks affect the process stability. Hyun Shi Xi in the Ming Dynasty people also used nitrogen oxide cut (touch) as the heat absorption layer to increase the fusion of the evening, The size of the mouth and the day and the day. Please refer to the 3A to 3D drawings in sequence, and the nitrogen oxide powder absorption layer & the first layer is grown as the insulation layer 32 at the bottom of the substrate 30, which can block the suction == =; 融 炫 炫 成 成 成 成 成 成 成 成 成 成 成 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫 炫This layer will first become a multi-J 50 not-existing amorphous stone layer 35, in the second excimer Lei, by the induction of 4 and the bottom The function of the heat absorbing layer 31 is such that the amorphous slab layer 35 is crystallized into a polycrystalline bismuth layer 36 of a large granule (photograph). Then, the mouth is 日 曰曰 ^ degree, but still the lion is in the other side, ir =, can be light 10 microns (10)) [Summary of the content] Anti-f for t to m, the main purpose of the present invention is to provide - The multi-day and long-day A« growth is arranged as a heat source to induce the amorphous 11 film to crystallize, thereby substantially solving the lack of prior art. The control is mostly to provide a method for producing a multi-(four) film, which can be modified by the crystallization degree of the ruthenium to control the polycrystalline ruthenium film to achieve electrical uniformity, and then the electrical properties of the ruthenium film transistor. A method for fabricating a polycrystalline (tetra) film disclosed by Guangwu Ming, which includes ==, I Baishou 'provides a substrate, 'new, a heat-absorbing layer on the substrate, an insulating layer deposited on 6 I2555〇8, and then deposited amorphous The Shixi film is on the insulating layer, and the straw is made of a heat-conducting layer arranged by the core material to form a heat-conducting layer, and the heat-conducting layer arranged by the source of the product is recrystallized and grown outward. Forming the crystal grains to remove the heat conductive layer in a regular arrangement', and this step does not affect the polycrystalline stone, and the number of j and the number of grain boundaries in the polycrystalline (tetra) film channel of the film transistor can be effectively controlled. And it can stably control the electrical properties of the thin film transistor, and improve the whole self-sufficiency of the whole drive road, and it is mixed in the industry.
=對本發_目的、特徵及其魏有進—步的了解，兹配 合圖式砰細說明如下： 【實施方式】 如第4圖所示，說明本發騎提供之多晶㈣膜之製作方法的主 要流程，包含有下列步驟： Η :先，如步驟测’提供—基板，基板可選自玻魏板、絕緣基 板或半導縣板，織，如步㈣觸，形成吸錢於基板上，如步驟 S300 ’再形成絕緣層於讀層上，接著，如步驟湖，形成非晶石夕薄 膜於絕緣層上，再如步驟_，形成規麟狀導熱層於非晶㈣膜 上，隨後，如步驟S6GG，藉由退火熱處理，使非晶韻膜以導埶層為 中心再結晶向外成長，而形成具均勻性之多晶矽薄膜。 以下以-實施例詳細說明本發明之製程步驟，並請依序參照第 5Α〜5Η圖以及第6Α〜6C圖所示，本發明 製作方法包括下列步驟： 、 如第5Α圖所示，先提供一玻璃基板4〇。 如第5Β圖所示，再利用電漿輔助化學氣相沉積（pECVD)方式， 在溫度250°C下沉積500奈米之氮氧化石夕(Si〇N)吸熱層41於玻璃基板 40上。 接著，如第5C圖所示，仍用電漿輔助化學氣相沉積方式，在溫度 250°C下沉積1G奈米之氧化碎⑽χ)作為絕緣層42，以隔絕下層= 化矽之吸熱層41對於後續形成之融熔矽結晶成核的影響。 7 1255508 下‘ΠΠΐ： ’再用電聚輔助化學氣相沉積方式，在溫度航 如第5E圖與^夕=_43於絕緣層42上。 子晶體陣列之導熱屛44 再蒸鍍300奈米規則排列之鋁金屬光 然後，如第；圖4=二膜43上。 膜43以形成多晶石夕薄膜=圖士所叫吏用準分子雷射照射非晶石夕薄 44作為冷源、中心，。、 日t，非曰曰矽溥膜43融溶後會以導熱層 造成晶Μ彼此距=外錄結晶’並㈣賴_的結果， 所示。雖麸*每# 又’進—步形成均勻多晶矽薄膜45 ,如第6C圖 理的方气，亦^例疋^取準分子雷射退火(ELA)作為非晶石夕退火熱處 的，亦可以高溫爐退火來處理。 最後，如第R「同- 晶體。 回不，可再將導熱層44去除，以應用於薄膜電 熱處卜改ίί f1圖所示’移除麵層44之後’可再利用多次退火 轨# 44所賴45晶界突起部分之影響，以及誘使中間因導 ^自所===晶，當然，此退火熱處理之方 要可=同;==層Γ為其他具有吸熱作用之物質，只 質ΛΑ 士 5 J 、吧緣層42可為其他具有絕緣作用之物 貝層44可為金屬或其他具導熱、反射率良好之鮮，且導孰、 排列成域子晶體之顧狀 f㈣位置及83格大小，再加上底部吸熱層之使用， 之結晶幅S度，而充分熱源，減緩小晶粒之形成，增加大晶粒 可：二/成可以控制且電性均勻之多晶矽薄膜電晶體。此外， :一步心多曰：影響在其上製作薄膜電晶體電路之特性’可 ▲到夕曰曰石夕物電晶體通道内的晶粒大小以及晶界數目，可以 穩定的控㈣膜電β%Μ之電性，改善整個驅動電路元件之均勾性。 因此，»本發明所提供之多晶石夕薄膜之製作方法，係藉由規則 1255508 排列之導熱層的光子晶體陣列，來誘使非晶矽成長晶粒大小均勻之多 晶矽薄膜，可用於薄膜電晶體液晶顯示器或主動式矩陣有機發光顯示 器上。 & ”、、 曰再者，本發明可進一步有效控制薄膜電晶體之通道内晶粒大小與 晶界數目丄改善多晶矽電晶體間之電特性不一致現象，讓低溫多晶矽 產生更大範圍之應用，譬如，運用至主動式矩陣驅動元件上，且經由 上述晶粒控制，在主減矩陣鶴元件會有電流不做及益法 控制之現象發生。 ’ 一另外1本發明所製作之多晶料膜晶粒可以大到2微米，大幅提 ^晶顯示器及有機發光二極體（0LED)顯示器所用多晶石夕驅動電路 几件之均勻度。 明ΐΐίίΓ以前述之實施例揭露如上，然其並非用以限定本發 二之精神和範圍内，所為之更動與潤飾，均屬本發 專利Γ圍 關於本發明所界定之保護範圍請參考所附之申請 【圖式簡單說明】 ==顯之多晶鶴膜之製作流程示意圖，· 弟2圖係自知技術之多晶硬_之構造示意圖； 弟4圖係本發明所提供之多晶㈣ = 第5A〜5H圖為本發明之實施 =方去的4圖， 剖面圖；及 W味供之多晶石夕薄膜之製作方法之流程 第6A〜6C圖為本發明之實施例 夕 上視圖。 杈么、之夕日日矽溥膜之製作方法之流程 【主要元件符號說明】 10 基板 U 非晶參薄膜 12 光阻 紹金屬 9 13 基板 氧化層 非晶矽薄膜 氧化層 空氣間隙 基板 吸熱層 絕緣層 非晶矽層 多晶矽層 非晶矽層 多晶矽層 基板 吸熱層 絕緣層 非晶矽薄膜 導熱層 多晶矽薄膜 10=About the understanding of the purpose, characteristics and Wei Weijin step, the following is a detailed description of the following: [Embodiment] As shown in Fig. 4, the main method of manufacturing the polycrystalline (tetra) film provided by the present ride is described. The process includes the following steps: Η: First, if the step is to measure the 'providing-substrate, the substrate may be selected from a glass plate, an insulating substrate or a semi-conducting plate, and weaving, as in step (4), forming a suction on the substrate, such as Step S300' re-forms the insulating layer on the read layer, and then, as in the step lake, forms an amorphous slab film on the insulating layer, and then, as in step _, forms a ribbed heat conductive layer on the amorphous (four) film, followed by In step S6GG, the amorphous film is recrystallized and grown outward from the conductive layer by annealing heat treatment to form a uniform polycrystalline silicon film. The process steps of the present invention are described in detail below with reference to the embodiments. Referring to FIG. 5 to FIG. 5 and FIG. 6 to FIG. 6C, the manufacturing method of the present invention includes the following steps: As shown in FIG. A glass substrate 4 〇. As shown in Fig. 5, a 500 nm nitrous oxide (Si〇N) heat absorbing layer 41 was deposited on the glass substrate 40 by plasma assisted chemical vapor deposition (pECVD) at a temperature of 250 °C. Next, as shown in FIG. 5C, a plasma-assisted chemical vapor deposition method is used to deposit 1 G of nanometer oxidized slag (10) ruthenium at a temperature of 250 ° C as an insulating layer 42 to insulate the lower layer = the ruthenium-absorbing layer 41. The effect on the nucleation of the subsequently formed melted crystallization crystal. 7 1255508 The following 'ΠΠΐ:' is reused by electro-accumulation-assisted chemical vapor deposition on the insulating layer 42 at a temperature of FIG. 5E and FIG. The thermal conductivity 屛 44 of the sub-crystal array is further vapor-deposited with a 300 nm regular arrangement of aluminum metal light, and then, as shown in Fig. 4, on the second film 43. The film 43 is formed as a cold source and a center by forming a polycrystalline slab film. , day t, after the non-deuterium film 43 is melted, the result is that the heat transfer layer causes the crystal grains to be separated from each other = the outer crystal crystallization and the (four) ray _. Although the bran * every # step into the formation of a uniform polycrystalline silicon film 45, such as the 6C picture of the square gas, also ^ 疋 ^ take excimer laser annealing (ELA) as the amorphous stone annealing hot spot, also It can be treated by annealing in a high temperature furnace. Finally, as in the Rth "the same - crystal. Back, the heat-conducting layer 44 can be removed to apply to the thin film electric heating area. ίί f1 shows the 'removal of the surface layer 44' can be reused multiple annealing rails# The influence of the protrusions of the 45 grain boundary of the 44th layer, and the inducement of the middle cause by the === crystal, of course, the annealing heat treatment must be the same; == layer Γ is other substances with endothermic effect, only The material layer 5 J and the edge layer 42 may be other insulating objects. The shell layer 44 may be metal or other material with good thermal conductivity and good reflectivity, and the orientation and arrangement of the domain sub-crystals may be the f (four) position and 83 grid size, plus the use of the bottom heat absorption layer, the crystal width S degree, and sufficient heat source, slow the formation of small grains, increase the large crystal grain: two / can be controlled and electrically uniform polycrystalline germanium film transistor In addition, : one step at a time: affecting the characteristics of the thin-film transistor circuit on which it is made. ▲ ▲ ▲ 曰曰 曰曰 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 的 的 的 的 的 的 的 的 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕The electrical conductivity of β%Μ improves the uniformity of the entire driver circuit components. Therefore, the method for fabricating the polycrystalline zea film provided by the present invention is a photonic crystal array of a thermally conductive layer arranged by the rule 1255508 to induce a polycrystalline germanium film having a uniform crystal grain size and a uniform crystal grain size, which can be used for the thin film electricity. On the crystal liquid crystal display or the active matrix organic light-emitting display. & </ RTI> </ RTI> Further, the present invention can further effectively control the grain size and the number of grain boundaries in the channel of the thin film transistor, and improve the electrical characteristics between the polycrystalline germanium transistors. Phenomenon, the application of low-temperature polysilicon to a wider range of applications, for example, applied to active matrix drive components, and through the above-mentioned die control, there is a phenomenon in which the current subtractive matrix crane component has current and control. The film of the polycrystalline film produced by the other invention can be as large as 2 micrometers, and the uniformity of several pieces of the polycrystalline silicon driving circuit used for the crystal display and the organic light emitting diode (OLED) display can be greatly improved. The above-mentioned embodiments are disclosed above, but are not intended to limit the spirit and scope of the present invention, and the modifications and refinements thereof are all subject to the scope of protection defined by the present invention. The application [simplified description of the schema] == The schematic diagram of the production process of the polycrystalline crane film, the second diagram of the polycrystalline hard _ of the self-knowledge technology; the fourth diagram of the polycrystal provided by the invention (4) = 5A to 5H are the implementation of the present invention = 4, a sectional view; and a flow of a method for producing a polycrystalline stone film for W-flavors. Figs. 6A to 6C are views of an embodiment of the present invention. .杈 、 之 之 日 日 日 日 之 之 流程 流程 流程 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Amorphous germanium polycrystalline germanium amorphous germanium polycrystalline germanium substrate heat-absorbing layer insulating layer amorphous germanium thin film thermally conductive polycrystalline germanium film 10