TWI255093B - Multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer - Google Patents

Abstract

A multiple-sampling circuit is developed for measuring reflected voltage and discharge time of a transformer, in which the sample signals are used for generating hold voltages by alternately sampling the reflected voltage signal from the transformer. A buffer amplifier is coupled to the hold voltages to generate a buffer voltage from the higher voltage of the hold voltages. A switch periodically samples the buffer voltage to produce a voltage-feedback signal. The voltage-feedback signal is thus proportional to the output voltage of the transformer. A threshold signal added up the reflected voltage produces a level-shift signal. A discharge-time signal is generated as the switching signal is disabled. The discharge-time signal is disabled once the level-shift signal is lower than the voltage-feedback signal. The pulse width of the discharge-time signal is therefore correlated to the discharge-time of the transformer. The sample signals are only enabled to generate hold voltage during the enable period of the discharge-time signal.

Description

1255093 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a switching mode power supply. The present invention relates to a switching controller for a control circuit of a power supply. [Prior Art] Various power supplies have been used on the ground to provide a bold (four) pressure. Based on the safety test 4, an off-line _ine)t source is located between the secondary and secondary sides: electrical isolation must be provided. - Lighter and secondary (four) tuning (four) must be adjusted to stabilize the output voltage of the off-line power supply. In order to save the number of parts and the need to remove the secondary circuit, the primary side control technique has been disclosed, for example, U.S. Patent No. 4,302,803, issued May 24, 1981. SUMMARY OF THE INVENTION The main object of the present invention is to provide a fine-sampling number in a power supply switching controller for measuring the voltage signal and discharge time of the transformer, and the wire is not in the lower end of the psychoscope. Under the demand of light and bribe two picking stable (four), the ribs control the output of the power supply. In addition, the discharge of the medullary H _ scale ship (release i__a called the power supply is a vital signal, silk touch valley light (vaUey read # side step, and achieve soft switching (soft switching). Eight inventions - multiple times The sampling device is used in the switching controller of the power supply, and is connected to the auxiliary winding of the pressure, a pulse width modulation and shielding unit and the __ oscillating unit. The multiple sampling ι includes a time-delay unit. Connected to the pulse width modulation and masking unit, the receiving signal of the output of the wide-width masking unit is received, and a delay time signal is generated when the field is stopped, and the switching signal is outputted through the internal_inverter output. Switching signal. A signal generating unit, connected to the time unit, connected to the (10) time signal and the reverse cut 1255093, the signal number ' is simultaneously connected to the auxiliary winding of the transformer through a voltage dividing resistor to obtain the reflection on the auxiliary winding The voltage signal is used for outputting a discharge time signal, a first sample signal and a first sample number. A sampling unit is connected to the voltage dividing resistor, the vibration unit, the pulse width modulation and the masking And the signal generating unit receives the first sampling signal, the second sampling signal, the reflected voltage signal, the pulse signal of the oscillating unit output, and the pulse width modulation and the clearing unit output one of the clearing signals For outputting a voltage feedback signal, the sampling unit can alternately sample the reflected voltage signal according to the control of the first sampling signal and the second sampling signal, and output the voltage feedback signal. The above summary and the following detailed description are intended to be illustrative of the scope of the invention. [Embodiment] Please refer to the first figure, which is a schematic diagram of a conventional switching power supply circuit including a transformer 1G. The transformer 1G has an auxiliary winding Na, a secondary side winding Np and a secondary side winding primary side. The winding Np is connected to an input voltage VlN. The resistor 51 and the resistor 52 are formed.

1 can be expressed by the formula (1): The cut, the type of electricity "the road of the road to read the job to display the third picture of the above-mentioned situation, the -: under the side of the city of m electric power can be .... .......-............-...............(1) Inductance value of primary side winding Np of 1255093, T 〇n is switched in the above formula (1), and LP is the on-time of the transformer 10 signal VpWM. ...... The picture is called the second B picture. Once the switching signal VPWM is turned to the low level, 1〇 will be transmitted to the secondary side of the transformer 1(), and through the rectifier: to ^ __ input (four) V. So, the two undercuts are produced. In addition, the voltage signal Vaux is simultaneously generated on the auxiliary winding Na of the voltage of 10, and the waveform of each point signal of the knife-switched power supply circuit is displayed in the interval of the second picture. The peak current Isi of the secondary side switching current Is can be expressed by the equation (2): , (V〇+ VF) In the above equation (2), 'VG is the output voltage of the power supply; Vf is the smoothing of the rectifier 4G. The voltage IV, Ls is the secondary side winding of the pressure $1 ^ ^ (four) sense value; & is the discharge time of the transformer ' can also be expressed as the discharge time of the secondary side current 1 §. The voltage signal VAUX1 can be expressed by the equation (3): VAUX1=—x(V〇+ VF) --------------------------- ------------------------------- At the same time, store (four) Gu 1G energy age at the same time pass the _ 2G scale capacitance 0 Subsequent charging of the parasitic capacitance Q causes Vds to be generated at both ends, and the voltage Vds value can be obtained by the equation (4):

Tnp

VdS = V丨N + [―— X (Vo + ----------------------------

I NS In the above formula (4), TNA, TNP and TNS are the winding resistances of the auxiliary winding Na, the primary side winding NP and the secondary side winding Ns of the transformer 10, respectively. For the first picture, please refer to the second CS!, after the stored energy in the transformer 1G is completely released, the secondary side switching current IS system will drop to zero amps. At this time, the voltage-system will be higher than the input voltage vIN, and the voltage vDS will start to reverse-recharge the input voltage ViN. At this time, the waveform of each point signal of the switching power supply circuit is displayed in the time of the third figure. This interval. 1255093 During a period of 1^ cycle in the interval I, the voltage Vds will drop to a valley voltage. The slew rate at which the voltage Vds falls is determined by the resonance frequency fR. The resonant frequency center and the Tq period are obtained by the equations (5) and (6). fR = 1 2WKc:............................................. ....................(5) tq = _L· (4 x fR) 2 ..............-.. ..................................(6) where C: is the power switch 20 parasitic capacitance value. When the voltage Vds begins to drop, the voltage signal VAUX will begin to decrease. At this time, the voltage signal Vaux /, the voltage VDS is in a proportional relationship, and the relationship is as follows:

VaUX = ¥x(Vds Vin) ...............................-.......... ...... (!) The discharge time Tds of equation (2) is measured by switching the falling edge of 汛唬vPWM to the corner of the voltage signal (c〇mer) 1 to measure the discharge time Tds of equation (2). Referring to the first figure, resistors 51 and 52 form a resistor with a knife pressure of 'two resistors connected between the auxiliary winding & The reflected voltage signal VDET can be expressed as (8):

Vdet = R52 R51 + R52 X Vaux (8) where R52 is the resistance of resistors 51 and 52. Referring to the fourth figure, a block diagram of a control circuit in accordance with the present invention is shown. A multi-sampling device 700 for use in a switching controller of a power supply is connected to an auxiliary winding NA, a pulse width modulation and occlusion unit 5 (10) and an oscillating unit _ of the transformer ι. The multiple sampling device includes a time-delay unit, a signal generating unit, and a sampling unit. Referring to the fourth meter, the coffee extension element is connected to the pulse width and the blanking unit 500, and receives the pulse width modulation and the masking unit output & one of the switching signals, and the switching signal When the stop is stopped, a delay time signal Vdl is output, and at the same time, an internal inverter output is output-inverted switching "/VPWM. The signal generating unit is connected to the _ late unit lion, and the 1255093 receives the delay time signal vDL and the inverted switching signal /vPWM, and is connected to the auxiliary winding of the 33⁄4: voltage device through a voltage dividing resistor to obtain The reflected voltage signal vDET ' is used to output a discharge time signal SDS, a first sample signal Vspi and a second sample signal vSP2. The sampling unit 100 is connected to the oscillating unit 600, the pulse width modulation and occlusion unit 500, and the signal generating unit 200, and receives the first sampling signal Vspi, the second sampling signal VsP2, and the reflected voltage signal VDET. The oscillating unit 6 〇〇 outputs a pulse signal PLS and the pulse width modulation and the clearing unit 5 〇〇 output one of the clear signals CLR for outputting a voltage feedback signal vv. The sampling unit 100 alternately samples the reflected voltage signal VDET according to the control of the first sampling signal VSP1 and the second sampling signal VsP2, and outputs the voltage feedback signal Vv. The main object of the present invention is to provide an accurate sampling device for measuring the voltage signal and discharge time of a transformer in a power supply. There is no need for an optocoupler and a secondary side, a 疋 adjuster at the primary side of the transformer. 'Used' to control the output voltage and output current of the power supply. With reference to the first figure, please refer to the fifth figure, which is a schematic diagram of the multiple sampling circuit used in the present invention. The reflected voltage signal VDET is sampled by the evening to generate the voltage feedback signal Vv and the discharge time signal SDS. The voltage feedback signal Vv is accurately proportional to the output voltage V〇. The discharge time signal s 〇 s represents the discharge time Tds of the secondary side switching current Is. The voltage is immediately sampled and measured before the secondary side switching current Is is discharged to zero. Therefore, the change of the secondary side switching current Is does not affect the value of the forward pressure drop 乂1? of the rectifier 40. The signal generating unit 200 includes a first signal generator, a second signal generator, a threshold signal 156 and a sampling pulse generator 19, and the sampling pulse generator 19 generates a sampling pulse §fL The action used to perform multiple samplings. A threshold signal 156 plus a reflected voltage signal vDET produces a level shift reflection signal. The first signal generator includes a D-type flip-flop 171 and two AND gates 165 and 166 for generating a first sampled signal Vsp and a second sampled signal Vsp2. The first generation state of the brother includes a D-type flip-flop 17 〇, a NAND gate 163, an AND gate 164, and a comparator 155 for generating a discharge time signal sDS. Referring to the fifth figure, and in conjunction with the sixth figure, the time delay circuit 3 includes an inverter 161, 1255093, an inversion to 162, a current source 18 〇, a transistor (8), and a capacitor i82, when switching signals, deactivating , is the generation-delay time Td. The wheel end of the inverter 161 is provided by the switching signal 1, and the input end of the lining of the lining _ _ stomach 162, the 瞒 _, 丨 _ 164 164 of the brother-end and the 正 type flip-flop 17 〇 The end of the clock. The inverter _ output can be turned on j off the solar celestial body m. The valley 182 is connected in parallel with the transistor 181, and the current source (10) charges the capacitor 182. Therefore, the current of the turbulent source 18 与 and the capacitance of the capacitor 182 determine the delay time Td of the time delay circuit. The capacitor 182 further outputs the delay time signal &

The output of the D-type positive and negative n 17G is connected to the second end of the gating 164, and the output of the D-type (6) is reduced by SDS. When the switching signal ν_ is deactivated, the discharge time job & is enabled. The output of the NAND gate 163 is connected to the reset terminal of the D-type flip-flop 17〇, and the first input of the gate 163 is connected to the capacitor 182 to receive the second of the delay time signal Vdl〇nand (6). The input is connected to the output of the comparative stomach 155. The negative input of comparator i55 is provided by the quasi-recording reflection 峨. Comparing the positive input of the stomach 155 is provided by the voltage feedback Vv output from the transfer unit (10). For this reason, the handle is delayed for a time to read, and the displacement displacement 峨 is lower than the Vv, and the discharge time is 峨& In addition, as long as the switching signal Vpwm is enabled, the discharge time signal SDS is deactivated. The sampling pulse generator 190 generates a sampling pulse signal for supplying the clock terminal of the D-type flip-flop 171 and the third terminal of the AND gates 165 and 166. The 〇 input of the D-type flip-flop 171 is connected to the inverted output to form a divide-by-2 counter. The output terminal and the inverting output terminal of the D-type flip-flop 171 are connected to the second ends of the AND gates 165 and 166, respectively. The first ends of AND gates 165 and 166 are also

疋 Provided by the discharge time signal SDS. The fourth ends of AND gates 165 and 166 are provided by a delay time signal vDL. Therefore, the first sampled signal vspi and the second sampled signal VSp2 are generated according to the sampled pulse signal. In addition, during the enable period of the discharge time signal SDS, the first sampled signal vspi and the second sampled signal VSI>2 are alternately generated. However, the delay time Td is inserted at the beginning of the discharge time signal s〇s to disable the generation of the first sample signal VSP1 and the second sample signal vSP2. Therefore, during the period of the delay time Td, the first sampled signal vSP1 and the second sampled signal 10 1255093

Vsp2 is deactivated. The first sampling signal Vspi and the second sampling signal VSP2 alternately control the switch (2) and the switch I22 in the sampling unit 1 (8), while the sampling unit 100 alternately samples the voltage signal νΑυχ through the voltage dividing resistor to sample the reflected voltage signal vDET. At the same time, the voltage signal Va Xin charges the first capacitor 110 and the second capacitor ln, respectively, while transmitting the first capacitor: and the second capacitor 111 to obtain the first voltage across the first capacitor 110 and the second capacitor ln. Maintain voltage with ^2. The switch 123 is connected in parallel with the first capacitor 11 () as a discharge of the first capacitor ^. The switch 124 is connected in parallel with the second capacitor (1), and is used as a buffer for the second capacitor (1). The buffer amplifier is disposed in the sampling unit 100, and includes the operational amplifiers 1 and (5), the diodes 13 and 131, and the current source. 135. The positive terminals of the operational amplifiers 15A and (5) are connected to the first capacitor 110 and the second capacitor (1), respectively. The negative terminals of operational amplifiers 150 and (5) are coupled to the buffer amplification correction output. The diode BG is connected from the output of the operational amplifier 15Q to the output of the buffer = amplifier, and the diode 131 is connected to the output of the buffer amplifier by the output of the operational amplifier 151. Therefore, the buffer amplifier is connected to the first capacitor ug and the second capacitor 1U' for receiving the first sustain voltage and the second sustain voltage, and obtaining a higher sustain voltage to obtain a -buffer voltage 'current source 135 to end the action. . The switching residual 125 is connected to the buffer amplifier to receive the pulse signal PLS to turn on or off, and the buffer voltage 'samply sampled onto the output capacitor 115 is used to generate the voltage feedback signal %. The voltage feedback signal vv is thus proportional to the turn-on voltage % of the transformer. After the delay time i, the first sampling signal VSP1 and the second sampling signal ~ start to generate the first and second maintenance light, thus eliminating the Lai Vaux _ secret agent ike (four) claims. When the switching signal VPWM is deactivated and the power switch 2 is turned off, the voltage signal ^: will generate a voltage surge. “爹考^六图, when the secondary side switching current 1 § discharge to zero, the electric signal ¥ begins to fall, by the comparator 155 _ used to disable the discharge time signal & discharge time signal ' pulse 1255093 The wave width is thus proportional to the discharge time & of the secondary side switching current Is. The discharge time signal sDS is disabled, and the first sampled signal Vspi and the second sampled signal I are deactivated, and more The subsampling action is stopped. At this time, the sustain voltage generated at the output of the buffer amplifier is expressed as - end her. The scale voltage is thus positively related to the voltage signal vAUX. Sampling and measurement is performed before the secondary side switching current Is is zero. Maintaining the _ is to take the higher voltage of the first-turn cake and the second turn voltage. When the reflected voltage signal vDET has begun to decrease, the reflected voltage signal will be ignored. In addition, if the switch is called VPWM enabled, it can be confirmed that the 肋 峨 _ has the minimum on-time. The minimum on-time of the switching signal vPWM will ensure the minimum discharge time Tds 'multiple sampling The reflected voltage signal ν〇Ετ is sampled in 700. The discharge time TDS is proportional to the on-time T〇N of the switching signal VPWM. Reference equations (1), (2), (3) and the transformer primary side inductance value LS = (TNS/TNP) 2 X LP, discharge time TDS can be expressed as equation (9):

Tr^o - i V|N , D NS τ (ν^)χ?^χΤ〇Ν ---------------------------- ------------------------ Please refer to the seventh figure, which is a schematic diagram of the pulse width modulation and occlusion unit circuit of the present invention. The pulse width modulation and masking unit 5GG includes H circuit and cover circuit, and the ship width modulation circuit includes a NAND gate 5H, a D-type flip-flop 515, an AND gate 519, and inverters 512 and 518. Simultaneously with the fourth and sixth figures, the inverter 512 in the pulse width modulation circuit is connected to the oscillating unit 600 to receive the pulse signal PLS. The output of inverter 512 is coupled to the clock terminal of D-type flip-flop 515 for enabling switching signal VPWM. The output of the D-type flip-flop 515 is connected to the first end of the AND gate 519, the second end of the AND gate 519 is connected to the output of the inverter 512, and the gate 519 outputs the switching signal VpwM. The reset end of the !) type flip-flop 515 is connected to the output of the nand gate 5ΐ. The first end of the NAND gate 511 is provided by a reset signal RST for periodically deactivating the switching signal Vpwm. A voltage loop error amplifier 513 receives the voltage feedback signal

Vv is coupled to the output of the blanking circuit 52A by the second end of the reset signal RS1^NAND gate 511. 12 1255093 Referring back to the seventh diagram, the blanking circuit 520 includes a NAND gate 523, a current source 525, a capacitor cut, a transistor 526, and inverters 521 and 522. The occlusion circuit 52 receives the switching signal and outputs it to the input of the inverter 521 and the first end of the NAND 523. The output of inverter 52i controls the turn-on and turn-off of transistor 526. The anti-sweep output is connected to the second end of the Μ·gate 523. The NAND idle 523 outputs the blanking signal Vblk, and the current of the current source and the capacitance of the capacitor 527 determine the width of the pulse that covers the Vblk. The input of the inverter 518 is connected to the round output of the NAND idle 5B, and receives the blanking signal I for outputting the clear signal CLR. Referring to the sixth figure, the clear signal CLR and the blank base I are inverted, and the clear signal CLR is used to control the on and off of the switches 123 and 124 shown in the fifth figure. When the switching signal VPWM is enabled, the blanking circuit 520 outputs the blanking signal I so that the switching signal is disabled, that is, the D-type flip-flop 515 is prevented from being reset. When the switching signal vPWM is turned off, the voltage signal Va is reflected by the transformer 10. Therefore, the switching signal vPWM must maintain a minimum switching frequency to ensure the switching action of the transformer 1 , to sample the reflected voltage signal Vdet multiple times. Please refer to the eighth figure, which is a schematic diagram of the circuit of the oscillator of the present invention. The operational amplifier 2〇1, the resistor 210 and the resistor 250 form a voltage to current converter, and generate a reference current bo according to the reference voltage Vr£f. A plurality of transistors 251, 252, 253, 254 and 255 form a current mirror, and a charging current I"3 and a discharging current Id are generated according to the reference current bo. The first switch 23A is connected to the drain of the transistor 253 and the oscillating capacitor 215. The second switch 231 is connected between the oscillating capacitor 215 and the transistor 255. The first comparator 205 outputs a pulse signal PLS for determining the switching frequency. The second end of the second switch 232 provides a south threshold voltage γ Η. The first end of the fourth switch 233 provides a low threshold voltage VL. The second end of the third switch 232 and the fourth switch 233 are connected to the negative end of the first comparator 2〇5. The input end of the inverter 260 is connected to the first end. The output of the comparator 205 is used to generate the pulse signal PLS, and the inverter 260 outputs the inverted pulse signal / PLS. The pulse signal PLS is used to turn on or off the second switch 231 and the fourth switch 233, and the pulse is inverted. The wave signal / PLS is used to turn on or off the first switch 230 and the third switch 232. 13 1255093 In summary, the present invention provides a precision device for measuring the voltage transformation _ pressure signal and discharge time in the transformer Death, the output of the conversion = the essentials for the present invention The following is familiar with the art, and the structure can be rectified without departing from the spirit and scope of the present invention. From the pre-frequency, the various miscellaneous and changing the patent system and its equivalent transfer, It can be seen as a part of the __. [Simplified description of the drawings] and is referred to as a detailed description of the detailed specifications, and the accompanying drawings are used to clearly describe the present invention, a part of the following figures. The embodiments of the present invention are illustrated to explain the principles of the present invention. The first figure is a schematic diagram of a conventional switched power supply circuit, and the second is a power switch of the switched power supply circuit operating in the second mode of the conductive mode. For the switching power supply circuit _ operation in the interception diagram; , heart, = a C map county Le lion circuit god _ operating in the interception of the third map is the switching power supply circuit The fourth diagram is a schematic diagram of the control circuit of the present invention; the fifth diagram is a schematic diagram of the multiple sampling circuit used in the present invention; the sixth diagram is the main waveform diagram of the multiple sampling circuit of the present invention; The seven maps are The circuit diagram of the pulse width modulation and masking unit is invented; and the eighth diagram is the circuit diagram of the oscillator of the present invention. [Main component symbol description] 10 Transformer 20 transistor 1505093 40 rectifier 45 DC voltage regulator capacitor 51 resistor 52 resistor 100 Sampling unit 110 Capacitor 111 Capacitor 115 Capacitor 121 Switch 122 Switch 123 Switch 124 Switch 125 Switch 130 Diode 131 Diode 135 Current Source 150 Operational Amplifier 151 Operational Amplifier 155 Comparator 156 Critical Signal 161 Inverter 162 Inverter 163 NAND gate 164 AND gate 165 AND gate 166 AND gate 170 D-type flip-flop 171 D-type flip-flop 180 current source 181 transistor 182 capacitor 190 sample pulse generator 200 signal generation unit 201 operational amplifier 205 comparator 210 resistor 215 Capacitor 230 Switch 231 Switch 232 Switch 233 Switch 250 transistor 251 transistor 252 transistor 253 transistor 254 transistor 255 transistor 260 inverter 300 time delay unit 500 pulse width modulation and occlusion unit

15 1255093 511 NAND gate 512 513 voltage loop error amplifier 515 518 inverter 519 520 blanking circuit 521 522 inverter 523 525 current source 526 527 700 capacitor multiple sampling circuit 600 inverter D-type positive and negative AND gate Phase NAND gate transistor oscillation unit

Claims (1)

1255093 X. Patent application scope: 1. • Kind of eve: human sampling device, which enables the field control of the power supply, the auxiliary winding of the money regulator, the pulse width modulation and the obscuration of the monopole_New_, Including: 夂-time ship delay unit 'connected to the pulse width machine and the cover unit, the connection _ pulse width modulation soldier obscures the early read--alkali, and stops the charm in the domain __delay a time signal, wherein the switching signal is inverted by the mailing-inverting switching signal, wherein the switching signal is used to switch the transformer via a power-on relationship; - The mobile tiger generates the early 7G 'connected to the delay unit, receives the delay time signal and the inverted switching signal, and is connected to the winding of the variable (4) through the --pressure repair device to obtain the - reflection on the auxiliary winding Voltage 峨, an output-discharge time signal, a first sampling signal and a second sampling signal; a sampling unit connected to the voltage dividing resistor, the oscillating unit, the pulse width modulation and occlusion unit, and the signal The generating unit receives the first sampling signal, the second sampling signal, the reflected voltage nickname, a pulse signal of the oscillating unit output, and the pulse width modulation and the clearing signal output of the occlusion unit for Output a voltage feedback signal; The sampling unit is configured to alternately sample the reflected voltage signal according to the control of the first sampling signal and the second sampling signal, and output the voltage feedback signal. 2. The multi-sampling device of claim 1, wherein the signal generating unit comprises a threshold signal, the threshold signal plus the reflected voltage signal generating a level shift signal; a discharge time signal will be The switching signal is generated when the switching signal is disabled; when the level shift signal is lower than the voltage feedback signal, the discharging time signal is disabled; the pulse width of the discharging time signal is thus related to the voltage transformation | The discharge time is proportional to the relationship. 3. The multi-sampling device of claim 1, wherein the signal generating unit further comprises: a sampling pulse generator for performing a plurality of sampling operations to generate a sampling pulse signal; 17 1255093 a first--[the generator, in the period of the activation of the discharge time signal, the first sampling signal and the second sampling signal are alternately generated according to the sampling pulse signal; wherein the delay time is inserted in the discharging time signal -p-shaped, during the period of the delay time, the sampling signal is disabled; and - the second signal generates H for generating the discharging time signal; when the switching signal is deactivated, the discharging time is enabled; After the delay time, the level shift signal is lower than the voltage feedback subtraction, and the "suppression scale" S; the towel discharge signal may also be disabled, as long as the switching signal is enabled. 4. If you apply for a patent scope! The multiple sampling device of the item, wherein the first sampling signal and the The second sampling subtraction alternately controls the two switches to sample the reflected voltage signal while passing through the -first capacitance and the -second capacitance to obtain the -first sustain voltage and the second sustain voltage. 5. If the sampling unit includes a buffer amplifier, the first capacitor has no second capacitor, and the first sustain capacitor is used. The second sustain voltage and a higher sustain voltage are obtained to obtain a buffer voltage. 6. The multi-sampling device of claim 3, wherein the sampling unit further comprises a switching-switching connection to the buffer amplifier, and receiving the pulse wave control, through a round-out capacitor, The buffer is periodically sampled to generate the feedback signal. 7. The multi-sampling device as described in the scope of the patent application, wherein the sampling and measurement of the scale is stopped by multiple sampling of the reflected voltage-down. The multi-sampling device described in the patent application, wherein the switching signal has the most on-time; once the switching signal is enabled, the minimum on-time ensures a minimum discharge interval for sampling the reflected voltage signal multiple times. . 9. If the application is specifically for the μ sampling device, the cap switching signal has a switching frequency of ze to ensure the switching action of the transformer for sampling the reflected voltage 多次 18