1253722 九、發明說明： 【發明所屬之技術領域】 本發明係提供-祕像_糾製作方法，綠—種互補式金 氧半導體電晶體影像感測器的製作方法。 【先前技術】 • 互補式金氧半導體電晶體影像感測器㈣.已被大量_ 於數位電子郎巾。例赠奴狱錢轉㈣㈣影像感測 器以掃_等產品駐，秘型互氣錢半物電晶體影像感 測關趨帅機等產品為主。由於互補式錢轉體電晶體影 像感測器可利用互補式金氧半導體電晶體標準製程製作，又可利 用現有半導體設備和技術，故生產量持續增加中。 响參考第1圖，第1圖為習知技術中於半導體基底1〇〇上形成 • 互補式金氧半導體電晶體(CMOS)影像感測器(image sens〇r)14〇之 方法示意圖。如第1圖所示，半導體基底100包含複數個淺溝隔 離(shallowtrench isolation)120 以及複數個感光二極體(phot〇di〇⑽ 122 ’且各感光二極體丨22係與至少一相對應之金氧半導體電晶體 (未顯示）電連接。其中，淺溝隔離12〇係用來作為任兩相鄰之 感光一極體122之間的絕緣體(insulator)，以避免感光二極體122 因和其他元件相接觸而發生短路。 1253722 習知技術係先於半導體基底100上形成平坦化層1〇2以覆蓋感 光一極體122和金氧半導體電晶體（未顯示），接著於平坦化層 上形成；I 層104和複數個圖案金屬層124，再於介電層1〇4上形 成複數個圖案金屬層126以及介電層106。其中，金屬層〗24以及 金屬層126皆形成於淺溝隔離120的上方，以使得入射光（未顯 不）射入時可聚集於感光二極體122，而不發生散射，造成訊號干 擾(crosstalk)。而金屬層124、126係為多重金屬内連線脇vd interconnects)，作為金氧半導體電晶體等之電路連結之用，之後， •再於介電層106上形成護層(passivati〇n)108並沈積氮化矽層11〇， 以防止水氣進入元件區中。 然後’於氮化石夕層110上方形成複數個由紅色、綠色、藍色 (R/G/B)濾光圖案所構成彩色濾光陣列（c〇1〇rfiltera胃，CFA) 128 ’並分別位於各個感光二極體122上方，接著於彩色濾光陣列 128上方再形成一間隔層(spacer layer)112,並於間隔層112上方形 • 成一由壓克力材料(acrylatematerial)構成之聚合物層(未顯示）。最 後再進行一曝光、顯影以及熱回流(refl〇w)製程，以於相對應的彩 色濾光圖案上方之該聚合物層(未顯示)中形成複數個聚光鏡 (U-lens)134，完成互補式金氧半導體電晶體影像感測器14〇的製 作0 但是’習知之互補式金氧半導體電晶體影像感測器一直都存在 有解析度不足、干擾雜訊(cross talkn〇ise)等問題，故近年來各家製 1253722 造商都希望將發光二極體寬度/彩色濾光陣列至發光二極體厚度比 提高，以增加影像感測器的解析度，所以如何提高發光二極^寬 度/彩色濾光陣列至發光二極體厚度比是該領域的重要議題。 【發明内容】 本發明係提供—種影像感測器的製作方法，以解決上述問題。 、在本發明的最佳實施例中，係提供一種製作影像感測器的方 法，方法包域供—個轉縣底，且半導縣聽含像素陣列 區域與邏輯區域，於像素陣列區域之半導體基底中形成複數個感 光極體於半$體基底上進行多重金屬内連線製程，於像素 列區域和邏輯區域上沈積制，去除像素陣顺域上方的護層， 以及於像素陣列區域中形成複數個遽光陣列，並分別對應 二極體。 〜 。由於本^㈣像鱗顺财具有制，所以發光二極體寬度 =慮7舰發光二極體厚纽提高，使細_器的解析 飯南’纽解決触f知技術的問題。 【實施方式】 请參考第2圖至裳7|S1 ^ 底綱上形成互補^ 至第7圖為本發明於半導體基 s_r)240之方法土乳半導體電晶體(CM〇S)影像感測器 不思圖。如第2圖所示，半導體基底2〇〇上可概 1253722 分為像素陣列區域(pixel array area)I和邏輯區域(logic area)n。在像 素陣列區域I中，半導體基底200包含複數個淺溝隔離(shaii〇w trenchisolation)220 以及複數個感光二極體(photodiode)222，且各 感光二極體222係與至少一相對應之金氧半導體電晶體（未顯示） 電連接。其中，淺溝隔離220係用來作為任兩相鄰之感光二極體 222之間的絕緣體，以避免感光二極體222因和其他元件相接觸而 發生短路。 • 本發明係先於半導體基底200上形成一平坦化層202，以覆蓋 感光二極體222和金氧半導體電晶體（未顯示），接著於平坦化層 202上形成介電層204和複數個圖案金屬層224，再於介電層204 上形成複數個圖案金屬層226以及介電層206。其中，金屬層224 以及金屬層226皆形成於淺溝隔離220的上方，使得入射光（未 顯示）射入時可聚集於感光二極體222，而不發生散射，造成訊號 干擾(crosstalk)。而金屬層224、226係為多重金屬内連線㈣脇vd • interC〇nnects)，其可利用金屬濺鍍、蝕刻或銅製程加以製備，作為 金氧半導體電晶體等元件的電路連結之用。 接著，僅於邏輯區域π中之介電層206上，製作一金屬層227, 用末Μ作互補式金氧半導體電晶體影像感測器(cis)對外連接的導 線，以完成所需設計的多重金屬内連線(111_—如_騰你）。 然後於半$體基底200上方沈積護層^passivati〇n)2⑽，護層2⑽的 材質係由氧化物(0#)層卿成，其材質可為二氧化石夕、構矽酸 1253722 玻璃等。隨後於護層208上方旋轉塗抹(spin coating) —光阻舞 (photoresistlayer)(未顯示），再利用光罩(ph〇t()mask)(未顯示） 定義出像素陣列區域I和邏輯區域Π。例如，當光阻層（未顯示） 為正光阻(positivephotoresist)時，光罩（未顯示）能使像素陣列區 域I在曝光時被光照射，但是邏輯區域Π則不會被光照射。接著 再以顯影劑侵入(penetrate)光阻層（未顯示）使邏輯區域n上方形 成遮罩(mask)229，如第3圖所示。 請參閱第4圖，隨後對半導體基底2〇〇進行一蝕刻(etch)製程。 因為像素陣列區域I上方沒有遮罩229遮蔽，所以位於像素陣列區 域I的護層208會被钕刻去除，但是在邏輯區域π的護層2〇8則 會因為受到遮罩229的保護而被保留。在完成微影暨蝕刻製程之 後，隨即剝除(strip)遮罩229，形成如第5圖的結構。值得注意的 疋’由於像素陣列區域I不具有護層2〇8,但邏輯區域玎仍具有護 層2〇8，因此本發明可視產品結構、設計需求、實際用途之不同， 若邏輯區域II之金屬層227有裸露、需待加強保護的狀況，本發 明可選擇性地於半導體基底細上方再沈積一層介電層（未顯示^ 來保護金屬層227。 然後請參閱第6圖，於半導體基底2〇〇上沈積_氮化石夕層21〇, 用來阻擋水氣進入多重金屬内連線以及元件區中。接著再於邏輯 區域II形成®案化光阻層（未顯示），並進行—爛製程以形成一 接合墊(pad)開口（未顯示），通達邏輯區域π之金屬層。 1253722 如第7圖所示，於氮化矽層210上方依序形成紅色濾光陣列 (color filter array，CFA) 228、綠色濾光陣列230和藍色濾光陣 列232於相對應的感光二極體222上方，接著於彩色濾光陣列 228、230、232上方形成間隔層細3〇61^>^)212，並於間隔層212 上方形成一由壓克力材料(acrylate material)構成之聚合物層(未顯 示）。最後再進行一曝光、顯影以及熱回流(reflow)製程，以於相對 應的彩色濾光陣列228、230、232上方之該聚合物層中形成相對 應的聚光鏡(U-lens)234、236、238，完成互補式金氧半導體電晶體 > 影像感測器240的製作。 相較於習知技術，由於本發明之互補式金氧半導體電晶體影像 感測器240的像素陣列區域j不具有護層2〇8，所以發光二極體您 寬度/彩色濾光陣列228、230、232至發光二極體222厚度比提高， 習知技術中護層108至半導體基底1〇〇的厚度通常是34k至58k， 但本發明素陣列區域工不具有護層2〇8後，其介電層2〇6至半導體 I基底2GG厚度可達26k，使得影像_ ^ _析度提高，故可有效 解決習知技術所遭遇__，大幅改善互補式金氧半導體電晶 體影像感測器的干擾雜訊(cross talk noise)並提高解析度。 、斤C僅為本發明之較佳實施例，凡依本發明申請專利範圍 斤U之均等^化與修飾，皆應屬本發明之涵蓋範圍。 1253722 【圖式簡單說明】 第1圖係為習知技術中於半導體基底100上形成CMOS影像感測 器之方法示意圖。 第2圖至第7圖係為本發明於半導體基底上形成CM〇s影像感測 器之方法示意圖。 【主要元件符號說明】 100、200 102、202 104、106、204、206 108、208 110、210 112、·212 120、220 122、222 半導體基底 平坦化層 介電層 護層 氮化石夕層 間隔層 淺溝隔離 感光二極體 124、126、224、226、227 金屬層 128、228、230、232 彩色濾光陣列 134、234、236、238 聚光鏡 140、240 互補式金氧半導體晶體影像感測器 229遮罩1253722 IX. Description of the Invention: [Technical Field] The present invention provides a method for making a secret image correction method, and a method for fabricating a green-type complementary MOS transistor crystal image sensor. [Prior Art] • Complementary MOS transistor image sensor (4). Has been a large number of digital lang. For example, the gift of slavery money (4) (4) image sensor Esau _ and other products stationed, secret type of mutual gas money half-element crystal image sensing and trending handsome machine and other products. Since the complementary money-transferring transistor image sensor can be fabricated using a complementary MOS transistor standard process, and existing semiconductor devices and technologies can be utilized, the throughput continues to increase. Referring to Fig. 1, FIG. 1 is a schematic diagram showing a method of forming a complementary MOS image sensor (image sens〇r) 14 半导体 on a semiconductor substrate 1 习 in the prior art. As shown in FIG. 1, the semiconductor substrate 100 includes a plurality of shallow trench isolations 120 and a plurality of photodiodes (phot〇di〇(10) 122 ′ and each of the photodiode 丨 22 systems corresponds to at least one. The MOS transistor (not shown) is electrically connected, wherein the shallow trench isolation 12 is used as an insulator between any two adjacent phototransistors 122 to avoid the photodiode 122 A short circuit occurs in contact with other components. 1253722 The prior art forms a planarization layer 1 〇 2 on the semiconductor substrate 100 to cover the photoreceptor 122 and the MOS transistor (not shown), followed by the planarization layer. Forming thereon; an I layer 104 and a plurality of patterned metal layers 124, and then forming a plurality of patterned metal layers 126 and a dielectric layer 106 on the dielectric layer 1〇4, wherein the metal layer 24 and the metal layer 126 are both formed in shallow The upper side of the trench isolation 120 is such that incident light (not shown) can be concentrated on the photodiode 122 without scattering, causing crosstalk. The metal layers 124 and 126 are multi-metal. Connection threat vd inte Rconnects), as a circuit connection for a MOS transistor or the like, and then forming a cap layer 108 on the dielectric layer 106 and depositing a tantalum nitride layer 11〇 to prevent moisture from entering the device In the district. Then, a plurality of color filter arrays (c〇1〇rfiltera stomach, CFA) 128' composed of red, green, blue (R/G/B) filter patterns are formed above the nitride layer 110 and are respectively located Above each photodiode 122, a spacer layer 112 is formed over the color filter array 128, and is squared on the spacer layer 112. A polymer layer composed of an acrylate material is formed ( Not shown). Finally, an exposure, development, and thermal reflow process is performed to form a plurality of concentrating mirrors (U-lens) 134 in the polymer layer (not shown) above the corresponding color filter pattern to complete the complementary Manufacture of MOS transistor image sensor 14 0 0 However, the conventional complementary MOS transistor image sensor always has problems such as insufficient resolution and cross talk noise. Therefore, in recent years, each manufacturer's 1252722 manufacturer hopes to increase the thickness ratio of the LED width/color filter array to the LED to increase the resolution of the image sensor, so how to improve the LED width/color Filter array to light-emitting diode thickness ratio is an important issue in this field. SUMMARY OF THE INVENTION The present invention provides a method of fabricating an image sensor to solve the above problems. In a preferred embodiment of the present invention, a method for fabricating an image sensor is provided. The method includes a packet domain for the bottom of the county, and the semi-conducting county listens to the pixel array region and the logic region in the pixel array region. Forming a plurality of photodiodes in the semiconductor substrate to perform a multiple metal interconnect process on the half-body substrate, depositing on the pixel column region and the logic region, removing the cap layer above the pixel array, and in the pixel array region A plurality of neon arrays are formed and respectively correspond to the diodes. ~. Because this ^ (4) is like a scale, the width of the light-emitting diode = the increase of the thickness of the light-emitting diode of the 7 ship, so that the analysis of the fine _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ [Embodiment] Please refer to FIG. 2 to form a complementary ^ to the seventh embodiment of the present invention. FIG. 7 is a method of using the semiconductor substrate s_r) 240 for a semiconductor-based semiconductor transistor (CM〇S) image sensor. Do not think about it. As shown in Fig. 2, the semiconductor substrate 2 can be divided into a pixel array area I and a logic area n. In the pixel array region I, the semiconductor substrate 200 includes a plurality of shallow trench isolations 220 and a plurality of photodiodes 222, and each of the photodiodes 222 is associated with at least one gold. An oxygen semiconductor transistor (not shown) is electrically connected. Among them, the shallow trench isolation 220 is used as an insulator between any two adjacent photodiodes 222 to prevent the photodiode 222 from being short-circuited due to contact with other components. The present invention forms a planarization layer 202 on the semiconductor substrate 200 to cover the photodiode 222 and the MOS transistor (not shown), and then form a dielectric layer 204 and a plurality of layers on the planarization layer 202. A patterned metal layer 224 is formed on the dielectric layer 204 to form a plurality of patterned metal layers 226 and dielectric layers 206. The metal layer 224 and the metal layer 226 are formed above the shallow trench isolation 220, so that incident light (not shown) can be collected on the photodiode 222 without scattering, causing crosstalk. The metal layers 224 and 226 are multi-metal interconnects (4) vod • interC〇nnects), which can be prepared by metal sputtering, etching or copper processes, and used as circuit connections for components such as MOS transistors. Next, a metal layer 227 is formed only on the dielectric layer 206 in the logic region π, and the wires are externally connected by a complementary MOS transistor image sensor (cis) to complete the desired design. Multiple metal interconnects (111_—such as _Teng you). Then, a protective layer ^passivati〇n) 2(10) is deposited on the upper half of the body substrate 200, and the material of the protective layer 2 (10) is made of an oxide (0#) layer, and the material thereof may be a corrosive stone, a ruthenium acid 1252722 glass, or the like. . A spin coating - photoresistlayer (not shown) is then applied over the cover layer 208, and a pixel array area I and a logic area are defined using a reticle (ph〇t() mask) (not shown). . For example, when the photoresist layer (not shown) is a positive photoresist, a photomask (not shown) enables the pixel array region I to be illuminated by light upon exposure, but the logic region Π is not illuminated by light. A logic layer n is then squared into a mask 229 by a developer penetrating the photoresist layer (not shown), as shown in FIG. Referring to FIG. 4, an etch process is then performed on the semiconductor substrate 2A. Since there is no mask 229 masking above the pixel array region I, the sheath layer 208 located in the pixel array region I is removed by engraving, but the sheath 2〇8 in the logic region π is protected by the mask 229. Reserved. After the lithography and etching process is completed, the mask 229 is subsequently stripped to form the structure as shown in Fig. 5. It is worth noting that since the pixel array area I does not have the protective layer 2〇8, but the logical area 玎 still has the protective layer 2〇8, the present invention can be visually related to the product structure, design requirements, and practical use, if the logical area II The metal layer 227 has a condition of being exposed and needs to be strengthened. The present invention can selectively deposit a dielectric layer on the fine surface of the semiconductor substrate (not shown to protect the metal layer 227. Then, refer to FIG. 6 on the semiconductor substrate. 2 deposited on the _ 氮化 夕 夕 layer 21 〇, used to block water vapor into the multi-metal interconnect and the component area. Then form a photoresist layer (not shown) in the logic area II, and - The ruin process forms a pad opening (not shown) to the metal layer of the logic region π. 1253722 As shown in FIG. 7, a red filter array is sequentially formed over the tantalum nitride layer 210. , CFA) 228, green filter array 230 and blue filter array 232 above the corresponding photodiode 222, and then form a spacer layer fine above the color filter array 228, 230, 232. ^) 212, and at intervals Above the layer 212 is formed a polymer layer (not shown) composed of an acrylate material. Finally, an exposure, development, and reflow process is performed to form corresponding concentrating mirrors (U-lens) 234, 236 in the polymer layer above the corresponding color filter arrays 228, 230, 232. 238, Completing the fabrication of the complementary MOS transistor & image sensor 240. Compared with the prior art, since the pixel array region j of the complementary MOS transistor image sensor 240 of the present invention does not have the protective layer 2〇8, the light-emitting diode has a width/color filter array 228, The thickness ratio of 230, 232 to the light-emitting diode 222 is increased. In the prior art, the thickness of the protective layer 108 to the semiconductor substrate 1 is usually 34k to 58k, but after the interlayer of the present invention does not have the protective layer 2〇8, The thickness of the dielectric layer 2〇6 to the semiconductor I substrate 2GG can reach 26k, which improves the resolution of the image_^_, so it can effectively solve the problems encountered by the prior art __, greatly improving the complementary MOS transistor image sensing. The device's cross talk noise and improved resolution. The present invention is only a preferred embodiment of the present invention, and the equalization and modification of the patent application scope of the present invention are all within the scope of the present invention. 1253722 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a method of forming a CMOS image sensor on a semiconductor substrate 100 in the prior art. 2 to 7 are schematic views showing a method of forming a CM 〇 image sensor on a semiconductor substrate according to the present invention. [Main component symbol description] 100, 200 102, 202 104, 106, 204, 206 108, 208 110, 210 112, · 212 120, 220 122, 222 semiconductor substrate planarization layer dielectric layer coating layer nitride layer interval Shallow trench isolation photodiode 124, 126, 224, 226, 227 metal layer 128, 228, 230, 232 color filter array 134, 234, 236, 238 concentrating mirror 140, 240 complementary MOS crystal image sensing 229 mask