1253157 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種形成尺寸不同之導電凸塊的方法，特 別是提供一種形成尺寸不同之電鍍凸塊的方法。 【先前技術】 隨著晶圓級封裝技術的改進，於製作封裝上變得愈來愈 普遍使用晶圓級封裝。傳統的晶圓設計，係包含許多相同的晶片單 元’因此對應於封裝所需的連接墊與凸塊的尺寸亦相同。 然而’為了降低製程成本，考慮將不同的晶片設計置於同一晶圓 上日守對應於封裝所需的連接墊與凸塊的尺寸便有所變化，連接墊與 凸塊的尺寸雜減，亦可狀寸差異蚊。切的設㈣鎌傳統 封裝製程中可以會面臨若干問題。 舉例來說’當於晶圓上以電鑛方式形成導電凸塊時，由於凸塊的BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming conductive bumps of different sizes, and in particular to a method of forming plated bumps having different sizes. [Prior Art] With the improvement of wafer-level packaging technology, wafer-level packaging has become more and more popular in manufacturing packages. Conventional wafer designs contain many of the same wafer cells. The corresponding pads and bumps required for the package are also the same size. However, in order to reduce the cost of the process, it is considered that the different wafer designs are placed on the same wafer. The size of the connection pads and bumps required for the package varies, and the size of the connection pads and bumps is reduced. Can be different in size. Cut the design (4) 镰 Traditional packaging process can face several problems. For example, when a conductive bump is formed on a wafer by electro-minening, due to the bump
^寸相異’因此於相關錢條件下，相_電財於尺寸較大的導 7凸塊中所呈韻高度聰低。根據上述，晶圓上便形成高度相 導電凸塊’當與基板結合時，晶财較低的導電 ^ ” 導電凸塊，減可—-魅法形錢㈣z 成良率的降低，反而無法達到降低成本的目的。 進而造 【發明内容】 6 有鑑於上述背景中’有關晶圓級職中不同尺寸之導電凸 塊的6又计所需’於此提供―種高度相同之導電凸塊的形成方法 與結構’利用分階段電㈣方式，可以確保不同尺寸的導/ 凸塊具有相同的凸塊高度。 再者，爲了製作具有相同高度但不同尺寸之導電凸塊與結 構’於此提供—種高度相同之導電凸塊的形成方法，遮蓋第 -次電_填滿較小凸塊的位置後再進行後續的電錢，可以 形成高度一致但不同尺寸之導電凸塊。 根據上述之目的，本發明之_實施例，提供一種高度相 同之導電凸塊的形成方法與結構。—晶圓結構上具有一導電 連接結構’-第—遮罩層形成於導電連接結構上。部份的第 —遮罩層被移除以形成—第―開口與―第二開口暴露出部分 的導電連接結構’其中第—開口與第二開口的大小相異。電 錢-第-導電層填滿第―開口與填人第二開口中，之後—第 層形成㈣-遮罩層上。移除部份㈣二遮罩層以暴 露出第二開口’最後再電鍍一第二導電層填滿第二開口。 【實施方式】 、 g之员&例用不意圖詳細描述如下，在詳述本發明之實施例 0〇表面的挪會放大顯示並說明，然不應以此作為有限定 1253157 的 此外’在貫際的晶圓表面與方法中，可以包含此結構中其他 必要的部分。 其次，當本發明之實施例圖式中的各元件或結構以單一元件或 冓述4月日守，不應以此作為有限定的認知，即如下之說明未特別 強磁目上的限制時，本發明之精神與應用範圍可推及多數個元件或 結構並存的結構與方法上。 第- A至第—D _示為本伽之—實施織行凸塊製程的侧 面示意圖。參照第-A圖，—晶圓1〇上可分為第—區域如與第二 區域5b，根據賴所職的連接導電凸塊尺寸，例如凸塊直徑而言， 位於第㊣域5a的導電凸塊將小於位於第二區域5a的導電凸塊。此 外，於b曰圓10上’第一區域5a與第二區域5&可分別位於連續的兩 個部分，例如位於晶圓的一半圓表面上，或是第一區域5a與第二區 域5a各包含獨立的次區域且可彼此參布，視實際輯所需而定。 於晶圓10上以適當的方式形成若干金屬連接墊12a與 12b(connecting pad) ’例如紹接墊或銅接塾，分別分布於第一區域 5a與第二區域5a。之後一絕緣保護層丨4(passivation iayer)覆蓋於晶 圓10表面上並分別暴露出金屬連接墊；[2a與金屬連接墊i2b的若干 表面。接著，利用適當的方法，例如電鍍或濺鍍的方式，將導電連 接結構16覆蓋於絕緣保護層14與暴露出的金屬連接墊i2a與金 !253157 屬連接墊12b表面上形成-導電表面。於一實施例中，導電連接結 構16為-般多層的下凸塊金屬結構(UBM)，例如包含阻障層與潤 濕/黏著層，其導電材料視後續欲形成的聰凸塊或純凸塊而定。 之後，-遮罩層18_Sk layer)覆蓋於導電連接結構16上並以適 當的方式移除部分的遮罩層 18以形成若干開〇 2〇a(第_開口)與開口 20b(第二開口）分別值於金屬連接墊12a與金屬連接墊创的上方。 於-實施例中，遮罩層18為—感光乾膜以貼附方式覆蓋，利用一般微 影與侧方式移除。於另-實施例中，遮罩層18亦可為_液態光阻以 方疋塗方式覆盖，但本發明不限於上述。再者，於_實施例中，遮罩層 is的厚度範圍可從25微米(micron mete_⑽微米不等，視後續欲 形成之導電凸塊的高度岐，但本發明不限於上述。此外，開口取 與開口 20b則視後續欲形成之導電凸塊的直徑而定，開口寬度範圍可 從5微米(micron meter)到1毫米(m诎刪⑺不等。可以理解的是，由 於後績位料-區域5a的導電凸塊將小於位於第二區域如的導電凸 塊，因此，開口 20a的開口寬度小於開口勘的開口寬度。 " 參照第- B圖，-導電層22a與導電層挪，例如錫師〇1叫、 銅或錦等無錯金屬或合金材料，分別填滿開口施並填入但未填滿開 口 20b巾。於-貫施例中，導電層2如與導電層娜係以電錢的方 式進行。要說明的是，由於開口咖的開口寬度小於開口勘的開口 寬度’因此於相同的電鑛條件與時間下，當位於第—區域&的開口咖 9 1253157 20b中填入導電層22b 被導電層22a填科位於第二_5a的開口 但未被導電層22b填滿。 ，224心Ή目，另—糊23最初繼_罩層18、導 ^ 勸彳她物糊23以暴露 出開口 20b中的99Κ认— 士 式盘材m η 。於—細种，層23與鮮層18形成方 /…目°，但本發砸不限於兩者相同，亦可兩者互異，例如亦 ™板印刷方式塗布該遮罩層23於導電層咖及周圍之部份 =層町。此外，本發明之精神雖朗㈣層先後形成的遮罩層a 與遮罩層18，但無需過度考量對準度(啦__素，因為後續步 驟與對準度的關聯度不大。 口“、、弟D圖’另一導電層24覆蓋開口勘中的娜上以填滿開 口 fb。之後再依序移除10上所有的遮罩層23與遮罩層Μ以形成若 、、兒凸塊(22a與施24)分別位於金屬連接墊❿與金屬連接墊⑽ 的上方，即分別分布於第一區域Sa與第二區域以内。之後可再利用籲 Z處理導電層22a與導電層22_，並且以適當方式移除暴露出的 連接構16(圖上未不）。於一實施例中，導電層％與導電層咖 或導弘層22b形成方式與材料相同，但本發明並不限於兩者相同，亦 可兩者互異。根據上述本發明之精神所得的導電層與導電層MW% 的直經雖财Θ，但冑度可鱗；_。 10 根據上述，本發明之一實施例中提供一種高度相同之導電凸 塊的形成方法，一晶圓結構上形成一下凸塊金屬結構。一第一 光阻層形成於下凸塊金屬結構上，之後移除部份的第一光阻層 以形成至少一第一開口與一第二開口暴露出部分的下凸塊金屬 結構，其中第一開口與第二開口的大小相異。電鍍一第一導 電層填滿第一開口與填入第二開口中。接著，形成一第二光 阻層於第一遮罩層上。移除部份的第二光阻層以暴露出第二 開口，再電鍍一第二導電層填滿第二開口。 以上所述之實施例僅係為說明本發明之技術思想及特點，其目的 在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能 以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均 等變化或修飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第一 A至第一 D圖所示為本發明之一實施例進行凸塊製程中步 驟的側面示意圖。 【主要元件符號說明】 5a 第一區域 5b 第二區域 10 晶圓 12a 金屬連接塾 1253157 12b 金屬連接墊 14 絕緣保護層 16 導電連接結構 18 遮軍層 20a，b 開口 22a，b，24導電層 23 遮罩層^Individuality is different. Therefore, under the relevant money conditions, the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ According to the above, the highly conductive bumps on the wafer are formed. When combined with the substrate, the conductive conductive bumps with lower crystal money can reduce the yield of the singularity (four) z, but cannot be reduced. The purpose of the cost. Further, the invention provides a method for forming a conductive bump of the same height in the above-mentioned background, which is required to provide a conductive bump of different sizes in the wafer level. With the structure 'using the staged electric (four) method, it can be ensured that the different sizes of the guides/bumps have the same bump height. Moreover, in order to make the conductive bumps and structures of the same height but different sizes, the height is provided here. The same method of forming the conductive bumps, covering the position of the first-time electric_filling the small bumps and then performing the subsequent electricity money, can form conductive bumps of uniform height but different sizes. According to the above object, the present invention The embodiment provides a method and structure for forming a highly uniform conductive bump. The wafer structure has a conductive connection structure--the first mask layer is formed on the conductive connection The first portion of the mask layer is removed to form a first conductive opening structure of the first opening and the second opening. The first opening and the second opening are different in size. The conductive layer fills the first opening and the second opening of the filling, and then the first layer forms a (four)-mask layer. The partial (four) two mask layer is removed to expose the second opening 'final plating a second conductive The layer fills the second opening. [Embodiment] The member of g, the example of g is not described in detail below, and the surface of the embodiment of the present invention is enlarged and displayed in an enlarged manner, and should not be used as In addition to the definition of 1253157, in the continuous wafer surface and method, other necessary parts of the structure may be included. Secondly, when the elements or structures in the embodiments of the present invention are in a single element or description 4 The stipulations of the present invention should not be construed as limiting the scope of the present invention. The spirit and scope of the present invention can be applied to structures and methods in which a plurality of components or structures coexist. -A to D-D The side view of the process of performing the wedging bump process. Referring to Figure-A, the wafer 1 can be divided into a first region, such as a second region 5b, according to the size of the connecting conductive bumps, such as convex In terms of the block diameter, the conductive bumps located in the positive domain 5a will be smaller than the conductive bumps located in the second region 5a. Further, on the b circle 10, the first region 5a and the second region 5& The two portions, for example, are located on a half of the circular surface of the wafer, or the first region 5a and the second region 5a each include independent sub-regions and can be disposed of each other, depending on the actual needs. A plurality of metal connection pads 12a and 12b (connecting pads) are formed in an appropriate manner, such as a pad or a copper pad, respectively distributed in the first region 5a and the second region 5a. Thereafter, an insulating iayer is provided. Covering the surface of the wafer 10 and exposing the metal connection pads respectively; [2a and the surface of the metal connection pad i2b. Next, the conductive connection structure 16 is overlaid on the surface of the insulating protective layer 14 and the exposed metal connection pad i2a and the gold 253157 genus connection pad 12b by a suitable method such as electroplating or sputtering to form a conductive surface. In one embodiment, the conductive connection structure 16 is a multi-layered lower bump metal structure (UBM), for example, comprising a barrier layer and a wet/adhesive layer, and the conductive material is formed by a subsequent bump or pure convexity. Depending on the block. Thereafter, a mask layer 18_Sk layer is overlaid on the conductive connection structure 16 and a portion of the mask layer 18 is removed in an appropriate manner to form a plurality of openings 2 〇 a (openings) and openings 20 b (second openings) The value is respectively above the metal connection pad 12a and the metal connection pad. In the embodiment, the mask layer 18 is - the photosensitive dry film is covered by attachment, removed by general lithography and sidewise. In another embodiment, the mask layer 18 may also be covered with a liquid photoresist, but the invention is not limited to the above. Furthermore, in the embodiment, the thickness of the mask layer is may range from 25 micrometers (micron mete_(10) micrometers, depending on the height of the conductive bumps to be formed later, but the invention is not limited to the above. And the opening 20b depends on the diameter of the conductive bump to be formed later, and the opening width can range from 5 micron (micron meter) to 1 mm (m 诎 ( (7). It can be understood that due to the post-performance material - The conductive bump of the region 5a will be smaller than the conductive bump located in the second region, for example, the opening width of the opening 20a is smaller than the opening width of the opening. " Referring to Figure-B, the conductive layer 22a and the conductive layer are moved, for example An electric metal or alloy material such as copper or brocade, which is filled with openings and filled in but not filled with openings 20b. In the embodiment, the conductive layer 2 is like a conductive layer. The method of electric money is carried out. It should be noted that since the opening width of the opening coffee is smaller than the opening width of the opening survey, it is filled in the opening area of the first area & 9 1253157 20b under the same electric ore condition and time. The conductive layer 22b is filled in by the conductive layer 22a Located in the opening of the second _5a but not filled by the conductive layer 22b. 224 hearts, the other paste 23 initially _ cover layer 18, guides her paste 23 to expose the 99 Κ in the opening 20b — 士式盘材 m η. In the fine-grained layer, the layer 23 and the fresh layer 18 form a square/... mesh, but the hairpin is not limited to the same, or may be different from each other, for example, also coated by a TM plate. The mask layer 23 is in the conductive layer and the surrounding part = layer. In addition, the spirit of the present invention is that the mask layer a and the mask layer 18 are formed successively, but the alignment is not excessively considered. __ prime, because the correlation between the subsequent steps and the degree of alignment is not large. Port ", brother D picture" another conductive layer 24 covers the opening of the survey to fill the opening fb. Then remove 10 in order All of the mask layer 23 and the mask layer are formed so that the bumps (22a and 24) are respectively located above the metal connection pads and the metal connection pads (10), that is, respectively distributed in the first area Sa and Within the two regions. The conductive layer 22a and the conductive layer 22_ may be processed by the use of the Z, and the exposed connection structure 16 is removed in an appropriate manner (not shown) In one embodiment, the conductive layer % is formed in the same manner and material as the conductive layer or the conductive layer 22b, but the present invention is not limited to the same as the two, or may be different from each other. According to the spirit of the present invention described above, According to the above, in one embodiment of the present invention, a method for forming conductive bumps of the same height, a wafer structure, is provided in a row of the conductive layer and the conductive layer MW%. Forming a bump metal structure thereon. A first photoresist layer is formed on the lower bump metal structure, and then removing a portion of the first photoresist layer to form at least a first opening and a second opening exposed portion The lower bump metal structure, wherein the first opening and the second opening are different in size. A first conductive layer is plated to fill the first opening and fill the second opening. Next, a second photoresist layer is formed on the first mask layer. A portion of the second photoresist layer is removed to expose the second opening, and a second conductive layer is plated to fill the second opening. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS First to first D are views showing a side view of a step in a bump process according to an embodiment of the present invention. [Main component symbol description] 5a First region 5b Second region 10 Wafer 12a Metal connection 塾1253157 12b Metal connection pad 14 Insulation protection layer 16 Conductive connection structure 18 Shield layer 20a, b Opening 22a, b, 24 Conductive layer 23 Mask layer