92twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種对高麼（High_voltage-tolerant， HVT)輸出/輸入電路，且特別是有關於一種具靜電放電 (electrostatic discharge，以下簡稱ESD)保護之耐高壓輸出 /輸入電路。 【先前技術】 現今電子電路中往往同時存在數種不同準位之工作 電壓。在不同準位之間傳遞訊號時，需要有適當之介面電 路作為緩衝。普遍應用於多電壓輸出/輸入電路(mixed_ voltage I/O circuit)中輸出驅動電路之堆疊式(stack) N型金 氧半場效電晶體（metal oxide semiconductor field-effect transistor，MOSFET)即被用以耐受高電壓，如圖1A所示。 例如，假設N型電晶體1丨丨與丨12之特性相同並且焊墊i 13 之訊號準位(例如3·3 V)大於電源電壓VDD (例如2.5V)， 則當電晶體111與112全部導通時，電晶體lu之源汲極 電壓或是電晶體112之源汲極電壓均等於焊墊訊號準位的 一半，因此可避免高電場應力效應，進而增加閘氧化層 (gate oxide)的可靠性。P型電晶體114之基體需保持浮接 (floating)，以防止焊墊113上較高電壓之訊號導入電源電 壓線VDD。 當正脈衝靜電流發生在焊墊113時，脈衝將使電晶 體111之汲極與基體間之接面崩潰，此崩潰電流將導致由 電晶體111與112所形成之等效電晶體進入導通狀態，然 1252574^2twf.doc/006 後將靜電流導引至接地電壓線vss。然而，已有報告顯 不針對由接地電壓vss線導引正脈衝靜電流之衝擊事件 (P_lve ESD/vss Zlppmg event)，圖 1A 之财高壓輸出/輪 入緩衝電路比—般輸輸人緩衝電路較胃因ESD而遭座 燒毀(damage)。 又 通常，輸出/輪入焊墊之電路被設計具有數組輸出/輪 入驅動電路，視需要而使用部分組數而將其餘組輸出/輪 入驅動電路禁能。其中，被禁能之輸出/輸人驅動電路稱 之為假輸出/輸入(dummy I/O)。圖1B是典型耐受高電壓 之輸出/輸入焊墊電路圖。請參照圖1B，圖中電路121即 代表被使用之輸出/輸入驅動電路，而電路122則代表被 不月b之輸出/輸入驅動電路（即"ο)。於正常狀況 下，透過電路121可傳遞訊號於内部電路115與焊墊113 之間。當正脈衝靜電流發生在焊墊113時，靜電流將分別 經由電路121與122而導引至接地電壓線VSS。然而， 電路121與122之觸發電壓並不相同，將導致其中接地之 電晶體開啟不一致。換句話說，當正脈衝靜電流發生時， 電路121之觸發電壓將小於電路122，而造成大量電流通 過電路121使得電路燒毀。 為了解決上述問題，美國專利第US 6747857 B1號 (2004年6月8日）提出「用於堆疊式NMOS靜電放電保 遵之箝位電路」（clamping circuit f〇r stacked NMOS ESD protection)’如圖ic所示。當正脈衝靜電流發生在焊墊ii3 時’靜電流將使箝位電路131中電晶體134導通，而造成 12525孫 2twf.doc/006 電路132中電晶體135之閘極接地。此時，電路Η】之觸 發電壓近似於電路133之觸發電壓，因此將靜電流自焊墊 113平均t由電路132與電路133導入接地電壓線vss， 而避免因大量電流通過電路121使得電路燒毀。然而，當 欲將正脈衝靜電流導引至接地電壓線vss時，此技術卻 造成電路132中之觸發電壓升高，致使無法及早觸發放電 路徑。 【發明内容】 本發明的目的就是在提供一種具靜電放電保護之耐 高壓電路，使得當正脈衝靜電流發生時，可以較小之觸發 電壓而及早觸發，以達到靜電放電保護之功能。 本發明的再一目的是提供一種靜電放電保護電路， 以車父小之觸發電壓而得以及早觸發，適時導引靜電流至接 地電壓線而避免燒毀内部電路。 本發明的又一目的是提供一種靜電放電保護電路， 藉由二極體之钳位特性使閘極電壓略高於接地電壓而得以 及早觸發，適時導引靜電流至接地電壓線而避免燒毁内部 電路。 本發明的另一目的是提供一種靜電放電保護電路， 以電晶體钳位閘極電壓，而達到上述諸目的。 本發明的再另一目的是提供一種靜電放電保護電 路，以電容分壓控制閘極電壓，而達到上述諸目的。 本發明提出一種具靜電放電保護之耐高壓電路，用 以接收積體電路之外部高電壓輸入訊號至焊塾。此耐高壓 7 1252578 14592twf.doc/006 電路包括第一至第六電晶體。第_電曰 耦接至焊墊。第二電晶體之第一源/、、乃:體之第一源/汲極 體之第二源級極，第二電晶體之第;^耦接至第一電晶 電晶體之第一源/汲極同時耦接至第雷，極接地。第三 體之閘極，第三電晶體之第二源你極^日體與第二電晶 四電晶體之第一源/汲極麵接至電源電壞Θ極接地第 輕接至焊墊，而第四電㈣之閘極職收’部^原壓= 訊號。第五電晶體之第一源/汲極耦接卜^„ 接至電源電壓。第六電晶體之第一源/沒』接= 第二源/汲極，第六電晶體之第二源/二:： 第電晶體之閘極則接收外部高電壓輸入訊號。 ^依照本發明的較佳實施例所述具靜電放電保護之耐 南壓電路，上述之第四電晶體係為Ρ型電晶體，並且第 〜第二電晶體、第五〜第六電晶體係為Ν型電晶體。依 照較佳實施例所述，第四電晶體之基體係浮接(fl〇ating)， 而第一〜第三電晶體、第五〜第六電晶體之基體接地。 本發明提出一種靜電放電保護電路，包括第一電晶 體、第二電晶體以及第三電晶體。第一電晶體之第一源/ 汲極耦接至嬋墊。第二電晶體之第一源/汲極耦接至第一 電晶體之第二源/汲極，而第二電晶體之第二源/汲極接 地。第三電晶體之第一源/汲極同時耦接至第一電晶體之 閘極與第二電晶體之閘極，而第三電晶體之第二源/汲極 以及閘極接地。 8 125257 各 2twf.doc/006 依照本發明的較佳實施例所述靜電放電保護電路， 上述之第一電晶體、該第二電晶體以及該第三電晶體係為 N型電晶體。依照較佳實施例所述，第一、第二以及第三 電晶體之基體接地。 本發明另提出一種靜電放電保護電路，包括第一電 晶體、第二電晶體以及二極體。第一電晶體之第一源/汲 極耦接至焊墊。第二電晶體之第一源/汲極耦接至第一電 晶體之第二源/汲極，第二電晶體之第二源/汲極接地。二 極體之陰極耦接至第一電晶體之閘極與第二電晶體之閘 極，二極體之陽極接地。 本發明又提出一種靜電放電保護電路，包括第一電 晶體、第二電晶體以及第三電晶體。第一電晶體之第一源 /汲極耦接至焊墊。第二電晶體之第一源/汲極耦接至第一 電晶體之第二源/>及極’苐二電晶體之第二源/没極接地。 第三電晶體之閘極以及第一源/汲極耦接至第一電晶體之 閘極與第二電晶體之閘極，第三電晶體之第二源/汲極接 地。 本發明再提出一種靜電放電保護電路，包括第一電 晶體、第二電晶體以及電容。第一電晶體之第一源/汲極 耦接至焊墊。第二電晶體之第一源/汲極耦接至第一電晶 體之第二源/汲極，第二電晶體之第二源/汲極接地。電容 之一端耦接至第一電晶體之閘極與第二電晶體之閘極，電 容之另一端接地。 I2525Z§92twf.doc/〇〇6 /本發明因利用電晶體I禺接於堆疊之各閘極， 使得堆疊NM0S之各閘極處於近似浮接狀態，因此當正 ，，靜^流發生時，可以較小之觸發電壓而及早觸發，適 時‘引靜電流至接地電壓線而達到靜電放電保護之功能。 ^為讓本發明之上述和其他目的、特徵和優點能更明 心員易1，下文特舉較佳實施例，並配合所附圖式，作詳細 5兄明如下。 ’ 【實施方式】 “圖2A是依照本發明較佳實施例所繪示之一種具靜電 放電保護之耐高壓(high-v〇itage_t〇lerant，HVT)輸出電路 圖。凊參照圖2A，耐受高電壓之堆疊NM〇s電路22〇接 收=體電路中内部電路21〇之外部高電壓輸入訊號以輸出 至焊墊240。堆疊NM0S電路22〇包括電晶體M4、 N型電晶體M5〜M6以及電阻R。電晶體M4之源極耦接 至電源電壓VDD，其汲極耦接至焊墊24〇，電晶體M4之 閘極接收内部電路210之外部高電屡輸入訊號。其中，電 晶體M4之基體係為浮接(£1〇此叩）。 電曰曰體M5之汲極耦接至焊墊240，而電晶體M5之 源極則耦接至電晶體M6之汲極。在本實施例中，電晶體 =5之閘極可以透過電阻R而耦接至電源電壓vDD。電 晶體Μ 6之源極接地，電晶體M 6之閘極接收内部電路2 i 〇 之外部咼電壓輸入訊號。在本實施例中，電晶體M5以及 M6之基體接地。 92twf.doc/006 靜電放電保護電路230可以利用輸出/輸入焊墊(1/0 pad)中未使用之剩餘組輸出/輸入驅動電路實施之，例如 配置NMOS電晶體至剩餘之輸出/輸入驅動電路中，使此 被配置之NMOS電晶體耦接至其中堆疊nm〇S之閘極。 如圖2A所示，靜電放電保護電路230包括N型電晶體 Ml〜M3。電晶體Ml之汲極耦接至焊墊240。電晶體M2 之汲極耦接至電晶體M1之源極，以及使電晶體M2之源 極接地。電晶體M3之汲極同時耦接至電晶體M1與M2 之閘極，並且使電晶體M3之源極與閘極接地。在本實施 例中’電晶體Ml〜]V13之基體接地。 在發生靜電流脈衝時，通常電晶體M6之閘極處於類 似浮接之狀態。藉由使電晶體M3保持截止狀態，使得靜 電放電保護電路230中電晶體M1與河2之閘極亦處於類 似浮接之狀態。因此，使得靜電放電保護電路23〇之靜電 放電觸發電壓(trigger voltage)接近於堆疊NMOS電路22〇 之觸發電壓，而可以在靜電流脈衝發生時一起打開放電路 徑以將靜電流導引至接地電壓線vss。 圖2B是依照本發明另一較佳實施例所繪示之一種具 靜電放電保護之耐高壓電，路圖。請參照圖2B，本實施j列 與圖2A相似，其中不同之處在於靜電放電保護電路2刈 中係以二極體D1之陰極耦接至各閘極，而將二極體 之陽極接地。 圖2C疋依照本發明再一較佳實施例所繪示之一種耳 靜電放電保護之耐高壓電路圖。請參照圖2C，本實施例 11 125257^92twf.doc/0〇6 與圖2A相似，其中不同之處在於靜電放電保護電路26〇 中係以N塑電晶體261之閘極與汲極同時耦接至電晶體 Ml與M2之閘極，並且將電晶體261之源極與基體接：。 圖2D是依照本發明另外一較佳實施例所繪示之一種 具靜電放電保護之耐鬲壓電路圖。請參照圖2D，本實施 例與圖2A相似，其中不同之處在於靜電放電保護電路27〇 中係以電容ci之一端耦接至電晶體M1與M2之閘極， 並且將電容ci之另一端接地。在此，電容C1例如以N 型電晶體施作之，亦即使電晶體之閘極當作電容之一端， 而將電晶體之源極、汲極與基體視為電容之另一端。 圖4是綠示圖2A之靜電放電保護電路230與圖1B 之習知電路122之漏電流與電壓關係之量測結果。於3.6V 偏壓下’漏電流從〇·245ηΑ略增加為〇·722ηΑ。 以下將利用HSPICE模擬圖2Α中靜電放電保護電92 twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a high-voltage-tolerant (HVT) output/input circuit, and more particularly to an electrostatic discharge (electrostatic discharge) , hereinafter referred to as ESD) protection of high voltage output / input circuit. [Prior Art] In today's electronic circuits, there are often several operating voltages of different levels. When transmitting signals between different levels, an appropriate interface circuit is required as a buffer. A stack of N-type metal oxide semiconductor field-effect transistors (MOSFETs) commonly used in output voltage circuits of a multi-voltage output/input circuit (mixed_voltage I/O circuit) is used. Withstand high voltages, as shown in Figure 1A. For example, assuming that the characteristics of the N-type transistor 1 丨丨 and 丨 12 are the same and the signal level of the pad i 13 (for example, 3·3 V) is greater than the power supply voltage VDD (for example, 2.5 V), when the transistors 111 and 112 are all When turned on, the source bucker voltage of the transistor lu or the source bucker voltage of the transistor 112 is equal to half of the pad signal level, thereby avoiding the high electric field stress effect and thereby increasing the reliability of the gate oxide. Sex. The base of the P-type transistor 114 needs to be floated to prevent a higher voltage signal on the pad 113 from being introduced into the power supply voltage line VDD. When a positive pulsed electrostatic current occurs in the pad 113, the pulse will cause the junction between the drain of the transistor 111 and the substrate to collapse, and the breakdown current will cause the equivalent transistor formed by the transistors 111 and 112 to enter the conduction state. Then, after 1252574^2twf.doc/006, the electrostatic current is directed to the ground voltage line vss. However, it has been reported that the impact event of the positive pulse electrostatic current (P_lve ESD/vss Zlppmg event) is guided by the ground voltage vss line, and the high voltage output/wheeled buffer circuit of FIG. 1A is more than the general input buffer circuit. The stomach is damaged due to ESD. Typically, the output/wheel-in pad circuit is designed with an array output/wheel drive circuit that uses partial sets of numbers and disables the remaining sets of output/wheel drive circuits as needed. Among them, the disabled output/input driver circuit is called dummy I/O. Figure 1B is a circuit diagram of an output/input pad that is typically tolerant of high voltage. Referring to Figure 1B, circuit 121 represents the output/input drive circuit used, and circuit 122 represents the output/input drive circuit (i.e., "ο). Under normal conditions, the transmission circuit 121 can transmit a signal between the internal circuit 115 and the pad 113. When a positive pulsed electrostatic current occurs in the pad 113, the electrostatic current will be directed to the ground voltage line VSS via circuits 121 and 122, respectively. However, the trigger voltages of circuits 121 and 122 are not the same, which will result in inconsistent turn-on of the transistors in which they are grounded. In other words, when a positive pulsed electrostatic current occurs, the trigger voltage of circuit 121 will be less than circuit 122, causing a large amount of current to pass through circuit 121 causing the circuit to burn out. In order to solve the above problem, U.S. Patent No. 6,747,857 B1 (June 8, 2004) proposes "clamping circuit f 〇 r stacked NMOS ESD protection" Ic shows. When a positive pulsed electrostatic current occurs in pad ii3, the electrostatic current will cause transistor 134 in clamp circuit 131 to conduct, causing the gate of transistor 135 in circuit 12 of 12525. At this time, the trigger voltage of the circuit 近似 is similar to the trigger voltage of the circuit 133, so the electrostatic current is averaged from the pad 113 by the circuit 132 and the circuit 133 to the ground voltage line vss, and the circuit is prevented from burning due to a large amount of current passing through the circuit 121. . However, when a positive pulsed electrostatic current is to be directed to the ground voltage line vss, this technique causes the trigger voltage in circuit 132 to rise, making it impossible to trigger the discharge path early. SUMMARY OF THE INVENTION An object of the present invention is to provide a high voltage resistant circuit with electrostatic discharge protection, so that when a positive pulsed electrostatic current occurs, a small trigger voltage can be triggered early to achieve electrostatic discharge protection. It is still another object of the present invention to provide an electrostatic discharge protection circuit which can be triggered early by the trigger voltage of the driver and guide the static electricity to the ground voltage line in time to avoid burning the internal circuit. Another object of the present invention is to provide an electrostatic discharge protection circuit, which has a gate voltage slightly higher than a ground voltage by a clamping characteristic of a diode, and is triggered early, and timely guides static electricity to a ground voltage line to avoid burning. Internal circuit. Another object of the present invention is to provide an electrostatic discharge protection circuit that achieves the above objects by clamping the gate voltage with a transistor. Still another object of the present invention is to provide an electrostatic discharge protection circuit which achieves the above objects by controlling the gate voltage by a capacitance division. The invention provides a high voltage resistant circuit with electrostatic discharge protection for receiving an external high voltage input signal of an integrated circuit to a solder fillet. This high voltage resistant 7 1252578 14592 twf.doc/006 circuit includes first to sixth transistors. The first electrode is coupled to the pad. a first source of the second transistor, a second source of the first source/drain of the body, a second of the second transistor, and a first source coupled to the first transistor The /pole is coupled to the thunder at the same time and is grounded. The gate of the third body, the second source of the third transistor, and the first source/drain surface of the second transistor and the second transistor are connected to the power source, the bad electrode is grounded, and the light is connected to the pad. And the fourth electric (four) of the gate of the job 'section ^ original pressure = signal. The first source/drain coupling of the fifth transistor is connected to the power supply voltage. The first source/none of the sixth transistor is connected to the second source/drain, and the second source of the sixth transistor/ Second:: the gate of the first transistor receives an external high voltage input signal. According to a preferred embodiment of the present invention, the south voltage circuit with electrostatic discharge protection, the fourth electro-crystalline system is a Ρ type a crystal, and the first to second transistors, the fifth to sixth electro-crystal systems are Ν-type transistors. According to the preferred embodiment, the base system of the fourth transistor is floated, and the first The base of the third transistor and the fifth to sixth transistors is grounded. The present invention provides an electrostatic discharge protection circuit including a first transistor, a second transistor, and a third transistor. The first source of the first transistor The drain is coupled to the pad. The first source/drain of the second transistor is coupled to the second source/drain of the first transistor, and the second source/drain of the second transistor is grounded. The first source/drain of the three transistors is simultaneously coupled to the gate of the first transistor and the gate of the second transistor, and the third transistor The second source/drain and the gate are grounded. 8 125257 2twf.doc/006 The electrostatic discharge protection circuit according to the preferred embodiment of the present invention, the first transistor, the second transistor, and the first The three-electron crystal system is an N-type transistor. According to the preferred embodiment, the bases of the first, second, and third transistors are grounded. The present invention further provides an electrostatic discharge protection circuit including a first transistor and a second a transistor and a diode. The first source/drain of the first transistor is coupled to the pad. The first source/drain of the second transistor is coupled to the second source/drain of the first transistor. The second source/drain of the second transistor is grounded. The cathode of the diode is coupled to the gate of the first transistor and the gate of the second transistor, and the anode of the diode is grounded. The invention further provides an electrostatic The discharge protection circuit includes a first transistor, a second transistor, and a third transistor. The first source/drain of the first transistor is coupled to the pad. The first source/drain of the second transistor is coupled a second source to the first transistor /> and a second source/no pole of the transistor The gate of the third transistor and the first source/drain are coupled to the gate of the first transistor and the gate of the second transistor, and the second source/drain of the third transistor is grounded. An electrostatic discharge protection circuit is further provided, comprising a first transistor, a second transistor and a capacitor. The first source/drain of the first transistor is coupled to the pad. The first source/deuterium coupling of the second transistor Connected to the second source/drain of the first transistor, the second source/drain of the second transistor is grounded. One end of the capacitor is coupled to the gate of the first transistor and the gate of the second transistor, the capacitor The other end is grounded. I2525Z§92twf.doc/〇〇6 / The present invention uses the transistor I to connect to the gates of the stack, so that the gates of the stacked NM0S are in an approximately floating state, so when positive, static ^ When the flow occurs, the trigger voltage can be triggered early with a small trigger voltage, and the static current can be induced to flow to the ground voltage line to achieve the function of electrostatic discharge protection. The above and other objects, features, and advantages of the present invention will become apparent to the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] FIG. 2A is a circuit diagram of a high-voltage-resistant high-voltage (HVT) output circuit with electrostatic discharge protection according to a preferred embodiment of the present invention. Referring to FIG. 2A, the tolerance is high. The voltage stacking NM〇s circuit 22 receives the external high voltage input signal of the internal circuit 21〇 in the body circuit to output to the pad 240. The stacked NM0S circuit 22 includes the transistor M4, the N-type transistors M5 to M6, and the resistor. R. The source of the transistor M4 is coupled to the power supply voltage VDD, the drain of the transistor is coupled to the pad 24A, and the gate of the transistor M4 receives the external high-voltage input signal of the internal circuit 210. Among them, the transistor M4 The base system is floating (1〇). The drain of the electric body M5 is coupled to the pad 240, and the source of the transistor M5 is coupled to the drain of the transistor M6. In this embodiment The gate of the transistor = 5 can be coupled to the power supply voltage vDD through the resistor R. The source of the transistor Μ 6 is grounded, and the gate of the transistor M 6 receives the external 咼 voltage input signal of the internal circuit 2 i . In this embodiment, the bases of the transistors M5 and M6 are grounded. 92twf.doc/006 Static electricity The electrical protection circuit 230 can be implemented by using the remaining set of output/input driving circuits that are not used in the output/input pad (1/0 pad), for example, configuring the NMOS transistor to the remaining output/input driving circuit, so that this is configured The NMOS transistor is coupled to the gate in which the nm 〇S is stacked. As shown in Fig. 2A, the ESD protection circuit 230 includes N-type transistors M1 M M3. The gate of the transistor M1 is coupled to the pad 240. The drain of the crystal M2 is coupled to the source of the transistor M1, and the source of the transistor M2 is grounded. The drain of the transistor M3 is simultaneously coupled to the gates of the transistors M1 and M2, and the transistor M3 is The source and the gate are grounded. In the present embodiment, the base of the 'transistor M1~V13' is grounded. When an electrostatic current pulse occurs, usually the gate of the transistor M6 is in a state similar to floating. By making the transistor M3 The off state is maintained, so that the gates of the transistor M1 and the river 2 in the electrostatic discharge protection circuit 230 are also in a similar floating state. Therefore, the electrostatic discharge trigger voltage of the electrostatic discharge protection circuit 23 is close to the stacked NMOS. Trigger voltage of circuit 22 And the discharge path can be opened together to generate the electrostatic current to the ground voltage line vss when the electrostatic flow pulse occurs. FIG. 2B is a high voltage with electrostatic discharge protection according to another preferred embodiment of the present invention. Referring to FIG. 2B, the present embodiment is similar to FIG. 2A in that the electrostatic discharge protection circuit 2 is connected to the gates of the diodes D1 and the diodes. The anode of the body is grounded. Figure 2C is a high voltage circuit diagram of an ear electrostatic discharge protection according to another preferred embodiment of the present invention. Referring to FIG. 2C, the present embodiment 11 125257^92 twf.doc/0〇6 is similar to FIG. 2A, except that the electrostatic discharge protection circuit 26 is coupled with the gate and the drain of the N-plastic transistor 261. It is connected to the gates of the transistors M1 and M2, and connects the source of the transistor 261 to the substrate: 2D is a circuit diagram of a tamper-resistant circuit with electrostatic discharge protection according to another preferred embodiment of the present invention. Referring to FIG. 2D, the present embodiment is similar to FIG. 2A, except that the electrostatic discharge protection circuit 27 is coupled to the gates of the transistors M1 and M2 with one end of the capacitor ci, and the other end of the capacitor ci. Ground. Here, the capacitor C1 is applied, for example, as an N-type transistor, and even if the gate of the transistor is regarded as one end of the capacitor, the source, the drain and the substrate of the transistor are regarded as the other end of the capacitor. 4 is a measurement result of the relationship between the leakage current and the voltage of the electrostatic discharge protection circuit 230 of FIG. 2A and the conventional circuit 122 of FIG. 1B. Under the bias of 3.6V, the leakage current increases slightly from 〇·245η to 〇·722ηΑ. The following will use HSPICE to simulate the electrostatic discharge protection in Figure 2
路。對於0.25um製程而言，在模擬中設定電源電壓VDD H5V’且以週期為200ns以及振幅為3.6V之時脈訊號(其 上生時間與下降時間均設為0.8ns)作為輸入訊號以進行模 擬表1則為利用HSPICE模擬圖2A中靜電放電保護電 路230之結果。 12 I25257^92twfd〇c/〇〇6 A1A®_2a中靜電放電保護電路之模擬結旲%imm ^ 0.25um 寬度/長度(um) 0.35um 20um*14/0.5um 上閘極連線 下閘極連線 1^}入電~^7^ 至 GGNMOS 20um/0.5umroad. For the 0.25 um process, the power supply voltage VDD H5V' is set in the simulation, and the clock signal with a period of 200 ns and an amplitude of 3.6 V (whose upper time and fall time are both set to 0.8 ns) is used as an input signal for simulation. Table 1 shows the results of simulating the electrostatic discharge protection circuit 230 of Figure 2A using HSPICE. 12 I25257^92twfd〇c/〇〇6 Simulation of electrostatic discharge protection circuit in A1A®_2a %imm ^ 0.25um Width/length (um) 0.35um 20um*14/0.5um Upper gate connection lower gate Line 1^} incoming power ~^7^ to GGNMOS 20um/0.5um
上升及下降時間=0.8ns 週期=200ns 直流漏電(n A) 模擬之輸入脈波 0.322/0.627 0.454/0.652 閘源極電壓/下閘極 一臨界電壓(V) 閘源極電壓/上閘極 _臨界電壓(V) 0.251/0.641 0.417/0.654 由表一可看出，以〇.25um製程為例，電晶體M1與 M2之閘源極電壓分別為〇·25ΐv與〇·322ν，皆小於久白 =臨界電壓0.641V與0.627V。換句話說，在正常工作狀 態下，可以確定圖2A中靜電放電保護電路23〇處於截止 狀態。 請繼續參照圖2A，當正脈衝之靜電放電到達焊墊24〇 時，電晶體Ml與M2之閘極電壓將超過觸發電壓，因此 V通電晶體Ml與m2。圖3是利用HspiCE模擬圖2A 中靜電放電保護電路23G之電壓時序圖。當人體放電模式 (HUman-Body M〇del，HBM) 2〇〇〇伏特之靜電脈衝發生在 焊墊24〇日夺，經由電晶體M1之寄生電容cgd使得電晶 體Ml與M2之閘極電壓隨之升高。當電晶體m與M2 之閘極電壓上升至〇·56ν時，電晶體隨與m2即被打開 而形成靜電流之路徑。由圖3中可看出在本實施例之模擬 13 I25257& 92twfdoc/006 條件下，在靜電放電保護電路230被觸發導通期間，電晶 體Ml與M2之閘源極電壓分別約為0.432V與0.56V。 圖2A之靜電放電保護電路230與圖1B之習知電路 122之量測結果被整理於表2中。 表2是圖2A之靜電放電保護電路230與圖1B之習 知電路122之量測結果。 本發明 習知 指寬(um) 20 指量 14 通道長(um) 0.5 上閘極連線 至 GGNMOS 20um/0.5um 經15K電阻至VDD 下閘極連線 GND 正脈衝人體放電模式 平均電壓 6.85KV 5.45KV 最小電壓 6.75KV 5.25KV Center 6.75 KV 5.5 KV Down 6.75 KV 5.5 KV Right 7KV 5.25 KV Up 7KV 5.5 KV Left 6.75 KV 5.5 KV It 1(A) 2.36E-03 5.50E-03 Vtl(V) 6.69 10.03 Ih(A) 4.63E-02 1.00E-01 Vh(V) 5.36 6.45 It2(A) 3.68 2.63 VT2(V) 11.48 20.51 Ron 1.30 3.99 It2*(Ron-1.5k) 5.5 4.0 負脈衝人體放電模式 平均電壓 -8 - 6 最小電壓 -8 -5 Center -8 -6.5 Down -8 -6.5 Right -8 -5 12525¾ 92twf.doc/006 表2中之量測數據係以〇·25ιιηι_2·5/3·3ν-ρ型基底製 程之測試樣本進行靜電放電量測之結果。由表2可清楚看 出’相較於習知電路，本發明可以承受更高等級之人體放 電模式的靜電流衝擊。並且，相較於習知電路l〇 〇3v之 觸發電壓，本發明具有更低之觸發電壓(6.69V)，亦即能 夠更早導通靜電流路徑而避免靜電流燒毀内部電路。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内’當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A是傳統用以耐受高電壓之堆疊式(stack) n型金 氧半場效電晶體(MOSFET)電路圖。 圖1B是典型耐受高電壓之輸出/輸入焊墊電路圖。 圖1C是美國專利第us 6747857 B1號提出之「用於 堆疊式NMOS靜電放電保護之箝位電路」。 圖2A是依照本發明較佳實施例所繪示之一種具靜電 放電保護之财向壓電路圖。 圖2B疋依照本發明另一較佳實施例所緣示之一種具 靜電放電保護之耐高壓電路圖。 圖2C疋依照本發明再一較佳實施例所繪示之一種具 靜電放電保護之耐高壓電路圖。 圖2D疋依照本發明另外一較佳實施例所繪示之一種 具靜電放電保護之耐高壓電路圖。 15 12525¾ 2twf.doc/006 圖3是利用HSPICE模擬圖2A中靜電放電保護電路 之電壓時序圖。 圖4是繪示圖2A之電路與圖1B之習知電路之漏電 流與電壓關係圖。 【主要元件符號說明】Rise and fall time = 0.8ns Cycle = 200ns DC leakage (n A) Analog input pulse 0.322/0.627 0.454/0.652 Gate source voltage / lower gate a threshold voltage (V) Gate source voltage / upper gate _ The threshold voltage (V) 0.251/0.641 0.417/0.654 can be seen from Table 1. Taking the 〇.25um process as an example, the gate voltages of the transistors M1 and M2 are 〇·25ΐv and 〇·322ν, respectively, which are less than the long white. = threshold voltages of 0.641V and 0.627V. In other words, in the normal operating state, it can be determined that the electrostatic discharge protection circuit 23A in Fig. 2A is in an off state. Referring to FIG. 2A, when the positive pulse electrostatic discharge reaches the pad 24, the gate voltages of the transistors M1 and M2 will exceed the trigger voltage, so V energizes the crystals M1 and m2. FIG. 3 is a voltage timing diagram for simulating the electrostatic discharge protection circuit 23G of FIG. 2A using HspiCE. When the human body discharge mode (HUman-Body M〇del, HBM) 2 volts of electrostatic pulse occurs in the pad 24, the parasitic capacitance cgd of the transistor M1 makes the gate voltage of the transistors M1 and M2 Raised. When the gate voltages of the transistors m and M2 rise to 〇·56ν, the transistor is opened with m2 to form a path of electrostatic current. It can be seen from FIG. 3 that under the conditions of the simulation 13 I25257 & 92twfdoc/006 of the present embodiment, during the period in which the electrostatic discharge protection circuit 230 is triggered to be turned on, the gate voltages of the transistors M1 and M2 are about 0.432V and 0.56, respectively. V. The measurement results of the electrostatic discharge protection circuit 230 of Fig. 2A and the conventional circuit 122 of Fig. 1B are organized in Table 2. Table 2 shows the measurement results of the electrostatic discharge protection circuit 230 of Figure 2A and the conventional circuit 122 of Figure 1B. The invention refers to the width (um) 20 finger 14 channel length (um) 0.5 upper gate connection to GGNMOS 20um/0.5um 15K resistance to VDD lower gate connection GND positive pulse human discharge mode average voltage 6.85KV 5.45KV minimum voltage 6.75KV 5.25KV Center 6.75 KV 5.5 KV Down 6.75 KV 5.5 KV Right 7KV 5.25 KV Up 7KV 5.5 KV Left 6.75 KV 5.5 KV It 1(A) 2.36E-03 5.50E-03 Vtl(V) 6.69 10.03 Ih(A) 4.63E-02 1.00E-01 Vh(V) 5.36 6.45 It2(A) 3.68 2.63 VT2(V) 11.48 20.51 Ron 1.30 3.99 It2*(Ron-1.5k) 5.5 4.0 Negative Pulse Human Body Discharge Mode Average Voltage -8 - 6 Minimum voltage -8 -5 Center -8 -6.5 Down -8 -6.5 Right -8 -5 125253⁄4 92twf.doc/006 The measurement data in Table 2 is 〇·25ιιηι_2·5/3·3ν- The test sample of the p-type substrate process was subjected to electrostatic discharge measurement. It can be clearly seen from Table 2 that the present invention can withstand electrostatic flow impact of a higher level of human discharge mode than conventional circuits. Moreover, the present invention has a lower trigger voltage (6.69V) than the trigger voltage of the conventional circuit l〇 〇3v, that is, the electrostatic flow path can be turned on earlier to prevent the electrostatic current from burning the internal circuit. While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a circuit diagram of a stacked n-type metal oxide half field effect transistor (MOSFET) conventionally used to withstand high voltage. Figure 1B is a circuit diagram of an output/input pad that is typically tolerant of high voltage. Fig. 1C is a "clamp circuit for stacked NMOS electrostatic discharge protection" proposed by U.S. Patent No. 6,747,857 B1. 2A is a circuit diagram of a financial stress with electrostatic discharge protection according to a preferred embodiment of the present invention. Fig. 2B is a diagram showing a high voltage resistant circuit with electrostatic discharge protection according to another preferred embodiment of the present invention. 2C is a diagram showing a high voltage resistant circuit with electrostatic discharge protection according to still another preferred embodiment of the present invention. 2D is a diagram showing a high voltage resistant circuit with electrostatic discharge protection according to another preferred embodiment of the present invention. 15 125253⁄4 2twf.doc/006 Figure 3 is a voltage timing diagram for simulating the ESD protection circuit of Figure 2A using HSPICE. 4 is a diagram showing leakage current versus voltage of the circuit of FIG. 2A and the conventional circuit of FIG. 1B. [Main component symbol description]
111、112、134、135、261、Ml〜M3、M5、M6 : N 型電晶體 113、 240 :焊墊 114、 M4 : P型電晶體 · 115、 210 :内部電路 121、 132、220 :堆疊 NMOS 電路 122、 133 :假輸出/輸入(dummy I/O)電路 131 :箝位電路 230、250、260、270 :靜電放電保護電路 Cgd :寄生電容 C1 :電容111, 112, 134, 135, 261, M1 to M3, M5, M6: N-type transistors 113, 240: pads 114, M4: P-type transistors · 115, 210: internal circuits 121, 132, 220: stacked NMOS circuits 122, 133: dummy output/input (dummy I/O) circuit 131: clamp circuits 230, 250, 260, 270: electrostatic discharge protection circuit Cgd: parasitic capacitance C1: capacitance
D1 :二極體 I R :電阻 16D1: diode I R : resistance 16