1252576 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種系統單晶片料，尤指—種具有電磁干擾屏 蔽功此设計的系統單a日日片設計，刻意在單晶片中的特定功能區 塊，例如類比/混合訊號區塊、射頻訊號區塊或記憶體區塊的周圍 設置防電磁干擾的遮蔽環形結構。 【先前技術】 由於半導體製程技術的持續進步，使得大量的電路元件可以被 製作在單一晶片上，再加上市場上對於複雜度高以及運用功能強 的各種電子商品的需求，使得單一晶片的整個電路統可整合包括 微處理器、記憶體、週邊及晶片匯流排等功能，以達到低功率、 高效能、小體積以及高可靠度等諸多優點。 而隨著積體電路在製程上的不斷進步，晶片設計的複雜度也跟 著提昇，造成對產品上市時間的需求更不易滿足。尤其是系統單 曰曰片中具有不同功能的區塊，例如數位/類比區塊或混合訊號區塊 等等，如何精確地完成實體設計，並成功進行驗證，成為晶片業 者所面臨的一大挑戰。 在系統單晶片的設計中，雜訊干擾，例如類比數位電路區塊干 擾或電磁干擾(EMI)，是目前亟待解決的問題。由於雜訊干擾可能 1252576 •嚴重影響到晶片運作的效能，因此晶片在實體設計階段就必須解 * 決這些問題。 【發明内容】 本發明提供一種具有電磁干擾屏蔽功能設計的系統單晶片設 計，刻意在單晶片中的特定功能區塊，例如類比/混合訊號區塊、 射頻訊號區塊或記憶體區塊的周圍設置防電磁干擾的遮蔽環形結 構。 ♦ * 根據本發明之較佳實施例，本發明揭露一種系統單晶片，包含 有一核心微處理器；一晶片匯流排界面;一嵌入式記憶體區塊； 以及一類比/混合訊號區塊，其中該類比/混合訊號區塊刻意以一第 一遮蔽環形結構圍繞在周圍，藉此保護該類比/混合訊號區塊不受 到電磁干擾。 為了使貴審查委員能更近-步瞭解本發明之特徵及技術内 容:請參_下錢本發明之詳細與關。然而所附圖式僅 供參考與辅助說_，並非絲對本發明加以限制者。 【實施方式】 第1圖繪示的是本發明較佳實施例的系統單.晶片1〇的功能區 塊不意圖。如第i圖所示，本發明的系統單晶片10適合應用在行 動通訊或多媒體領域，其大體上包括有—嵌人式核心處理器12、 1252576 -一數位讯號處理器(digital signal processor，DSP)14、一晶片記情體 區塊16、一匯流排界面18、一 MPEG解碼器2〇以及一類比/混合 訊號區塊22。上述的各個功能區塊皆整合製造在同一晶片上。第 :1圖中所顯示的系統單晶片10的功能區塊示意圖僅供說明，並非 限制本發明範疇。習知該項技藝者可以在理解本發明所揭露之内 容後，應用與本發明相同之概念至類似的系統單晶片中，以解決 類似的問題。舉例來說，在其它實施例中，本發明的系統單晶片 _亦可包括射頻訊號積體電路。 根據本發明之較佳實施例，前述的嵌入式核心處理器可以 為16/32位元的(註··⑽c為reduced instmcti〇n如 的縮寫)微處理器，並由美國ARM有限公司所提供。根據本發明 之較佳實施例，前述的晶片記憶體區塊16可以是動態隨機存取記 憶體、非揮發性記憶體或者其它記憶體。如第1圖所示，本發明 •之主要特點在於别述的晶片記憶體區塊16刻意利用一遮蔽環形結 構160將曰曰片圮憶體區塊16圍繞包覆其中，而前述的類比/混合訊 旒區塊22則利用一遮蔽環形結構22〇將類比/混合訊號區塊22圍 繞包覆其中。 • 當本發明的系統單晶片在操作時，遮蔽環形結構16〇以及遮蔽 裏开/…構220皆為接地(Ground)狀態，其所發揮的功能是對高頻數 位時脈所產生的電磁干擾(EMI)e成屏蔽，使電磁干擾不會影響類 比/混合訊號區塊22的正常運作或產生訊號耦合現象。為了更進一 1252576 步詳細解釋前述的遮蔽環形結構160以及遮蔽環形結構22〇的實 體構造，以下再以繪示於第2圖中沿著第！圖中切線14，的剖面做 說明。 如第2圖所示，遮蔽環形結構22〇包含有一金屬屏蔽牆24〇， 其環設於類比/混合訊號積體電路250的周圍。前述的金屬屏蔽牆 240係為一堆疊而成的金屬牆，利用半導體製程將每一層的金屬導 春線層與導介(via)層堆疊起來，從下至上可能包括有接磾層(第2圖 中以’’CONT”標示)金屬、第一層金屬(M1)、第一層導介層^工）、 第二層金屬(M2)、第二層導介層(V2)、第三層金屬(M3)、第三層 導介層(V3)以及第四層金屬(]^4)。在遮蔽環形結構22〇的底部， 設有-離子佈植區域26〇，其係植入於石夕覆絕緣基板(S〇I)28〇中， 亚且連接至金屬屏蔽牆240。前述的離子佈植區域26〇最好能夠設 在罪近淺溝絕緣結構(sti)的附近。在遮蔽環形結構22〇的上端則 _為金屬墊層290，可以將遮蔽環形結構22〇接至地。 口口請參閱第3圖以及第4圖，其中第3圖繪示的是本發明的系統 單晶片30的-部份遮蔽環形結構其在類比/數位界面處的上視示 意^第4圖緣示的是第3圖中沿著切線關，所見的剖面^ ,如月;1所述，金屬屏蔽牆240係由多層的金屬以及導介層堆疊而成， ~其在類比/數位界面處具有一類比/數位連結窗口 3〇〇，使前述的數 位峨處理器(DSP)M得以經由訊號線32〇與屏蔽的類比/混合訊 號區塊22互通連結。前述的類比/數位連結窗口 最好能夠設置 1252576 在距離類比/混合訊號區塊的主要卫作訊號線㈣的位置。 另外’如第3圖所示’訊號線32()可以藉由兩條平行的地線34〇 構成雙地線平行屏蔽作用。這兩條平行的地線與訊號線32〇 所處的i屬層相同，如在第3圖中地線34()與訊號線⑽皆由第 四層益屬所疋義出來’且兩條地線34〇分別設於訊號線的兩 侧’並以最小線寬製作，藉此雙地線平行賊作職少訊號柄合 現象。 以上所述僅為本發明之較佳實施例，凡依本發财請專利範 圍所做之均賴倾修飾，冑應屬本發明之涵絲圍。 【圖式簡單說明】 第1圖繪示的是本發明較佳實施例的系統單晶片的功能區塊示 意圖。 第2圖為沿著第1圖中切線i-Γ的剖面示意圖。 第3圖是本發明的系統單晶片的一部份遮蔽環形結構其在類比 /數位界面處的上視示意圖。 第4圖是第3圖中沿著切線ΙΙ-ΙΓ所見的剖面示意圖。 1252576 【主要元件符號說明】 10 糸統早晶片 12 嵌入式核心處理器 14 數位訊號處理器 16 晶片記憶體區塊 18 匯流排界面 20 MPEG解碼器 22 類比/混合訊號區塊 30 糸統早晶片 160 遮败壞形結構 220 遮蔽環形結構 240 金屬屏蔽牆 250 類比/混合訊號積體電路 260 離子佈植區域. 280 矽覆絕緣基板 ， 290 金屬塾層 300 類比/數位連結窗口 320 訊號線 340 .地線 11 ⑧1252576 IX. Description of the invention: [Technical field of the invention] The present invention relates to a single-chip material of a system, in particular, a system single-day solar design with electromagnetic interference shielding function, deliberately in a single wafer A specific functional block, such as an analog/mixed signal block, an RF signal block, or a memory block, is provided with an anti-electromagnetic interference shielding ring structure. [Prior Art] Due to the continuous advancement of semiconductor process technology, a large number of circuit components can be fabricated on a single wafer, coupled with the market demand for various electronic products with high complexity and powerful functions, making the entire single wafer The circuit system can integrate functions such as microprocessor, memory, peripheral and chip bus to achieve low power, high efficiency, small size and high reliability. With the continuous advancement of the integrated circuit in the process, the complexity of the chip design has also increased, making the demand for time-to-market more difficult to meet. In particular, blocks with different functions in the system's single-chip, such as digital/analog blocks or mixed-signal blocks, etc. How to accurately complete the physical design and successfully verify it becomes a major challenge for the chip industry. . In the design of system single-chip, noise interference, such as analog digital block interference or electromagnetic interference (EMI), is an urgent problem to be solved. Since noise interference may be 1252576. • The performance of the wafer operation is seriously affected, so the wafer must be resolved during the physical design phase. SUMMARY OF THE INVENTION The present invention provides a system single-chip design with an electromagnetic interference shielding function design, deliberately in a specific functional block in a single chip, such as an analog/mixed signal block, an RF signal block, or a memory block. Set the shielding ring structure against electromagnetic interference. According to a preferred embodiment of the present invention, a system single chip includes a core microprocessor, a wafer bus interface, an embedded memory block, and an analog/mixed signal block, wherein The analog/mixed signal block is intentionally surrounded by a first shadow ring structure, thereby protecting the analog/mixed signal block from electromagnetic interference. In order to enable your review board to get a closer look at the features and technical content of the present invention: please refer to the details and details of the invention. However, the drawings are for reference and aid only, and are not intended to limit the invention. [Embodiment] FIG. 1 is a schematic diagram of a functional block of a system of a preferred embodiment of the present invention. As shown in FIG. 1, the system single chip 10 of the present invention is suitable for use in the field of mobile communication or multimedia, and generally includes an embedded core processor 12, a 1252576-digital signal processor (digital signal processor, DSP) 14, a chip ticker block 16, a bus interface 18, an MPEG decoder 2A, and an analog/mixed signal block 22. Each of the above functional blocks is integrated and fabricated on the same wafer. The functional block diagram of the system single chip 10 shown in Fig. 1 is for illustrative purposes only and is not intended to limit the scope of the invention. Those skilled in the art will be able to apply the same concepts as the present invention to similar system single wafers after understanding the disclosure of the present invention to solve similar problems. For example, in other embodiments, the system single chip of the present invention may also include an RF signal integrated circuit. According to a preferred embodiment of the present invention, the aforementioned embedded core processor may be a 16/32-bit microprocessor (Note (10)c is an abbreviation for reduced instmcti〇n), and is provided by American ARM Co., Ltd. . In accordance with a preferred embodiment of the present invention, the aforementioned wafer memory block 16 can be a dynamic random access memory, non-volatile memory or other memory. As shown in FIG. 1, the main feature of the present invention is that the other-described wafer memory block 16 is intentionally wrapped around the smear-receiving block 16 by a shielded annular structure 160, and the aforementioned analogy/ The mixing buffer block 22 surrounds the analog/mixed signal block 22 with a shadow ring structure 22〇. • When the system single chip of the present invention is in operation, the shielding ring structure 16〇 and the shielding opening/closing structure 220 are all in a ground state, and the function thereof is electromagnetic interference to the high-frequency digital clock. (EMI) e is shielded so that electromagnetic interference does not affect the normal operation of the analog/mixed signal block 22 or signal coupling. In order to further explain the above-described structure of the shielding ring structure 160 and the shielding ring structure 22A in detail, the following is further illustrated in Figure 2 along the first! The section of the tangent 14 in the figure is illustrated. As shown in FIG. 2, the shielding ring structure 22A includes a metal shielding wall 24'', which is disposed around the analog/mixing signal integrated circuit 250. The foregoing metal shielding wall 240 is a stacked metal wall, and the metal spring layer and the via layer of each layer are stacked by a semiconductor process, and the interface layer may be included from the bottom to the top (2nd) The figure is marked with ''CONT') metal, first layer metal (M1), first layer of via layer), second layer of metal (M2), second layer of via layer (V2), third layer a metal (M3), a third layer of a conductive layer (V3), and a fourth layer of metal (4). At the bottom of the shielding ring structure 22, an ion implantation region 26 is provided, which is implanted in the stone. The insulating substrate (S〇I) 28 is sub-connected to the metal shield wall 240. The ion implantation region 26 is preferably disposed adjacent to the sin near shallow trench insulating structure (sti). The upper end of the structure 22A is a metal pad layer 290, and the shielding ring structure 22 can be connected to the ground. For the mouth, please refer to FIG. 3 and FIG. 4, wherein FIG. 3 shows the system single chip of the present invention. The top view of the 30-partially masked ring structure at the analog/digital interface. The fourth figure shows the section along the tangential line in Figure 3, as seen in the section ^, eg The metal shielded wall 240 is formed by stacking a plurality of layers of metal and a conductive layer, and has an analog/digital connection window at the analog/digital interface, so that the aforementioned digital 峨 processor (DSP) M can be interconnected with the shielded analog/mixed signal block 22 via the signal line 32. The aforementioned analog/digital link window is preferably capable of setting the position of the main guard signal line (4) in the distance analog/mixed signal block. In addition, as shown in Fig. 3, the signal line 32() can be parallel shielded by two parallel ground lines 34〇. The two parallel ground lines and the signal line 32〇 are located. The genus layer is the same. For example, in Figure 3, the ground line 34() and the signal line (10) are both defined by the fourth layer of genus 'and the two ground lines 34 设 are respectively disposed on both sides of the signal line' and are minimized. The line width is made, so that the double-line parallel thief works as a small signal. The above description is only a preferred embodiment of the present invention, and all the patents in accordance with the scope of the invention are modified. It belongs to the han silk circumference of the present invention. [Simple description of the drawing] Figure 1 shows the present BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view of a tangential line i-Γ along the first embodiment. FIG. 3 is a partial shadow ring structure of the system single wafer of the present invention. A schematic diagram of the upper view at the analog/digital interface. Fig. 4 is a schematic cross-sectional view taken along line ΙΙ-ΙΓ in Fig. 3. 1252576 [Description of main component symbols] 10 糸 早 early wafer 12 embedded core processor 14 Digital Signal Processor 16 Chip Memory Block 18 Bus Interface 20 MPEG Decoder 22 Analog/Mixed Signal Block 30 糸 Early Wafer 160 Covering Bad Structure 220 Shading Ring Structure 240 Metal Shielding Wall 250 Analog/Mixed Signal Product Body circuit 260 ion implantation area. 280 绝缘 insulating substrate, 290 metal 塾 layer 300 analog/digital connection window 320 signal line 340. ground line 11 8