TWI251976B - Switching control circuit for primary-side-controlled power converters - Google Patents

Abstract

The present invention discloses a switching control circuit for a primary-side controlled power converter. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal. A current-waveform detector generates a current-waveform signal by measuring a primary-side switching current. An integrator generates a current-feedback signal by integrating the current-waveform signal with the discharge time. A time constant of the integrator is correlated with the switching frequency, thus the current-feedback signal is proportional to an output current of the power converter. A PWM circuit controls the pulse width of the switching signal in response to the outputs of a voltage-loop error amplifier and a current-loop error amplifier. The output voltage and the maximum output current of the power converter are therefore regulated.

Description

1251976 IX. Description of the invention: [Technical field to which the invention pertains] The present invention is a control circuit for an electric hybrid (four) control circuit, which is specially adapted to a switching mode power supply of a switching mode power supply. [Prior Art] Various power supplies have been widely used to provide stably adjusted voltages and currents. Based on compliance with safety considerations, an off-line power supply (〇ff_linep〇werc〇nverter) must provide electrical isolation between its primary and secondary sides (galvanie is〇lati〇n). In this case, a switch-type control device is disposed on the primary side of the power supply, and a _cal-coupler and a secondary-side stabilizer (sec〇ndary side regulat〇r) must be used to stabilize the f adjustment. Output voltage and output current. The main object of the present invention is to provide a switching control device for the primary side of the power supply, which is used to control the output voltage and output current of the power supply without requiring an optical coupler and a secondary side stabilizer. Furthermore, the present invention further provides frequency hopping characteristics for extending the switching frequency of the switching signal to reduce electrical and magnetic interference (EMI). Therefore, the volume and cost of the power supply can be reduced. SUMMARY OF THE INVENTION A switching control device is applied to a power supply of a primary side control, and includes a switching power switch through a current sensing device for switching a transformer. A switching signal switches the power switch to stably adjust the output voltage and the maximum output current of the power supply. A controller is coupled to the 忒' voltage regulator and the current sensing device for generating a voltage feedback signal and a current feedback signal. During the period of the switching off time (Off time), by sampling the voltage signal and the transformer's discharge time, during the switching on time (ontime), by measuring the transformer once 1251976 Side current signal. The switching signal is generated according to the voltage feedback signal and the current feedback signal. The controller includes a voltage waveform detector for sampling the voltage signal multiple times and generating a voltage feedback nickname and a discharge time signal. The voltage waveform detector is connected to the auxiliary winding of the transformer through a resistive divider (auxistary divider). The discharge time signal represents the discharge time of the transformer and also represents the discharge time of the secondary side switching current. A current waveform detector generates a current waveform signal by measuring a current signal on the primary side of the transformer. An oscillator generates an oscillation signal to determine the switching frequency of the switching signal. An integrator generates a current feedback signal by integrating the current waveform signal and the discharge time. The first operational amplifier and the first reference voltage constitute a voltage loop error amplifier for amplifying the voltage feedback signal and providing loop gain for the purpose of outputting the voltage. control. The second operational amplifier and the second reference voltage form a current loop error amplifier for amplifying the current feedback signal and providing loop gain for the purpose of output current control. A peak-current limiter is connected to the current sensing device to limit the maximum value of the current signal on the primary side of the transformer. A pulse width modulator combines a first comparator (first comparat〇r) with a second comparator (secon(j comparator), based on the output of the voltage loop error amplifier, the output of the current loop error amplifier and the peak current limiter The output is used to control the pulse width of the switching signal. A pr〇grammable current source is connected to the input of the voltage waveform detector for temperature compensation. The programmable current source A programmable current is generated based on the temperature of the controller to compensate for the temperature deviation of the power supply at the output voltage. A pattern generator generates a digital pattern code. The first pr〇grammable capacitor is connected to the oscillator and the module generator, and can be used to modulate the switching frequency according to the digital module code. The spectrum of the switching frequency is extended, so It can reduce the electromagnetic interference of the power supply. The second programmable capacitor (sec〇nd Programmable capacitor) is connected to the integrator and module generator. In order to make the integrator's 1251976 time constant closely related to the switching service, the (4) is proportional to the output current of the power supply. The power of the program should be noted. The above summary and the following detailed description demonstrate the scope of the patent application in the present invention, and other objects related to the present invention are described in the following description and diagrams. Explain. ~炎"" ^ [Embodiment]

Figure 1 shows a power supply. The power supply includes a transformer 1 〇 having a auxiliary ear winding na, a primary side winding Np and a secondary side winding Ns. The primary side winding Np is provided by an input voltage that is supplied by the power supply. In order to stably adjust the output voltage v〇 of the power supply and the output stream 10', a controller 70 generates a switching signal v_, and controls a power switch such as a transistor 2 through a current sensing device (_ent__device) for switching the transformer. 〇〇. Current sensing, resistance 30 is like the same current sensing device. FIG. 2 shows various signal waveforms of the power supply of FIG. 1. When the switching signal ^^^^ is turned on (logically high level), a primary side switching current 产生 is generated. The primary side switching peak current IP1 can be obtained from:

I — V|N -r P1—17 ---------------------------------------- -----------------------------(1) where LP is the inductance value of the primary winding Np of the transformer i〇; T〇N is the switching The on time of the signal VpwM. Once the switching signal VPWM transitions to off (logically low level), the fault energy of the transformer 1〇 will be transmitted to the secondary side of the transformer 1〇, and through the rectifier 4 to the wheel terminal of the power supply. Then, the secondary side switching current Is is generated. The secondary side switching peak current IS1 can be expressed as: (2) 1251976 where v. For the power supply of the wheel out; dragon is the forward voltage drop of the rectifier 4Q; (4) the second winding is called the Lai value; 4 is the transformer ι〇 ^ discharge time ' can also be expressed as the secondary side switching current Is Discharge time. At the same time, in the auxiliary winding NaJi of the transformer 10, a voltage signal V is generated, and the voltage signal v is expressed as: VAUX1=^X(V0+VF)----------------- ---------------------- 1 NS (3) where TNA and TNS are the turns of the transformer 1〇_help winding Na and the secondary winding Ns . When the secondary side switching current Is drops to zero, the voltage signal V generated by the auxiliary winding Na starts to decrease, which also means that the energy storage of the transformer 10 is completely released at this moment. Therefore, the discharge time Tds of equation (7) can be corrected by subtracting v_& falling Wei (touch % edge) to the corner where the voltage signal vAUX starts to fall (c〇mer), as shown in Fig. 2. The primary side switching peak current IP1 and the winding of the transformer 1G can determine the secondary _ switching peak current Isi, and the secondary side switching peak current isi can be expressed as: where Tnp is the winding of the primary winding Np of the transformer § 1 变Number of turns. The control state 70 includes a supply terminal VCC and a ground terminal GND for supplying power. A resistor 5 〇 and a resistor 51 are connected in series to form a divider, and the two resistors are respectively connected between the auxiliary winding Na of the transformer 1 与 and the ground reference level. The detection terminal DET of the controller 70 is connected to the junction of the resistor 5 〇 and the resistor 51. When the detection terminal DET generates a voltage ν 〇Ε τ, it can be obtained:

Vdet R51: Vaux R50 + R51 where R% and R51 are the resistance values of the resistors 5〇 and 51, respectively. (5) The voltage signal Vaux further charges the capacitor 65 via the rectifier 60 to supply power to the controller 70. The current sensing resistor 3 is connected from the source of the transistor 20 to the ground reference level for converting the primary side switching current Ip to the current signal Vcs. The 1251976 sense terminal CS of the controller 7 is connected to the current sensing resistor 30 for detecting the current signal.

The output terminal 〇UT of the Vcs 0 controller 70 generates a switching signal VpwM for switching the transformer 10. A compensation network is connected to the voltage-compensation terminal COMV of the controller 7 for voltage loop frequency compensation. The compensation network can be connected to the ground reference level using a capacitor, such as capacitor 31. Another compensation network is connected to the current compensation terminal (current-c〇mpensati〇ntermi blood i)c〇m! of the controller 7〇 for current loop frequency compensation. The compensation network can also be connected to ground reference level 'like capacitor 32' using a capacitor. Figure 3 shows a controller 7 in accordance with a preferred embodiment of the present invention. A voltage waveform detector 1 generates a voltage feedback signal 乂乂 and a discharge time signal by a plurality of sampling voltages vDET, and the discharge time signal sDS represents a discharge time Tds of the secondary side switching current Is. A current waveform detector 3 generates a current waveform signal ¥^ by measuring the current signal Vcs on the primary side of the transformer. An oscillation u. The 200 generates a vibration signal pu for determining the switching frequency of the switching signal vpwM. An integrator 4 产生 generates a current feedback signal % by integrating the current waveform signal \^ with the discharge time tds. An operational amplifier 71 and a reference voltage Vr£fi form a voltage loop error amplifier for amplifying the voltage feedback signal Vv and providing a loop gain for output voltage control. An operational amplifier 72 and a reference voltage form a current loop error amplifier for amplifying the current feedback signal % and providing a loop gain for output current control. A pulse width modulator 500 is coupled to the comparator 73 and the comparator 75 for controlling the pulse width of the switching signal vPWM according to the output of the voltage loop error amplifier, the output of the current loop error amplifier, and the peak current limiter. Both operational amplifiers 71 and 72 have the characteristics of conduction (trans_c〇nductance). The output of the operational amplifier 71 is connected to the voltage compensation terminal and the positive input of the comparator 3. The output of the operational amplifier 72 is coupled to the current compensation terminal c〇MI and the positive terminal input of the comparator 75. The negative input of comparator 73 is coupled to the output of adder_. Comparators

The negative input of 1C is provided by the ramp signal RMp, which is generated by the 1251976 oscillator 200. The adder 600 generates a slope signal VsLp by adding the transformer-secondary current signal Vcs to the slope duty, and the adder functions to form a slope compensation for the voltage loop. The positive input of the comparator 74 is connected to the sensing terminal cs by the negative input of the comparator 74, which can be used to detect the current on the primary side of the transformer, and the Lai-Lion-Lion The two inputs of the (eyde_by_eyde) current-limited pro-J NAND gate 79 are connected to the output of the comparator, comparator %, and comparator, respectively. The output of the NA gate 79 generates a reset signal (the job t_雄ST. The reset signal is supplied to the pulse width modulator 500 for controlling the duty cycle of the switching signal VpwM. Switching the current 1? from the primary side The pulse width modulation to the switching signal Vp side forms a current control loop, and the amplitude value (magmtude) of the secondary side switching current & is controlled according to the reference voltage ν_. The secondary side switching current Is and the primary side switching current ^ The relationship between the ratios is shown in equation (4). The signal waveform shown in the root system 2, the power supply (4) output electric correction is the average value of the secondary side switching current Is. The output current can be expressed as: for the switching period of the switching subtraction, no The time of the stagnation is always close. The output current of the power supply is 1〇, so it can be stably adjusted. The 贞 贞 3 (8) detects the current signal & and generates the current waveform signal Vw. The integrated cutter 400 is integrated by The current waveform signal v and the discharge (5) TDS further generate a current feedback signal V. The current feedback signal can be designed as: V, - Vw ^ds_ 2 1 (7) wherein the current waveform signal 乂 ~ is expressed as: V ,

丨NS

Rs X ls (8) where T! is the integrator 4〇〇 The signal % can be rewritten as: the time constant. It can be seen from equations (6)-(8) that current feedback (9) 1251976

Vl II

1 NS

NS

We can see that the current feedback signal is proportional to the output current of the power supply. When the output current increases, the current feedback signal is increased, but the maximum value of the current feedback signal is transmitted through the electric bet. The 敎 adjusts the value of _ in the reference secret v_. Under the feedback control of the current control loop, the maximum output current is 〗 〖. —) can be obtained from: |〇(max) x ________

TnS 1 + (GaxGswx^) (10) where K is a constant 'system, equal to Tl/T; Ga is the gain of the current loop error amplifier (Gay); Gy is the gain of the switching circuit. When the loop gain of the current control loop is high (Ga χ Gsw>> U, the maximum output current I〇(max) is simplified to:

L〇(max) = K X

Tnp VREF2 (11) X »»--

The maximum input itj current i〇(max) of the Tns Rs power supply is stably adjusted to a fixed current according to the reference* of the reference Vref2. In addition, the pulse width modulation of the voltage signal vAUX is sampled to the switching signal to form a voltage control loop, and the amplitude value of the voltage signal Vaux is controlled according to the value of the reference voltage Vrefi. The voltage signal VAUX has a proportional relationship with the output voltage \^〇, as shown in equation (3). The voltage signal vAUX is again attenuated to obtain the voltage Vdet as shown in equation (5). The voltage waveform detector 100 generates a voltage feedback signal Vv through multiple sampling of the voltage VDET. The value of the voltage feedback signal Vv is stably adjusted by the voltage control loop and controlled according to the value of the reference voltage Vrefi. The voltage loop error amplifier and switching circuit provide loop gain for the voltage control loop. Therefore, the output voltage V〇 can be simplified to:

Vo =

Rso + R51 R51

Tns Tna x Vrefi)-Vf (12) The voltage signal VAUX is multi-sampled by the voltage waveform detector 100. Voltage sampling and measurement are performed immediately before the secondary side switching current Is discharges to zero. Therefore, the change in the secondary side switching current Is does not affect the value of the forward voltage drop vF of the rectifier 40. However, as temperature 1251976 changes, the forward voltage drop VF of rectifier 40 also changes. A programmable current source 80 is coupled to the input of the voltage waveform detector 100 for temperature compensation. The programmable current source 80 produces a programmable current τ based on the temperature of the controller 70. The programmable current τ combined with the resistors 50 and 51 produces a voltage ντ that compensates for temperature variations in the forward voltage drop VF.

Vt = , tx RsoxR^-------------------------------------------- ------------------(13)

Rso + Rsi Referring to equations (12) and (13), it can be found that the ratio of the resistance values R5〇 to R51 determines the output voltage V〇. The resistance value of the resistor and R51 determines the temperature coefficient to compensate for the forward voltage drop Vf of the rectifier 40. Due to the programmable current source 80, the equation (丨2) can be rewritten as...

Vo = rR50 + Rsi R51 —-x Vrefi) ~ Vf H- Vt Τνα (14)

4 is a diagram showing a voltage waveform detector 1 in accordance with a preferred embodiment of the present invention. A sample-pulse generator 190 generates a sampled pulse signal for multiple sampling. A threshold voltage 156 is applied to the voltage signal VAUX, thereby generating a level-shift reflected signal. The first signal generator includes a D-type flip-flop 17 and two AND gates 165 and 166 for generating a first sampled signal (first

Sample signal) VSP1 and the second sample signal VSP2. The second signal generator includes a D-type flip-flop 170, a NAND gate 163, and an AND signal.

The gate 164 and the comparator 155 are used to generate a discharge time signal Sds. A time-delay circuit includes an inverter 162, a current source 180, a transistor 181, and a capacitor 182.

The delay time Td is generated when the switching signal Vpwm is disabled. The input of the inverter 161 is provided by the switching signal VPWM, and the output of the inverter ι61 is connected to the input of the inverter 162, and is also connected to the first terminal input of the AND gate 164 and the d-type flip-flop 170. Clock-input. The output of the inverter 162 can be turned on or off (〇n/〇ffm crystal (8). The capacitor 182 is connected in parallel with the transistor 181, which charges the capacitor 182. Therefore, the current and current of the current source 180 The capacitance value of 182 determines the delay time of the time delay circuit, and the capacitance 182 is the output of the time delay circuit. The D input of the d-type flip-flop 17〇 is pulled up (puU 12 1251976 hlgh) to the supply voltage u-type positive The output of the counter 17〇 is connected to the second "J °H8_gate 164 output discharge time signal sDS of the fun ^ gate. When the switching signal vPWM is disabled, the heart-to-day discharge signal Sds is enabled The state (such as North (5). The output of this gate π] is connected to the reset input of the D-type flip-flop 17〇. The input of the ναν〇 gate 163 is connected to the output and comparator of the time delay circuit. The output of 155. The negative input of comparator 155 is provided by the level shifting signal. The positive input of comparator 155 is boosted by the feedback signal γ. Therefore, after the delay time Td, once The position displacement reflection signal is lower than the voltage feedback Vv 'discharge time signal Sds is forbidden In addition, as long as the switching signal Vpwm is enabled, the discharging time signal SDS is also disabled. The sampling pulse signal generated by the sampling pulse generator 190 is applied to the clock input of the D-type flip-flop 171, The third terminals of the AND gates 165 and 166 are input. The D input of the D-type flip-flop 171 is connected to the inverted output terminal to form a divide-by-2 counter (divide_by_tw〇c〇unter). The output of the d-type flip-flop πι And the reverse output system is respectively connected to the second terminal input of the AND gates 165 and 166. The first terminal input of the AND gates 165 and 166 is provided by the discharge time signal Sds. The fourth terminal input system of the gates 165 and 166 Connected to the output of the time delay circuit. Therefore, the first sampling signal Vspi and the second sampling signal v are generated according to the output of the sampling pulse signal. In addition, during the period of the enabling state of the discharging time signal SDS During the period, the first sampling signal Vspl and the second sampling signal vSP2 are alternately generated. However, the insertion delay time Td at the beginning of the discharging time signal SDS is used to prohibit the generation of the first sampling signal VSP1 and Second The sampling signal vSP2. During the period of the delay time Td, the first sampled signal v milk and the second sampled signal VSP2 are therefore disabled. The first sampled signal vSP1 and the second sampled signal Vsi> The voltage signal VAUX is alternately sampled via the detecting terminal DET and the resistive voltage divider. The first sampling signal Vspl and the second sampling signal VSP2 control the switch 121 and the switch 22 for respectively obtaining the capacitance across the capacitor 11〇 and the first hold voltage of the capacitor 111 and the second hold voltage (sec〇nd h〇ld voltage). Switch 123 is connected in parallel with capacitor 丨10 for discharging capacitor i 1 。. The switch i24 13 1251976 is connected in parallel with the capacitor 111 for generating a sustain voltage by the capacitor U1 > including the operational amplifiers 15A and (5), the diode 13 (), and the buffei*amplifier. The operational amplifiers 150 and 151 u, 135 are used for the i-ray & 111, b 鸲 input system is respectively connected to the capacitor 110. The second: the negative input terminal of the wide 51 is connected to the output ratchet body 13 of the buffer amplifier (M_ The output of the operational amplifier 15G is output to the output of the buffer amplifier. The diode 131 is amplified by the output of the operational amplifier 151. The output of the sustain voltage is compared with the second sustain voltage. High... Jintian h flat 乂 (10) is applied to maintain voltage. The current source (3) is used to terminate the operation. Switch 125 is periodically turned on to the capacitor's sustain voltage to generate voltage feedback signal Vv. By her pro-number pLs, the switching action of turning on or off is generated. After the time Td, the first recording and the sampling signal VSP2 start to generate the first sustain voltage and the second sustain voltage, so that the voltage can be eliminated. The signal interference of the signal vAUX (spikeinterf(10)ce). When the switching signal v_ is disabled and the transistor 20 is turned off, the voltage spike of the voltage signal Vaux will be generated. When the secondary side switching current IS is released Zero, 峨 峨 Vau> Decrease, the signal Sds of the discharge day is disabled by the debt measurement of the comparator 155. The pulse width of the discharge time signal & is thus closely related to the discharge time Tds of the secondary side switching current IS. According to the discharge time signal sDS is disabled, and the first sampling signal Vspi and the second sampling signal Vsp2 are disabled, and multiple sampling is stopped. At this time, a sustain voltage is generated at the output of the buffer amplifier, indicating The end voltage is thus closely related to the voltage signal Vaux. Before the secondary side switching current Is drops to zero, the voltage signal Vaux is sampled. The sustain voltage is obtained by taking the first sustain voltage and the first The two higher voltages of the sustain voltage, and when the voltage signal VAUx begins to decrease, the sampled voltage will be ignored. Figure 5 shows an oscillator 200 in accordance with a preferred embodiment of the present invention. Operational amplifier 201, resistor 210 and resistor 250 constitutes the first voltage to current converter (first V-to-I converter). The first voltage to current converter generates a reference current according to the reference voltage VreF L25〇. Several transistors such as 251, 252, 253, 254 and 255 form a current mirror. According to the reference 14 1251976, the current is 25 〇 to generate the oscillator charge current l253 and the relocation discharge. The current discharge (current discharge) I255. The drain of the transistor 253 generates the oscillating charging current I253. The drain of transistor 255 produces the oscillating discharge current 1255. The switch 230 is connected between the drain of the transistor \253 and the capacitor 215, and the switch 231 is connected between the drain of the transistor 255 and the capacitor 215. The ramp number RMP is obtained by capacitor 215. The positive terminal input of comparator 205 is coupled to capacitor 215. The comparator 205 outputs an oscillation signal PLS which determines the switching frequency. One of the terminals of switch 232 is provided by a high threshold voltage (j^gh threshold voltage) VH. The first end of switch 233 is provided by a low threshold voltage (i〇wthresh〇ldv〇ltage) VL. The second end of switch 232 and the second end of switch 233 are both connected to the negative input of comparator 2〇5. The input of inverter 260 is coupled to the output of comparator 205 for generating an inverse _ phase oscillation signal / PLS. The oscillation signal PLS is used to turn on or off the switch 231 and the switch 233. The reverse phase oscillation signal/PLS control switch 230 and the switch 232 are turned on and off. The first programmable capacitor 910 is connected in parallel with the capacitor 215, and is used to modulate the switching frequency according to the signal of the digital module ρΝ··Ρι. The resistance value ^1() of the resistor 210, the capacitance value C2i5 of the capacitor 215, and the electric valley value C91G of the first programmable valley 910 determine the switching period τ of the switching frequency, and the switching period τ can be obtained by: (C215 + C910) XV〇SC VREF/R210 R210 x (C215 + C910))

Vosc Vref (15)

Where Vosc = VH-VL. The capacitance value c9i of the first programmable capacitor 91〇 changes according to the change of the digital module Ρν··Ρι. Figure 6 shows a current waveform detector 3A in accordance with a preferred embodiment of the present invention. A peak detector includes a comparator 31 〇, a current source 32 〇, a switch 33 〇, a switch 34 〇, and a capacitor 361. The peak value of the sampled current signal Vcs is used to generate a peak current signal (peak_cun^t signal). The positive input of comparator 310 is provided by current signal Vcs. The negative input of comparator 31 is coupled to capacitor 361. Switch 330 is coupled between current source 320 and capacitor 361. The output of the comparator 31 is used to turn the switch BO on or off. The switch 34 is connected in parallel with the capacitor train to discharge the capacitor 301. The switch mo is periodically turned on to the peak current signal of the capacitor S62, and 15 1251976 is used to generate the current waveform signal Vw. The switch 350 is turned on or off by the oscillation signal PLS. Figure 7 shows an integrator 4A in accordance with a preferred embodiment of the present invention. The second voltage-to-I converter includes an operational amplifier 410, a resistor 450, and transistors 420, 421 and 422. The positive input of operational amplifier 410 is provided by current waveform signal vw. The negative input of operational amplifier 410 is coupled to resistor 45A. The output of the operational amplifier 41A drives the gate of the transistor 420. The source of transistor 420 is coupled to resistor 450. The second voltage to current converter generates a current 1420 via the drain of the transistor 420 in accordance with the current waveform signal Vw. The transistors 421 and 422 form a current mirror having a ratio of 2:1. Current l42G is driven by the drain of transistor 422

The ~l mirror is used to generate a programmable charging current IpRG. The programmable charging current can be expressed as: where R450 is the resistance of resistor 450.

The electric valley 471 is used to generate an integrated signal. The switch 46 is connected between the drain of the body 422 and the capacitor 471. The switch 460 is turned on and off by the discharge time signal Sds. Switch 462 is coupled in parallel with capacitor 471 for discharging capacitor 471. At the Cx end of the integrator 400, a second programmable capacitor 93 is connected in parallel with the capacitor 471' to provide a close relationship between the integrator 400 (quad) constant and the switching frequency. The second programmable capacitor 930's electrical hybrid C (four) depends on the hybrid group Ρν· $ _ also changes. The switching loss periodically conducts an integral signal to capacitor 472 for generating a current feedback signal %. The ignition and signal PLS control switch 461 is turned on and off. The current feedback signal across the capacitor 472 can be obtained by:

Vi = 1 Vw ~R450 X(C471 + C930)XT~X ^ (17) According to equations (4)-(7), the current feedback signal Vi and the secondary side switching current Is and the output current of the power supply are 1〇 Have a close _. Therefore, equation (9) can be rewritten as: 16 (18) 1251976

Vi = so χ --- x Rs x |〇Tnp where m is a fixed value and can be determined by: (19) m __ R210 X (C215 + C910) Vosc R450 X (C471 + C930) Vref resistance 450 The resistance value R45❶ is closely related to the resistance value r2(1) of the resistor 21〇. The capacitance value of the capacitor 471 is closely related to the capacitance value c93() of the capacitor 930 and the capacitance value C215 of the capacitor 215 and the capacitance value Gw of the capacitor 910. Therefore, the current feedback signal 乂 is proportional to the output current of the power supply 1〇. Fig. 8 is a circuit diagram showing a pulse width modulator 5A according to the present invention. The pulse width modulator 5 includes a S NAND gate 511, a D-type flip-flop 515, an AND gate 519, a blanking circmt 520, an inverter 512, and an inverter 518. The 〇 input of the 正-type flip-flop 515 is pulled up to the supply voltage Vcc. The oscillating signal PLS drives the input of the inverter 512. The output of the inverter 512 D f jl & ii 515 is input to the clock, and (4) the switching base is enabled. The output of the D-type positive and negative 515 is connected to the first terminal input of the brake 519. The second end of the gate 519 is connected to the output of the inverter 512. Nab 519 outputs this switching signal PWM is used for city power supply 11. ^The resetter of the flip-flop 515 is connected to the output of the test. The first input of the NA 511 is provided by the reset signal (should be s(4)) RST. The period causes the switching signal to be the disabled state gate ===7_ to the blanking circuit 52G_, and the switching signal is simply the minimum on time (minimumon-time) of the stone protection switching signal %_. Switch

Facet _ face the minimum money time & this silk card - an appropriate v __ sample. The discharge time I side inductance value LS is as shown in equation (2〇), and the discharge time & can be expressed as -------

Ls=(^-)2xLp 17 (20) (21) 1251976 τ /- V IN D NS τ

Tds =( -)x X 1 ON ----------------

Vo + Vf Tnp where TON is the on time of the switching signal Vpwm.

The input of the occlusion circuit 520 is provided by the switching signal Vpwm. When the switching signal VpwM is enabled, the blanking circuit 520 will generate a blanking signal VBLk to disable the reset of the D-type flip-flop 515. The blanking circuit 520 includes a NAND gate 523, a current source 525, a capacitor 527, a transistor 526, and inverters 521 and 522. The switching signal VPWM is supplied to the input of the inverter 521 and the first terminal input of the NAND gate 523. Current source 525 charges capacitor 527. The transistor 526 and the capacitor 527 are connected in parallel. The output of inverter 521 controls the turn-on and turn-off of transistor 526. The input of inverter 522 is coupled to capacitor 527. The output of inverter 522 is coupled to the second terminal input of NAND gate 523. The output of the NAND gate 523 outputs the blanking signal VBLK. The current of the current source 525 and the capacitance of the capacitor 527 determine the pulse width of the masking signal ~^^. The input of inverter 518 is coupled to the output of NAND gate 523. The output of inverter 518 produces a clear signal CLR for controlling the turn-on and turn-off of switch 123, switch 124, switch 340 and switch 462.

Figure 9 is a circuit diagram showing the addition 600 according to the present invention. An operational amplifier 610, a transistor 620, a transistor 621, a transistor 622 and a resistor 650 form a third V-to-I converter for generating a current l622 according to the output of the ramp signal RMP. The operational amplifier is amplified, and the positive input of 611 is provided by the current signal Vcs. The inverting input of the operational amplifier 611 is coupled to the output system for establishing the operational amplifier 611 as a buffer. The drain of the transistor 622 is connected to the output of the operational amplifier 611 via a resistor 651. The slope signal vSLP is generated at the pole of the transistor 622. The slope signal VSLp is thus closely related to the ramp signal Rjvjp and the current signal Vcs. Figure 10 is a diagram showing a module generator 9A in accordance with a preferred embodiment of the present invention. A clock genemtor 951 generates a clock signal CK. A plurality of registers 971, 972 and 975, and an XOR gate 952 form a linear shift register, which is used to generate a linear code according to the clock signal CK (iinear C0(je). x〇r gate 952 The input determines the polynomial (polynGmials) of the linear displacement 18 1251976 register and determines the output of the linear shift register. The digital pattern code PN··Ρι uses the part derived from the linear code. Optimized application. Furthermore, in order to generate the frequency jump characteristic to reduce the electromagnetic interference of the power supply, a module generator generates a digital module code ρΝ · · Ρι. The first programmable capacitor 9ι The 〇 is connected to the oscillating device 2 〇〇 and the module generator 910, according to the digital module code Ρ ν, the output of the Ρ ι is used to modulate the switching frequency of the switching signal vPWM. The second programmable capacitor 93 连接 is connected The integrator_disk module generator 900 is configured to make the integrator time constant constant and the switching frequency. The digital module code PN · 々 controls the capacitance of the first programmable capacitor _ and the second capacitor 930 Value. The electric diagram of the type 11 is displayed according to this The capacitance of the programmable capacitor program of the preferred embodiment of the month is the same as that of the second programmable capacitor 93. The program ^^^#^t^^4(switching-capacitw sets), C 〇s also. .sN separately form a switched capacitor device. Switch &capacitance;; 2 and switch s2 and capacitor 〇 2 are (four) connection, _ & and capacitor Cn series cargo connection, group code Ρ ν,. Turn-on and turn-off of the switch S1, S2, ..Sn, the value of the digital-to-digital capacitance. 熟悉j The familiarity of the private capacitor can be modified without departing from the structure of the spirit and scale of the present invention. Change, from the above-mentioned view of F, the scope of the patent application for Benfa's ## and its equivalent explanation can be regarded as the same as the hair of the hair. The one that meets the following requirements is as follows: 19 1251976 [Simple description of the drawing] Attached here The drawings are used to clearly describe the present invention, and are cited and included in the detailed specification, the following description of the present invention, and the detailed description of the principles of the present invention. Figure 1 shows the power supply. Circuit block diagram with switching control device, Figure 2 shows power supply and switching Main waveform of the device, FIG. 3 shows a controller according to a preferred embodiment of the present invention; FIG. 4 shows a voltage waveform detector according to a preferred embodiment of the present invention, and FIG. 5 shows a waveform according to the present invention. The oscillator of the preferred embodiment;

6 is a current waveform detector according to a preferred embodiment of the present invention; FIG. 7 is a diagram showing an integrator according to a preferred embodiment of the present invention; and FIG. 8 is a circuit diagram showing a pulse width modulator according to the present invention. Figure 9 is a circuit diagram showing an adder in accordance with the present invention; Figure 1 is a block diagram showing a module generator in accordance with a preferred embodiment of the present invention; and Figure 11 is a view showing a programmable capacitor in accordance with a preferred embodiment of the present invention. [Main component symbol description] 10 Transformer 20 Transistor 30 Current sense resistor 31 Capacitor 32 Capacitor 40 Rectifier 45 Capacitor 50 Resistor 51 Resistor 60 Rectifier 65 Capacitor 70 Controller 71 Operational Amplifier 72 Operational Amplifier 73 Comparator 74 Comparator 75 Comparator 79 NAND gate 20 1251976 80 Programmable current source 81 Double carrier transistor 82 Double carrier transistor 83 Resistor 84 P mirror transistor 85 P mirror transistor 86 P mirror transistor 87 η mirror transistor 88 η mirror transistor 100 Voltage Waveform Detector 110 Capacitor 111 Capacitor 115 Capacitor 121 Switch 122 Switch 123 Switch 124 Switch 125 Switch 130 Diode 131 Diode 135 Current Source 150 Operational Amplifier 151 Operational Amplifier 155 Comparator 156 Critical Signal 161 Inverter 162 Inverter 163 NAND gate 164 AND gate 165 AND gate 166 AND gate 170 D-type flip-flop 171 D-type flip-flop 180 current source 181 transistor 182 capacitor 190 sample pulse generator 200 oscillator 201 operational amplifier 202 operational amplifier 205 Comparator 210 Resistor 211 Resistor 215 Capacitor 216 Capacitor 230 On 231 Switch 232 Switch 233 Switch 234 Switch 250 Transistor 1251976 251 Transistor 252 Transistor 253 Transistor 254 Transistor 255 Transistor 259 Transistor 260 Inverter 300 Current Waveform Debt Sense 310 Comparator 320 Current Source 330 Switch 340 Switch 350 Switch 361 Capacitor 362 Capacitor 400 Integrator 410 Operational Amplifier 411 Operational Amplifier 420 Transistor 421 Transistor 422 Transistor 423 Transistor 424 Transistor 425 Transistor 450 Resistor 452 Resistor 460 Switch 461 Switch 462 Switch 464 Switch 466 Switch 468 Switch 471 Capacitor 472 Capacitor 473 Capacitor 474 Capacitor 500 Pulse Width Modulator 511 NAND Gate 512 Inverter 515 D-type Reactor 518 Inverter 519 AND Gate 520 Blank Circuit 521 Inverter 522 Inverter 523 NAND Gate 525 Current Source 526 transistor 527 capacitor 1251976 600 adder 611 operational amplifier 621 transistor 650 resistor 900 module generator 930 second programmable capacitor 952 XOR gate 972 register 610 operational amplifier 620 transistor 622 transistor 651 resistor 910 a programmable capacitor 951 Generator 971 register register 975

twenty three

Claims (1)

1251976 j gas. The film bursts (: more) to replace the storm, one-one-one 'noisy two hearts' feelings · · · ΙββΓ Ten, the scope of application for patents: 1 · A switching controller for primary side control The power supply includes: a switching power switch for switching a transformer through a current sensing device; wherein the transformer is connected to an input voltage of the power supply; a switching signal, controlling the switching power switch, The voltage output detector is connected to the transformer, and a voltage signal is generated by the auxiliary winding of the transformer by multiple sampling, thereby generating a voltage back. a signal and a discharge time signal; wherein the discharge time signal indicates a discharge time of the transformer; a current waveform detector connected to the current sensing device for measuring the current signal for generating a current waveform signal; The current signal is generated according to the primary side switching current of the transformer; an integrator, by integrating the current waveform signal and the discharge Time for generating the current feedback signal; the oscillator </ RTI> is used to generate a vibration signal to determine the switching frequency of the switching signal; a voltage loop error amplifier and a current loop error amplifier respectively for amplifying the voltage feedback a signal and the current feedback signal; and a pulse width modulator, according to the output of the voltage loop error amplifier and the current loop error of the output of the Lu's generation to generate the switching signal; wherein 'in the switching signal The cut-off time is used to generate the voltage feedback signal by sampling the voltage signal and the discharge time of the transformer; and measuring the current signal of the transformer during the on-time of the switching signal to generate current feedback a switching signal, wherein the switching signal is generated according to the voltage feedback signal and the current feedback signal. 2. The switching controller according to claim 1, further comprising: a programmable current source, An input connected to the voltage waveform detector for temperature compensation; 24 wherein the smear current source is based on the control The temperature produces a programmable current. 3. The switching control method described in the first application of the patent application, the step further comprises: a module generator for generating a digital module code; a type of electric valley connected to the oscillator and the module generator, according to the digital module code, for modifying the switching frequency; and a second programmable code, connecting the job integrator and the mode domain The time constant for the integral is closely related to the switching frequency; wherein the digital module code controls the capacitance of the first programmable capacitor and the second programmable capacitor. 4. According to the switching control described in the first item of the patent application, the time constant of the integral lion has a close relationship with the switching period of the switching signal. 5. The switching controller of claim 1, wherein the voltage waveform detector comprises: a sampling pulse generator for generating a sampling pulse signal; a critical signal, wherein the critical signal is added The voltage signal is used to generate a level shift signal; a first capacitor and a second capacitor; a first signal generator for generating a first sample signal and a second sample signal, wherein the first sample signal is The second sampling signal is used to alternately sample the voltage signal, wherein the first sustain voltage and the second sustain voltage are respectively maintained across the first capacitor and the second capacitor, wherein the first sampling signal and the The second sampling signal is alternately generated according to the sampling pulse signal period during the period of the enabling state of the discharging time signal; wherein a delay time is inserted at the beginning of the discharging time signal, wherein the first sampling signal a sampling signal and the second sampling signal are disabled during a period of the delay time; a buffer amplifier, the first sustain voltage and the second High voltage holding voltage to generate 25 a sustaining signal; a second output capacitor for sampling the sustain signal for outputting the voltage feedback signal; and a first read generator for generating the discharge time signal, when the switching signal is disabled The discharge time signal is an enable state, wherein after the delay time, once the level displacement is lower than the feedback signal, the service power is reduced to the disabled state, and the Wei electricity time is also disabled. As long as the switch is enabled. 6. The controller of claim 1, wherein the voltage waveform detector repeatedly samples the voltage signal to terminate, and (4) generates the voltage feedback signal, wherein the transformer is in the second The switching controller of the third aspect of the invention is the same as the switching controller of the third aspect of the invention, wherein the module generator comprises: a clock generator for Generating a clock signal; and a linear shift register for generating the digital module code according to the clock signal. 8. The switching controller of claim 1, wherein the vibrator comprises: a first voltage to current converter for generating an oscillating charging current and an oscillating discharging current, wherein the first voltage conversion The current converter comprises an oscillating operational amplifier, an oscillating resistor and a sinusoidal crystal; a oscillating capacitor connected in parallel to the first programmable capacitor; a first oscillating switch, wherein the first apex of the first oscillating switch Provided by the oscillating charging device, and the second end of the first oscillating switch is connected to the first oscillating capacitor; and a second oscillating switch, wherein the first end of the second oscillating switch is connected to the Oscillation is slightly, and the second end of the second oscillation switch is driven by the oscillating discharge current; an oscillating comparator having a non-inverting input connected to the first oscillator capacitor, wherein 兮26 te 9 turns (heart ^ replacement!: ^ 1^ - 丨 _ I | 丨丨 · 丨丨丨丨丨丨丨, (10) | |, m _... Brother a comparator produces the oscillation signal; - Oscillation ratio fresh 'has - The positive input connects to the a capacitor, wherein the button comparator generates the oscillation signal; - a third oscillator "1 off, having a first-end phase supplied by a high threshold voltage, and a second terminal connected to a negative terminal input of the oscillation comparator; Μ - a fourth-vibration 1 switch having a first-end terminal supplied by a low threshold voltage, and a second terminal connected to the negative-end input of the oscillation comparator; and a ""-oscillation inversion n' having - The round man is connected to the new one. The round-out end is used to generate the reverse-phase oscillation. The towel is used to read the second oscillation and the fourth oscillation. The reverse-phase vibration signal is turned on. Or, the first vibrating switch and the third vibrating end are cut off. 9. If the switching control (4) described in item 8 is applied, the wiper of the first vibrating capacitor is connected in parallel. The first programmable capacitor includes a oscillating capacitance, wherein the oscillating switching capacitor is turned on or off by the digital module code. 10. The switching control as described in claim 1 Following, the current wave paste includes: σ-peak detector, by volume The peak of the current signal is used to generate a peak current signal, a third capacitor for maintaining the peak current signal, a second output capacitor for generating the current waveform signal, and a switch for turning on the peak current signal To the second output capacitor, wherein the open relationship is turned on or off by the oscillation signal. The switch controller according to claim 1, wherein the integrator comprises: - second Voltage to current conversion n, by time op amp, time power = with time crystal 27 1 skirt 5 | 1 soil for the wall, in.[- ...' '** ·" « rl -.·, · a _ body a group consisting of a charging current of the first program; a voltage-to-current converter generates a signal according to the current waveform signal, and the capacitors of the program are connected in parallel to generate an integrated signal; The first end of the switch is connected to the time capacitor by the programmable charging current, and the first end of the switch is connected to the time switch by the discharge time signal. Turn on or cut f; f a switch n day alone capacitor connected in parallel, (4) discharge the time capacitor; second output capacitor ' is used to output the current feedback signal; The third switch of the scale and integral domain is used, and the third switch is turned on or off by the oscillation signal. 12. If the method is as follows, please refer to the switching control described in item 〖, in which the material exchange has a maximum gate--the object is called the enable state, and the minimum value of the discharge time can be ensured. The voltage signal is sampled multiple times. 13·- Switching control II, applied to the power supply of the secondary side control, including ··· switching power off, rib switching-transformer, wherein the transformer is connected to the input voltage of the power supply; -Switching the signal, controlling the switching of the gods, the output voltage and the maximum output current of the rib-stabilized electric enchantment; - voltage wave, · connection _ change _, the sampling of the voltage generated by the auxiliary winding of the mixer Therefore, the voltage feedback signal and the discharge time signal are generated; wherein the discharge time signal indicates the discharge time of the transformer; an oscillator 'is used to generate an oscillation signal to determine the switching frequency of the switching signal; a voltage loop error amplifier and a current loop error amplifier for respectively amplifying the voltage feedback signal and the current feedback signal; and 28 13⁄43⁄43⁄4. (replacement replacement; ............. II = wide modulation The output of the amplifier is generated according to the output of the error amplifier of the electric Wei road and the output of the current loop. The 丄-controller is connected to the transformer at the cutoff time of the switching signal. During this period, the voltage signal and the discharge time of the converter are used to generate a voltage feedback signal, wherein the switching signal is generated according to the voltage feedback signal. The switching controller of claim 13 , further comprising: a private current source connected to the input end of the voltage waveform controller for temperature compensation, wherein the programmable current test Controlling the temperature of H to generate a programmable current. The switching controller of claim 13, further comprising: a module generator for generating a digital module code; An electric valley connected to the oscillator and the module generator for modulating the switching frequency according to the digital module code; and a second programmable capacitor connected to the integrator and the module And the time constant of the integrator is closely related to the switching frequency, wherein the digital module code controls a capacitance value of the first programmable capacitor and the second programmable capacitor. 29 1251976 ΓΜΜ ~ΊΠ[ι_ I III u mr «uiBuniUMrm clear«II tKtrnmm-Mm丨_«u 11 师(四).;Um* -, 光月日修 (more j is replacing h 94 :. 咖-'-H ll( ......,. XI. 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