1251398 94.12.16 0851 ltwfl.doc/006 九、發明說明： 本發明是有關於一種振盪器電路。特別是關於一種精 準電阻電容式振盪器電路，不易受製程溫度之影響。 振盪器一般可產生一具有固定頻率的方形脈衝’其在 邏輯電子電路有廣泛的用途。傳統由固定電阻電容(RC)構 成的環狀振盪器，如第1圖所示。 於第1圖中，一電流源100根據其固定的電阻R ’可 產生一電流I=VBG/R，其中VBG代表由一帶隙電路(Bandgap circuit)所產生的一'穩定電壓。電流源1 〇〇爲習知技藝’於 此不詳述。振盪器電路根據電流源100之電阻値及電路內 電容値，於輸出端Kout產生一振盪脈衝信號。 電流源100之一端接地，而另一端連接於振擾器的開 關電路，其包括一第一路徑102a與一第二路徑102b。第一 路徑l〇2a與一第二路徑l〇2b相對稱且並聯。第一路徑l〇2a 包括串聯的一 NM0S電晶體與一 PM0S電晶體。NM0S電 晶體之源極連接到電流源10(^PMOS電晶體之源極連接到 一電壓源Vps〇NM0S電晶體與PM0S電晶體的連接節點A 連接於一電容l〇4a，再接著連接到一地電壓。由於避免受 系統電源VCC的影響，電壓源Vps則由一調節器 (regiUato〇l〇i輸出。調節器ι〇1，接收系統電源VCC而輸 出固定電壓源Vps供震盪器之用。 NMOS電晶體與PM0S電晶體的二閘極相連，且連接 到一輸出端點Kout。另外，節點A又連接到一史密特 (Schmitter)反向器1〇6a。史密特反向器1〇6a的輸出端又連 4 1251398 0851 1twfl.doc/006 94.12.16 接到一反與閘l〇8a(NAND Gate)。反與閘108a的輸出端又 連接到一反向器。反向器的輸出端又連接到一反與閘 ll〇a。反與閘110a輸出端爲信號輸出端Kout，其又回饋到 第一路徑102a之NM0S電晶體與PM0S電晶體之閘極。 爲得到工作週期（duty cyde)50%的信號脈衝，第二路 徑l〇2b也包括串連的一 NM0S電晶體與一 PM0S電晶體。 而節點B也並聯到地電壓之電容l〇4b(同104a之値），及後 續串接有一史密特反向器l〇6b，反與閘l〇8b，反向器以及 反與閘110b。反與閘108a與反與閘l〇8b相互接收其輸出。 同樣地，反與閘ll〇a與反與閘ll〇b相互接收其輸出。 根據第1圖的傳統電路，於節點A與節點B的電壓波 形如第2圖所示。其相差爲180度的相位，但是其波形爲 交替的下降波段與穩定高準位。其高準位爲電壓源Vps， 而低準位爲史密特反向器106a的觸發電壓。其電容器上的 電壓下降斜率由RC決定’而下降緣之轉換電壓由史密特反 向器106a，106b所決定。因此，傳統電路下降緣之轉換電 壓易受製程及溫度彭響因而改變其輸出頻率，且需要一-尝周 節器(regulator)電路，因而增加其複雜度。 有鑑於此，本發明提供一種電阻電容式振盪器電路， 包括二比較器’具有較簡化的電路結構，且不易受系統電 源VCC製程及溫度影響。另外也可節省電源消耗。 本發明之一種電阻電容式振盪器電路，由一電流源驅 動，包括對稱且並聯的第一開關電路與第二開關電路。第 5 1251398 0851 ltwfl.doc/006 94.12.16 一開關電路有一信號輸出端及第一節點。第二開關電路有 一互補信號輸出端及第二節點。任取二節點之一，同時輸 入給第一比較器與第二比較器。第一比較器接又收一 1/2VBG電壓，而第二比較器又接收2VBG電壓。第一比較器 輸出到一 PMOS電晶體，而第二比較器輸出到一 NMOS電 晶體◦ PMOS電晶體與NMOS電晶體串聯，且連接於系統 電源與地電壓之間。此二電晶體串聯處又串聯一栓鎖器與 一^反向器。检鎖器之輸出連接於互補ί目號輸出麵而反向窃1 之輸出連接於信號輸出端。 本發明另外提供一種電阻電容式振盪器電路，被一電 流源驅動，該電流源有一穩定的輸出電壓VBG。此振邊器 包括：一第一開關電路，有一第一信號輸出端與一第一節 點，其中第一信號輸出端輸出一第一輸出脈衝信號’而第 一節點經一第一電容器與一地電壓連接。一第二開關電 路，與該第一開關電路對稱且並聯，有一第二信號輸出端 與一第二節點，其中第二信號輸出端輸出一第二輸出脈衝 信號，與第一輸出脈衝信號互補，而第二節點透過一第二 電容器與地電壓連接。該第一電容器與該第一電容器有相 等電容値。一第一比較器，與第一節點及第二節點二者其 一之一選定節點連接，且接收一固定下限電壓値。一第二 比較器，與選定節點連接，且接收一固定上限電壓値。一 開關控制電路，接收第一比較器與第二比較器之輸入’且 有二輸出端分別連接於第一開關電路與第二開關電路之第 一信號輸出端與第二信號輸出端。 6 1251398 0851 ltwfl .doc/006 94.12.16 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖繪示一傳統電阻電容式振盪器電路； 第2圖繪示於第1圖中，於節點A與B之電壓波形； 第3圖繪示依照本發明，一電阻電容式振盪器電路；以 及 第4圖繪示依照本發明，於第3圖中，於節點C與D 之電壓波形。 標號說明： 100，200 :電流源 101 :調節器 102a :第一路徑 102b :第二路徑 104a，104b :電容器 106a，106b :史密特反向器 108a，108b :反與閘 110a，110b :反與閘 202a，202b : PMOS 電晶體 204a，204b : NMOS 電晶體 206a :第一電容 206b :第二電容 208a :第一比較器 1251398 0851 ltwfl .doc/006 2〇Sb :第二比較器 210a :第一 MOS電晶體 210b :第二MOS電晶體1251398 94.12.16 0851 ltwfl.doc/006 IX. INSTRUCTIONS: The present invention relates to an oscillator circuit. In particular, a precision resistor-capacitor oscillator circuit is not susceptible to process temperature. Oscillators typically produce a square pulse with a fixed frequency, which has a wide range of uses in logic electronic circuits. A ring oscillator consisting of a fixed resistor capacitor (RC) is shown in Figure 1. In Fig. 1, a current source 100 generates a current I = VBG / R according to its fixed resistance R ', wherein VBG represents a 'stable voltage' generated by a bandgap circuit. Current source 1 is a prior art and is not described in detail herein. The oscillator circuit generates an oscillation pulse signal at the output terminal Kout according to the resistance of the current source 100 and the capacitance 电路 in the circuit. One end of the current source 100 is grounded, and the other end is connected to the switching circuit of the oscillator, which includes a first path 102a and a second path 102b. The first path l〇2a is symmetrical with a second path l〇2b and is connected in parallel. The first path l〇2a includes an NMOS transistor in series and a PMOS transistor. The source of the NM0S transistor is connected to the current source 10 (the source of the PMOS transistor is connected to a voltage source Vps〇NM0S transistor is connected to the connection node A of the PMOS transistor to a capacitor l〇4a, and then connected to a Ground voltage. Because it is protected from the system power supply VCC, the voltage source Vps is output by a regulator (regiUato〇l〇i. Regulator ι〇1, receiving system power supply VCC and outputting a fixed voltage source Vps for the oscillator. The NMOS transistor is connected to the two gates of the PMOS transistor and is connected to an output terminal Kout. In addition, the node A is connected to a Schmitter inverter 1〇6a. Schmidt reverser 1 The output of 〇6a is connected to a gate NAND8a (NAND Gate). The output of the NAND gate 108a is connected to an inverter. The inverter is connected to an inverter. The output terminal is connected to a reverse gate 〇a. The output of the reverse gate 110a is a signal output terminal Kout, which is fed back to the gate of the NM0S transistor and the PMOS transistor of the first path 102a. (duty cyde) 50% of the signal pulse, the second path l〇2b also includes a series of NM0S electricity The body is connected to a PM0S transistor, and the node B is also connected in parallel to the capacitance of the ground voltage l〇4b (the same as 104a), and the subsequent series connection has a Schmidt inverter l〇6b, the inverse gate and the gate l〇8b, The inverter and the anti-gate 110b. The anti-gate 108a and the anti-gate l8b receive each other's output. Similarly, the anti-gate 〇a and the anti-gate 〇b receive each other's output. In the conventional circuit, the voltage waveforms at node A and node B are as shown in Fig. 2. The phase difference is 180 degrees, but the waveform is an alternating falling band and a stable high level. The high level is the voltage source Vps. The low level is the trigger voltage of the Schmidt inverter 106a. The slope of the voltage drop across the capacitor is determined by the RC' and the switching voltage of the falling edge is determined by the Schmidt inverters 106a, 106b. Therefore, the conventional circuit The switching voltage of the falling edge is susceptible to the process and temperature, thus changing its output frequency, and requires a -regulator circuit, thereby increasing its complexity. In view of this, the present invention provides a resistor-capacitor oscillator. Circuit, including two comparators, has a simplified circuit It is not susceptible to system power supply VCC process and temperature. It can also save power consumption. A resistor-capacitor oscillator circuit of the present invention is driven by a current source, including a first switch circuit and a second switch that are symmetric and parallel. Circuit No. 5 1251398 0851 ltwfl.doc/006 94.12.16 A switching circuit has a signal output and a first node. The second switching circuit has a complementary signal output and a second node. Any one of the two nodes is input to the first comparator and the second comparator. The first comparator receives another 1/2 VBG voltage, and the second comparator receives a 2 VBG voltage. The first comparator is output to a PMOS transistor, and the second comparator is output to an NMOS transistor. The PMOS transistor is connected in series with the NMOS transistor and is connected between the system power supply and the ground voltage. The two transistors are connected in series with a latch and an inverter. The output of the lock is connected to the complementary output surface and the output of the reverse 1 is connected to the signal output. The present invention further provides a resistor-capacitor oscillator circuit driven by a current source having a stable output voltage VBG. The edger includes: a first switching circuit having a first signal output end and a first node, wherein the first signal output terminal outputs a first output pulse signal 'the first node passes through a first capacitor and a ground Voltage connection. a second switching circuit symmetrical and parallel with the first switching circuit, having a second signal output end and a second node, wherein the second signal output end outputs a second output pulse signal complementary to the first output pulse signal The second node is connected to the ground voltage through a second capacitor. The first capacitor has a capacitance 値 equal to the first capacitor. A first comparator is coupled to one of the first node and the second node and receives a fixed lower limit voltage 値. A second comparator is coupled to the selected node and receives a fixed upper limit voltage 値. A switch control circuit receives the inputs of the first comparator and the second comparator and has two outputs connected to the first signal output and the second signal output of the first switch circuit and the second switch circuit, respectively. The above objects, features, and advantages of the present invention will become more apparent and understood. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conventional resistive-capacitor oscillator circuit; FIG. 2 is a diagram showing waveforms of voltages at nodes A and B in FIG. 1; and FIG. 3 is a diagram showing a waveform according to the present invention. A resistor-capacitor oscillator circuit; and FIG. 4 illustrates voltage waveforms at nodes C and D in FIG. 3 in accordance with the present invention. DESCRIPTION OF REFERENCE NUMERALS 100,200: current source 101: regulator 102a: first path 102b: second path 104a, 104b: capacitor 106a, 106b: Schmidt inverter 108a, 108b: anti-gate 110a, 110b: reverse AND gates 202a, 202b: PMOS transistors 204a, 204b: NMOS transistor 206a: first capacitor 206b: second capacitor 208a: first comparator 1251398 0851 ltwfl .doc/006 2〇Sb: second comparator 210a: A MOS transistor 210b: a second MOS transistor
Vps :電壓源 實施例 本發明的主要特徵之一是利用二比較器，構成一開關 控制迴路，可有效降低電路的複雜性，且不易受系統電源 VCC與溫度的影響，另外也可節省電源消耗。 以下舉一實施例，做爲本發明特徵的描述說明，但是 本發明並不受限於實施例。 第3圖繪示依照本發明，一電阻電容式振盪器電路。 於第3圖中，一電流源200連接於一系統電源VCC，且驅 動本發明之振盪器電路。電流源200例如由帶隙電路 (Bandgap circuit)設計而成，其電流由vBG/R所決定。VBG 是帶隙電路提供的一穩定電壓，不易受溫度所影響。電流 源200 —實際的應用，可分二部分，可於另一端接地。 振盪器電路一般包括一第一開關電路與一第二開關電 路。第一開關電路與第二開關電路由電流源2 G 0所驅動。 第一開關電路與一第二開關電路有對稱的元件，並聯在一 起。第一開關電路包括串聯的一 PMOS電晶體202a與一 NM0S電晶體204a。PM0S電晶體202a之源極連接於電流 源200，NM0S電晶體204a之源極也連接於接地端部分的 電流源200。二電晶體202a，204a的汲極連接於第一節點 C。第一節點C有一第一電壓VI。第一節點C後續又串接 8 1251398 0851 ltwfl.doc/006 94.12.16 一第一電容206a，而後接地。二電晶體2〇2a，204a的閘極 共接於一第一信號輸出端Kout。 第二開關電路與第一開關電路並聯，也包括一 PM0S 電晶體202b與一 NM0S電晶體204b ◦ PM0S電晶體202b 之源極也連接於電流源200。NM0S電晶體204b之源極也 連接於接地端部分的電流源200。二電晶體202b，204b的 汲極連接於第二節點D。第二節點D有一第二電壓V2。第 二節點D後續又串接一第二電容206b，而後接地。第一電 容2〇6a與第二電容206b之電容値相等，與電流源的電阻 可產生一 RC的震盪信號。二電晶體202b，204b的閘極共 接於互補之第二信號輸出端Bar(Kout)，又標示爲^。 爲控制開關電路的運作，以產生一固定頻率的信號輸 出脈衝，本發明又包括二比較器208a，208b，及配接的M0S 電晶體，栓鎖器，及反向器等。 由第一節點C與第二節點D任取其一當爲一工作電壓 波，例如取第一節點C的第一電壓VI爲工作電壓波。事 實上’第一節點C與第二節點D的電壓波爲相互差180度 相位的電壓波，如第4圖所示。第一節點C分別連接於第 一比較器208a與第二比較器208b之輸入端，因此第一電 壓VI同時輸入二比較器208a，208b，例如於正輸入端。 第一比較器208a的負輸入端接收一固定下限電壓，例如 1/2VBG，而第二比較器208b的負輸入端接收一固定上限電 壓’例如2VBG。二比較器208a，208b的基本特徵是，爲了 配合後續的電路，於二穩定電壓界線之間，產生穩定循環 1251398 0851 ltwfl.doc/006 94.12.16 的邏輯狀態。VBC其有穩定電壓不易受溫度影響。 就以本實施例而言，第一比較器208a配合第一電壓 VI的波形，循環輸出0111的邏輯狀態，而第二比較器208b 循環輸出0010的邏輯狀態。本發明僅顯於此實施例的電 路，及邏輯狀態。 由於比較器208a，208b的輸出邏輯狀態是循環變化， 其例如再配合包括二MOS電晶體及栓鎖器，即可達到輸出 信號的波形。二MOS電晶體例如包括串接的一第一 MOS 電晶體210a (例如爲PMOS電晶體）與一第二MOS電晶 體210b (例如爲NMOS電晶體）。第一 MOS電晶體210a 之源極連接於系統電源VCC，閘極連接於第一比較器208a 的輸出端，而汲極連接於一栓鎖器之一端。第二M〇S電晶 體210b的汲極也共同連接於該栓鎖器之一端，閘極連接於 第二比較器208b的輸出端’而源極連接於地電壓。栓鎖器 的另一端爲互補的第二信號輸出端Bar(Koiit)，並且回饋到 第二開關電路之二電晶體202b，204b之二閘極。互補的第 二信號輸出端Bar(Kout)又與一反向器連接’此反向器輸出 端得到第一信號輸出端Kout，並連接到第一開關電路之二 電晶體202a，204a之二閘極。 上述二比較器208a，208b的輸出，使得第一 M0S電 晶體210a與第二M0S電晶體2l〇b不會同時被打開（ON)， 因此不會有太大的DC電流，其發生於傳統的振Μ #電 路，其原因例如是電容器連接於史密特反向器106a，106b， 特別是於接近Vps/；2時會有較大的DC電流。 1251398 08511twfl.doc/006 94.12.16 於第3圖中，由於NMOS電晶體2(Ma、2(Mb，也連接 到同電流之電流源200，因此第一電壓VI與第二電壓V2 形成週期的三角電壓波，例如是正三角電壓波。第一電壓 VI與第二電壓V2相差一 180度的相位。因此可任取第一 電壓VI與第二電壓V2任其一爲一工作電壓，輸入給二比 較器208a，208b的正輸入端。另外二比較器208a，208b 的負輸入端分別輸入1/2VBG與2VBG。由於VBC具有溫度補 償效應，不易受溫度影響，例如於_4〇°C與115°C之間。因 此有精確的振盪頻率。 上述二比較器208a，208b的正負端輸入關係，並不一 定如實施例的連接方法，其主要能產生一穩定循環的輸出 的邏輯即可。至於二M〇s電晶體210a，210b及栓鎖器及 反向器可視爲一開關控制電路，以適當輸出互補的預計得 到的方形信號脈衝。 本發明，因此至少具有下數優點； 1. 電流一樣由VBG/R固定，故RC依然爲定値。 2. RC放電之時間，由兩個比較器，固定於1/2VBC與 2 V B 〇之間。由於其採用帶隙電路之電壓輸入’亦不受溫度 所影響。 3. 本發明不需額外的調節器(regulator)。傳統電路須 調節器以減少VCC的影響。 4. 本發明之第一 M0S電晶體210a與第二M0S電晶 體210b，配合比較器的輸出，不會同時被打開（0N) ’因此 不會有太大的DC電流。 1251398 0851 ltwfl .doc/006 94.12.16 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲Vps: Voltage Source Embodiment One of the main features of the present invention is to construct a switch control loop by using two comparators, which can effectively reduce the complexity of the circuit, is not easily affected by the system power supply VCC and temperature, and can also save power consumption. . The following embodiments are described as a description of the features of the present invention, but the present invention is not limited to the embodiments. Figure 3 illustrates a resistive capacitor oscillator circuit in accordance with the present invention. In Figure 3, a current source 200 is coupled to a system power supply VCC and drives the oscillator circuit of the present invention. The current source 200 is designed, for example, by a bandgap circuit whose current is determined by vBG/R. VBG is a stable voltage provided by the bandgap circuit and is not susceptible to temperature. Current source 200 - the actual application, can be divided into two parts and can be grounded at the other end. The oscillator circuit typically includes a first switching circuit and a second switching circuit. The first switching circuit and the second switching circuit are driven by a current source 2 G 0 . The first switching circuit and the second switching circuit have symmetrical components that are connected in parallel. The first switching circuit includes a PMOS transistor 202a and an NMOS transistor 204a connected in series. The source of the PM0S transistor 202a is connected to the current source 200, and the source of the NMOS transistor 204a is also connected to the current source 200 of the ground terminal portion. The drains of the two transistors 202a, 204a are connected to the first node C. The first node C has a first voltage VI. The first node C is subsequently connected in series with 8 1251398 0851 ltwfl.doc/006 94.12.16, a first capacitor 206a, and then grounded. The gates of the two transistors 2〇2a, 204a are connected in common to a first signal output terminal Kout. The second switching circuit is coupled in parallel with the first switching circuit, and also includes a PM0S transistor 202b and a NMOS transistor 204b. The source of the PM0S transistor 202b is also coupled to the current source 200. The source of the NM0S transistor 204b is also connected to the current source 200 of the ground terminal portion. The drains of the two transistors 202b, 204b are connected to the second node D. The second node D has a second voltage V2. The second node D is in turn connected in series with a second capacitor 206b and then grounded. The first capacitor 2〇6a is equal to the capacitance 値 of the second capacitor 206b, and the resistance of the current source generates an RC oscillating signal. The gates of the two transistors 202b, 204b are coupled to a complementary second signal output terminal Bar (Kout), also designated as ^. To control the operation of the switching circuit to produce a fixed frequency signal output pulse, the present invention further includes two comparators 208a, 208b, and mated MOS transistors, latches, and inverters. The first node C and the second node D are each taken as an operating voltage wave, for example, the first voltage VI of the first node C is an operating voltage wave. In fact, the voltage waves of the first node C and the second node D are voltage waves that are 180 degrees out of phase with each other, as shown in Fig. 4. The first node C is connected to the input of the first comparator 208a and the second comparator 208b, respectively, so that the first voltage VI is simultaneously input to the two comparators 208a, 208b, for example, at the positive input. The negative input of the first comparator 208a receives a fixed lower limit voltage, such as 1/2 VBG, while the negative input of the second comparator 208b receives a fixed upper limit voltage, e.g., 2 VBG. The basic feature of the two comparators 208a, 208b is that a logic state of the stable loop 1251398 0851 ltwfl.doc/006 94.12.16 is generated between the two stable voltage boundaries in order to cooperate with the subsequent circuits. VBC has a stable voltage that is not susceptible to temperature. In the present embodiment, the first comparator 208a cooperates with the waveform of the first voltage VI to cyclically output the logic state of 0111, and the second comparator 208b cyclically outputs the logic state of 0010. The present invention is only illustrative of the circuitry of this embodiment, and the logic state. Since the output logic state of the comparators 208a, 208b is a cyclic change, which, for example, further includes two MOS transistors and a latch, the waveform of the output signal can be achieved. The two MOS transistors include, for example, a first MOS transistor 210a (e.g., a PMOS transistor) and a second MOS transistor 210b (e.g., an NMOS transistor) connected in series. The source of the first MOS transistor 210a is connected to the system power supply VCC, the gate is connected to the output of the first comparator 208a, and the drain is connected to one end of a latch. The drain of the second M〇S transistor 210b is also commonly connected to one end of the latch, the gate is connected to the output terminal of the second comparator 208b and the source is connected to the ground voltage. The other end of the latch is a complementary second signal output terminal Bar (Koiit) and is fed back to the second gate of the second transistor 202b, 204b of the second switching circuit. The complementary second signal output terminal Bar(Kout) is further connected with an inverter. The inverter output terminal obtains the first signal output terminal Kout and is connected to the second transistor of the first switch circuit two transistors 202a, 204a. pole. The output of the above two comparators 208a, 208b is such that the first MOS transistor 210a and the second MOS transistor 203b are not turned ON at the same time, so there is not much DC current, which occurs in the conventional The vibrating #circuit is for example due to the fact that the capacitor is connected to the Schmidt inverters 106a, 106b, especially when approaching Vps/;2, there is a large DC current. 1251398 08511twfl.doc/006 94.12.16 In Figure 3, since the NMOS transistor 2 (Ma, 2 (Mb, also connected to the current source 200 of the same current), the first voltage VI and the second voltage V2 form a period The triangular voltage wave is, for example, a positive triangular voltage wave. The first voltage VI is different from the second voltage V2 by a phase of 180 degrees. Therefore, any one of the first voltage VI and the second voltage V2 can be used as an operating voltage, and is input to the second voltage. The positive input terminals of the comparators 208a, 208b. The negative inputs of the other two comparators 208a, 208b respectively input 1/2 VBG and 2 VBG. Since the VBC has a temperature compensation effect, it is not susceptible to temperature, for example, _4 〇 ° C and 115 Between ° C. Therefore, there is a precise oscillation frequency. The positive and negative input relationship of the above two comparators 208a, 208b is not necessarily the connection method of the embodiment, and it can mainly generate a logic of a stable loop output. The two M〇s transistors 210a, 210b and the latch and the inverter can be regarded as a switch control circuit for appropriately outputting complementary expected square signal pulses. The present invention therefore has at least the following advantages; By VBG/R Fixed, so the RC is still fixed. 2. The RC discharge time is fixed by two comparators between 1/2VBC and 2 VB 。. Because of its voltage input using the bandgap circuit, it is also unaffected by temperature. 3. The present invention does not require an additional regulator. The conventional circuit requires a regulator to reduce the influence of VCC. 4. The first MOS transistor 210a of the present invention and the second MOS transistor 210b, which cooperate with the output of the comparator, It will not be turned on at the same time (0N) 'so there will not be too much DC current. 1251398 0851 ltwfl .doc/006 94.12.16 In summary, although the present invention has been disclosed above with a preferred embodiment, it is not The scope of the present invention is defined by the scope of the appended claims, which are defined by the scope of the appended claims.