1249900 九、發明說明： 【發明所屬之技術領域】 +本《月係提供4幫浦式直流轉直流轉換器增益 笔路，特別是本發明係利用指數升壓架構串接或改變兩 =電^幫浦電路來提升電壓的倍率，可適用於晶片設 °。己隐、手持式電子產品及驅動電路等相關產業。 【先前技術】 目前串接式的電荷幫浦電路在串接級數少時，輸出 電壓倍率勉強可以隨著串接級數增加而增加，但當串接 級，增多時，若要再提升輸出電壓倍率，可能需要串接 ，夕級的電路’才能達到高倍率的電壓輸出，然而當級 ^二至某個程度’因金屬氧化半導擊QS)開關臨界 Κ Μ上升的關係’後面級數的開關可能無法正常運 作，造成輸出電壓受到限制，雖可利用時脈⑷⑽)來提 升金屬氧化半導體開關閘極控制電壓，以克服金屬氧化 ^導體開關的臨界電壓，使金屬氧化半導體開關得以正 常運作，但當級數太多或者升壓太高，使得後級的金 乳化半導體開關的臨界電&幅上升至超騎脈可 服的範圍’造成電荷幫浦電路無法有效卫作，且升 限制更易出現在輸入電壓較小的操作情況下，由於輪入 電壓小’其時脈的電壓也較小，無法克服金屬氧化： 體開關臨界電壓上升的現象將提早產生。 1249900 上述之電荷幫浦電路的架構，以 串聯，搭配適當的時脈== :導體St數線性的增力…一屬二 h體-極體之導通特性造成導通跨_的問題 母-級電路的跨壓損失’且當輸出 數： 二制氧化半導體二極…之源極端(s〇urc= :B，)。的電位差也越大，導致基板效應（二 古蚀—加嚴重’造成臨界電愿會隨充電電麼上升而提 :使！：母：級電路的跨壓損失隨著級數增加而提高， 將使取1¾可產生的電壓受到限制。 =解決上述的問題，可以利料㈣程改變基極端 的，接方式來改善，在製程上將使用浮動的井（floating =:，在金旦屬氧化半導體之外面’臨界電壓上升的情況 ^ ，，但影響仍然存在，且製程改變也變更了標準製 私，造成製作上的不便。」丨eh_TSQmg _所提出的Ncp 系列的修改（NCP1&NCP2)，為了解決每一級向後級 ?輸時’臨界電壓所造成的電壓浪費，利用後級產生的 回電，驅動前級的金屬氧化半導體開關（後極的高電壓 接至刚級金屬氧化半導體開關的閉極端），但由於後級 的臨界电壓上升十分嚴重，欲要產生夠大的閘極電壓（Vg) 才能克服，而後級的電壓已經受到臨界 得輸出電壓受到限制。 的々曰使 1249900 【發明内容】 因此，本發明之主要目的係在於提供一電路級數1249900 IX. Description of the invention: [Technical field to which the invention belongs] + This month provides four pump-type DC-to-DC converter gain pens. In particular, the present invention uses an exponential boosting architecture to cascade or change two=electric^ The pump circuit can increase the voltage multiplier and can be applied to the chip set. Hidden, hand-held electronic products and drive circuits and other related industries. [Prior Art] At present, when the number of series-connected charge pump circuits is small, the output voltage multiplication rate can be increased as the number of series-connected stages increases, but when the series-connected stage is increased, the output is to be increased again. Voltage multiplier, may need to be connected in series, the circuit of the eve level can reach the high-magnification voltage output, but when the level ^2 to a certain degree 'because of the metal oxide semi-guided hit QS) switch the critical Κ Μ rise relationship 'the number of stages The switch may not function properly, causing the output voltage to be limited. Although the clock (4) (10) can be used to raise the gate voltage of the metal oxide semiconductor switch to overcome the threshold voltage of the metal oxide switch, the metal oxide semiconductor switch can operate normally. However, when the number of stages is too high or the boost is too high, the critical electric & amplitude of the gold-emulsified semiconductor switch of the latter stage rises to the range of the super-accidental service, causing the charge pump circuit to be ineffective, and the limit is increased. It is more likely to occur in the case of a small input voltage, because the wheel-in voltage is small, and the voltage of the clock is also small, and the metal oxidation cannot be overcome: The phenomenon that the threshold voltage rises will occur early. 1249900 The above-mentioned structure of the charge pump circuit is connected in series with the appropriate clock ==: the linear force of the St-number of the conductor... The conduction characteristic of the two-body-pole body causes the problem of the conduction cross-_ mother-stage circuit The trans-voltage loss' and when the number of outputs: the source of the two-system oxidized semiconductor dipole... (s〇urc = :B,). The larger the potential difference, the substrate effect (two ancient eclipse - plus serious 'causes the critical electricity will rise with the charging power: make!: mother: the voltage loss of the stage circuit increases with the number of stages, will The voltage that can be generated by the 13⁄4 is limited. = Solve the above problem, you can improve the (4) process to change the base end, and improve the connection method. The floating well will be used in the process (floating =:, in the metal oxide semiconductor Outside the 'threshold voltage rises ^, but the effect still exists, and the process change has also changed the standard manufacturing, causing inconvenience in production." 丨eh_TSQmg _ proposed Ncp series modification (NCP1 & NCP2), in order to Solve the voltage waste caused by the critical voltage of each stage to the rear stage, and use the power generation generated by the latter stage to drive the metal oxide semiconductor switch of the previous stage (the high voltage of the rear pole is connected to the closed end of the rigid metal oxide semiconductor switch) ), but because the threshold voltage rise of the latter stage is very serious, it is necessary to generate a large gate voltage (Vg) to overcome, and the voltage of the latter stage has been subjected to the critical output voltage. To be limiting. 1,249,900 so that the said 々 SUMMARY OF THE INVENTION Accordingly, a primary object of the present invention is based is to provide a circuit of series
>、電路結構簡單及無輸出電壓限制之電荷幫 轉直流轉換器增益電路。 彳工>；，L 為達上述之目的，本發明係提供—電荷幫浦式直泣 轉直流轉換器增益電路’係藉由電荷幫浦輸出級跨壓^ 失修正電路（PG〇，使輸出級的切換開關能適當的阻止 輸出端的電荷倒灌回升壓電路中，同時使輸出級不會因 基體效應（body effect)而造成開關或二極體跨壓損^變 大的問題’改善輸出電塵的限制。該電荷幫浦輸出級跨 壓損失修正電路可搭配一比較器與一緩衝電路形成…指 數倍率升壓的直流轉直流電源轉換電路，具備高輸出電 壓轉換倍率’並解決了因線性升壓.而受到基體效應限制 的問題’達到η1指數倍率升壓（其中，n為每—級電路 的升壓倍率，i為總共使用到的升壓電路之總級數）。本 發明之電荷幫浦輸出級跨壓損失修正電路搭酉己ni指數倍 率升壓的直流轉直流f源轉換電路，將有效提高升壓^ =，並因電路級數少，可減少製作成本，適用於低輸入 電壓（如：一般電池）的情況下操作，可作為直流轉直 :的電壓轉換裔，以低成本的電路達到高升壓倍率的電 壓，可應用於相關晶片設計、記憶體、手持式電子產品 及驅動電路等產業。 【實施方式】 1249900 明苓閱『第1〜6圖』所示，係本發明之電荷幫浦 輸出級跨壓損失修正電路示意圖、本發明之電壓增益提 升荷幫浦輸出級跨壓損失修正電路示意圖及 之电荷幫浦輸出級跨壓損失修正電路之電壓模擬圖。如 圖所不.本發明之電荷幫浦式直流轉直流轉換器增益電 路係包含電荷幫浦輸出級跨壓損失修正電路（PG|)工， 該電荷幫浦輸出級跨壓損失修正電路（pG丨）i由一作為 PN接面之第—金屬氧化半導體（M〇s)i卫的兩端分別與 第★電今1 2及一第二電容1 3相連接，一作為二極 體^第—金屬氧化半導體14之—端與—第三金屬氧化 料體1 5之-端才目連接成一連接#，該連接端並與該 第二電容1 3及該第-金屬氧化半導體i i之相連端連 接:而該第三金屬氧化半導5之另—端與該第二金 f乳化半導體1 4之另—端連接，該第三金屬氧化半導 體1 5作為開關使用，一第四金屬氧化半導體工6之― 半導體15之閘極端與一第五金屬 減^體1 7之閘極端及-第六金屬氧化半導體工8 二：相連接’且該第六金屬氧化半導體1 8之閘極端 Γ 金屬氧化半導體1 6之祕端相連接，並與該 弟一金屬氧化半導體丄4及該第一金屬氧化半導體u 之相連端連接，該第六金屬氧化半導體1 8之另-端盘 =第一金屬氧化半導體Η之間極端相連接，而上叙 第五金屬氧化半導體⑽⑽^軸叫㈣…⑴^ 1249900 為輸出級切換開關，可在適當的時脈週期導通或關閉， 阻止輸出端的電荷倒灌回升壓電路中，同時使輸出級不 會因基體效應（b〇dy effect)而造成開關或二極體跨壓損 失變大。 在荷幫浦輸出級跨壓損失修正電路電壓模擬中， 當輸入電M (vdd)等於時脈，（dk1) 3丄等於時脈2 (clk2) 3 2等於3V時，因其輸人電㈣大，輸出升麼 速度很快，在約5μδ時，輸出電壓（v〇ut) 3 3達到理想 = 12V(如第3圖所示）。若將輸入電壓（Vdd)降為15v 日守輸出響應雖然較慢，但仍約在25ps達到理想值6V之 輸出電壓3 3 (如第4圖所示）。將所有電容充滿電荷成 為1.5V輸出電壓之穩態操作狀態下，節點c(n〇deC)2 3 =VC電塵2 3 1隨著時脈13 i被頂起，其變動週期將和 犄脈1 3 1 —致，當時脈1 3 1於高準位時，該Vc電壓2 3 1被推升至時脈1 3工之高準位（約6V)，將該vc電壓 2 3 1、、’二。玄第五金屬氧化半導體1 7輸出至輸出電壓 (Vout) 33，因該第五金屬氧化半導體丄7的閘極 (gate)端足以克服臨界電壓（thresh〇丨d ，、） 的南電壓（如第5圖之vB電壓2 2工），使該第五金屬氧 化半導體1 7完全導通’故該…電壓2 3丄接近6χ/的電 壓完全提供給輸出端（如第5圖所示）。 為了產生夠同的該第五金屬氧化半導體17之閘極 (9則電壓，在時脈2高（_)(如表工所示）時，節點 1249900 A(node A)2 1的乂4電壓2 1 1被推至高位準（略小於 7.5V)，再透過由PM〇s所接成pN二極體（pN川门⑶训 diode)之第一金屬氧化半導體1 1對節點B(n〇de B)2 2 的第電谷1 2充電，由於該第一金屬氧化半導體1 1 有導通的跨壓降（cut-in voltage約0.5V)，使得節點B 2 2的购21提升至大約踏〇.5=7吏 二電容1 3對第一電容i 2充電，將使該第二電容工3 所儲存的電荷消耗一些並儲存至該第一電容丄2，所以 泫VA電壓2 1 1會略微下降，所損失的電壓（會損失的 電荷）將在下一個半週期（clk1 high, clk2 low)時，由 電容C3補充。由於該第一金屬氧化半導體i igPMOs 所接成PN二極體，該PN二極體的導通壓降不會受到基體 效應的影響，而接近一定值，所以該VB電壓2 2 1不會 口及第一金屬氧化半導體丄丄的導通跨壓而大幅度的下 2 °當下一個半週期（dk1 h丨gh, C丨k2 |〇w)時因該第一 私谷1 2之下極板連接至時脈^ 3 1，所以該Vb電壓$ 2 1被在上推升一個時脈（c丨〇ck)約為8 5V(7+1 5 = 8 5V)， =電壓2 3 1被時脈13 “謂而要對輸出電容充 電時’該第五金屬氧化半導體丄7的間極㈨則會產 生:電壓使得該第五金屬氧化半導體丄了完全導通，當 。亥弟五金屬氧化半導體i 7之間極㈣為時脈2低（_ :勢由節點D(nodeD)24左方之第四金屬氧化半導 肢1 6的問極端連接至節點A2 i，該Va電壓2丄工位於 1249900 5·8〜5.9V之低位準，故該第四金屬氧化半導體丄6的閘 極電I約為5_8〜5.9V，而該第四金屬氧化半導體i 6的 源極（source)端為該Vc電壓2 3工接近6V，該第四金屬 氧化半導體1 6的VGS電Μ接近於0，並未大於臨界電愿 (Vth)，此時該第四金屬氧化半導體丄6關閉（〇ff)。同樣 的，如上述之時脈2低（dk2丨ow)時，該節點D2 4右方之 該第六金屬氧化半導體丄8之閘極端電壓為該Va電壓2 ▲11(5.8〜5.9V)’該第六金屬氧化半導體i 8之源極端為 4Vb電壓2 2 1 (8.5V左右）’該第六金屬氧化半導體1 8的VGS電壓可克服該臨界電壓，所以該第六金屬氧化半 導體1 8為開啟（on)的狀態，因該第六金屬氧化半導體工 8導通，將節點D2 4的VD電愿2 4 1拉至接近該Vb1 壓2 2 1的位準（8.5V)，足以克服該臨界電壓，使得該第 五孟屬氧化半導體1 7完全導通，將該vc電壓2 3 1的 6V送至輸出端。同時，該第二電容i 3在上個半週期被 消耗用於對該第-電容工2充電的電荷，將藉由〇3上的 該Vc電壓2 3 1(6V)來補充，所以該、電壓2工工會小 幅的提升，由7.5V(時脈2高）降至5.8〜5.9V(時脈2低^電 壓值提升至更接近6V (如第5圖所示）。 為了使輸出電壓3 3不會倒灌回電路，在時脈彳低， 時脈2高（clk1 low，C|k2 high)(如表1所示）時，該第六金 屬氧化半導體1 8的閘極端接至該乂八電壓（7.5V)，該第 六金屬氧化半導體1 8的源極端為該vB電壓（7V)，由於 1249900 垓閘極端之電壓比該源極端之電壓高，無法克服該臨界 電壓，所以該第六金屬氧化半導體1 8截止，而該第四 金屬氧化半導體1 6的閘極端接至該vA電壓（7.5V)，該 第四金屬氧化半導體i 6的源極端接至該7(：電壓接近 4.5V’该第四金屬氧化半導體丄6的1電壓遠大於該臨 界電壓，將使該第四金屬氧化半導體1 6導通，使得該 節點D2 4的乂〇電壓2 4 1被拉至和該節點C2 3接 近，亦即該第五金屬氧化半導體17之間極電壓接近 ).5\，所以該第五金屬氧化半導體i 7處於截止狀態， i將δ亥輸&電壓播住而不致回充至升麼電路中。如上敛 所述’該節點D2 4的VD電壓2 4 χ為該第五金屬氧化半>, simple circuit structure and no output voltage limit charge help DC converter gain circuit. Completion >;, L For the above purpose, the present invention provides a charge pump type direct weeping to DC converter gain circuit' by means of a charge pump output stage cross-voltage correction circuit (PG〇, The switching switch of the output stage can appropriately prevent the charge of the output terminal from being poured back into the boosting circuit, and at the same time, the output stage does not cause the problem that the switch or the diode crosses the pressure loss due to the body effect. The limitation of electric dust. The charge pump output stage voltage loss correction circuit can be combined with a comparator and a buffer circuit to form an index-magnification step-up DC-to-DC power conversion circuit with high output voltage conversion ratio' and solve the problem. Linear boost. The problem of being limited by the matrix effect 'reaches the η1 exponential rate boost (where n is the boost ratio of each-stage circuit, i is the total number of stages of the boost circuit used in total). The charge pump output stage cross-voltage loss correction circuit is equipped with a DC-to-DC f-source conversion circuit with a boost rate boost, which will effectively increase the boost ^ = and reduce the manufacturing cost due to the small number of circuit stages. It is suitable for operation with low input voltage (such as: general battery). It can be used as a DC-converted voltage conversion source to achieve high boost ratio voltage with low-cost circuit. It can be applied to related chip design and memory. [Embodiment] 1249900 The following is a schematic diagram of the charge pump output stage voltage loss correction circuit of the present invention, and the voltage gain of the present invention, as shown in "1st to 6th". A schematic diagram of a voltage-correction circuit for improving the load-stage voltage loss of the load pump and a voltage simulation diagram of the charge-voltage output correction circuit of the charge pump output stage. As shown in the figure, the charge pump DC-DC converter gain circuit of the present invention includes Charge pump output stage voltage loss correction circuit (PG|), the charge pump output stage voltage loss correction circuit (pG丨) i is used as a PN junction surface-metal oxide semiconductor (M〇s) The two ends of the wei are respectively connected to the first and second capacitors 1 and 2, and the other end of the second metal oxide semiconductor 14 and the second metal oxide body. Talent Connected to a connection #, the connection end is connected to the second capacitor 13 and the connection end of the first metal oxide semiconductor ii: and the other end of the third metal oxide semiconductor 5 and the second gold f emulsion semiconductor The other end of the connection, the third metal oxide semiconductor 15 is used as a switch, a fourth metal oxide semiconductor 6 - the gate of the semiconductor 15 and the gate of a fifth metal minus 1 - and - The sixth metal oxide semiconductor worker 8: the phase connection 'and the gate terminal of the sixth metal oxide semiconductor 18 is connected to the terminal end of the metal oxide semiconductor 16 and is combined with the metal-oxide semiconductor 4 and the first The connected ends of the metal oxide semiconductors u are connected, the other end of the sixth metal oxide semiconductor 18 is connected to the first metal oxide semiconductor, and the fifth metal oxide semiconductor (10) (10) is called (4) (1) ^ 1249900 is the output stage switch, which can be turned on or off at the appropriate clock cycle to prevent the charge at the output from being poured back into the boost circuit, while the output stage does not cause a switch or two due to the matrix effect (b〇dy effect). Polar body cross The pressure loss is too large. In the voltage simulation of the load-voltage loss correction circuit of the load-pump output stage, when the input power M (vdd) is equal to the clock, (dk1) 3丄 is equal to the clock 2 (clk2) 3 2 is equal to 3V, because of its input power (4) Large, the output rises very fast, at about 5μδ, the output voltage (v〇ut) 3 3 reaches ideal = 12V (as shown in Figure 3). If the input voltage (Vdd) is reduced to 15v, the output response is slower, but it still reaches the ideal 6V output voltage of 3 3 at 25ps (as shown in Figure 4). In a steady-state operating state in which all capacitors are fully charged to a 1.5V output voltage, node c(n〇deC)2 3 =VC dust 2 3 1 is jacked up with clock 13 i , and its period of change will be 1 3 1 As a result, when the pulse 1 3 1 is at the high level, the Vc voltage 2 3 1 is pushed up to the high level of the clock 13 (about 6V), and the vc voltage is 2 3 1 , 'two. The fifth metal oxide semiconductor 17 output to the output voltage (Vout) 33, because the gate terminal of the fifth metal oxide semiconductor 丄7 is sufficient to overcome the south voltage of the threshold voltage (thresh〇丨d, , ) The vB voltage of Fig. 5 is 2), so that the fifth metal oxide semiconductor 17 is completely turned on. Therefore, the voltage of the voltage 2 3 丄 close to 6 χ is completely supplied to the output terminal (as shown in Fig. 5). In order to generate the same gate of the fifth metal oxide semiconductor 17 (9 voltage, when the clock 2 is high (_) (as shown by the meter), the node 1249900 A (node A) 2 1 乂 4 voltage 2 1 1 is pushed to a high level (slightly less than 7.5V), and then passed through a first metal oxide semiconductor 1 1 pair node B (n〇) connected by p〇 diode (pN川门(3) training diode) De B) The second valley of the 2 2 is charged, since the first metal oxide semiconductor 11 has a conduction-cut voltage (cut-in voltage of about 0.5 V), so that the purchase of the node B 2 2 is raised to approximately 5.5=7吏2 capacitor 1 3 charges the first capacitor i 2, so that the charge stored by the second capacitor 3 is consumed and stored to the first capacitor 丄2, so the 泫VA voltage 2 1 1 will Slightly falling, the lost voltage (the charge that will be lost) will be supplemented by capacitor C3 during the next half cycle (clk1 high, clk2 low). Since the first metal oxide semiconductor i igPMOs is connected to the PN diode, The conduction voltage drop of the PN diode is not affected by the matrix effect, but is close to a certain value, so the VB voltage 2 2 1 does not have a mouth and the first metal oxide semiconductor 丄丄The conduction is across the pressure and the next 2 ° is the next half cycle (dk1 h丨gh, C丨k2 |〇w) because the lower plate of the first private valley is connected to the clock ^ 3 1, so The Vb voltage $ 2 1 is pushed up by a clock (c丨〇ck) of about 8 5V (7+1 5 = 8 5V), = voltage 2 3 1 by the clock 13 "say to the output capacitor When charging, the inter-electrode (nine) of the fifth metal-oxide-semiconductor ytterbium 7 generates: a voltage causes the fifth metal-oxide-semiconductor semiconductor to be fully turned on, and the pole (four) between the hexa-metal oxide semiconductors 7 is a clock 2 Low (_: potential is connected to node A2 i by the fourth metal oxide semi-limb limb 16 on the left side of node D (nodeD) 24. The Va voltage 2 is located at a low level of 1249900 5·8~5.9V. Therefore, the gate electrode I of the fourth metal oxide semiconductor device 6 is about 5_8 to 5.9V, and the source terminal of the fourth metal oxide semiconductor device 6 is the Vc voltage of 2 3, which is close to 6V. The VGS electric enthalpy of the tetrametal oxide semiconductor 16 is close to 0, and is not greater than the critical electric power (Vth), at which time the fourth metal oxide semiconductor 丄6 is turned off (〇ff). Similarly, the clock 2 is low as described above. (dk2丨ow), the gate terminal voltage of the sixth metal oxide semiconductor 丄8 on the right side of the node D2 4 is the Va voltage 2 ▲11 (5.8~5.9V). The source terminal of the sixth metal oxide semiconductor i 8 is 4Vb voltage 2 2 1 (about 8.5V) 'The VGS voltage of the sixth metal oxide semiconductor 18 can overcome the threshold voltage, so the sixth metal oxide semiconductor 18 is in an on state due to the sixth metal The oxidized semiconductor device 8 is turned on, and the VD power of the node D2 4 is pulled to a level close to the Vb1 voltage 2 2 1 (8.5 V), which is sufficient to overcome the threshold voltage, so that the fifth sulphur oxide semiconductor 17 Fully conductive, the 6V of the vc voltage 2 3 1 is sent to the output. At the same time, the charge that the second capacitor i 3 is consumed for charging the first capacitor 2 in the last half cycle is supplemented by the Vc voltage 2 3 1 (6V) on the 〇3, so The voltage 2 trade union increased slightly, from 7.5V (clock 2 high) to 5.8~5.9V (clock 2 low ^ voltage value increased to closer to 6V (as shown in Figure 5). In order to make the output voltage 3 3 does not back into the circuit, when the clock is low, clock 2 is high (clk1 low, C|k2 high) (as shown in Table 1), the gate terminal of the sixth metal oxide semiconductor 18 is connected to the gate Eight voltage (7.5V), the source terminal of the sixth metal oxide semiconductor 18 is the vB voltage (7V), and since the voltage of the 1249900 gate terminal is higher than the voltage of the source terminal, the threshold voltage cannot be overcome, so the first The hexa-metal oxide semiconductor 18 is turned off, and the gate terminal of the fourth metal oxide semiconductor 16 is connected to the vA voltage (7.5 V), and the source terminal of the fourth metal oxide semiconductor i 6 is connected to the 7 (: voltage is close to 4.5) V' the voltage of the fourth metal oxide semiconductor 丄6 is much larger than the threshold voltage, which will turn on the fourth metal oxide semiconductor 16 The 乂〇 voltage 2 4 1 of the node D2 4 is pulled close to the node C2 3, that is, the pole voltage between the fifth metal oxide semiconductor 17 is close to .5\, so the fifth metal oxide semiconductor i 7 is at In the off state, i will broadcast the δ 输 & voltage without charging back into the circuit. As mentioned above, the VD voltage of the node D2 4 is 4 χ, which is the fifth metal oxidized half.
戈口園所示：係本發明之電荷幫 電路係可與一^卜壶m它哭菸_ & %吩不思圖。如圖所示 浦輸出級跨_失修正電路係可盘According to Gekouyuan: the charge-assisted circuit of the present invention can be combined with a pot of tea, and it cries smoke _ & %. As shown in the figure, the output stage of the sub-slide correction circuit is available.
路，先將小倍率的第一級兩倍電荷 1249900 =電路2 5提升電壓，再透過該比較器與該緩衝器， =提升時脈的電壓大小’使第二級兩倍電荷幫浦電路 私山不再使用小&壓來做幫浦時脈（pumping c|〇ck)，將 ‘出電：：：阿：降低開關的電荷消耗’可最快的將 舟A 至所需要的倍率，而由於該時脈的電壓同 二，可克服因臨界電壓所造成輸出電壓限制的問 =即使在小的輸人電壓（Vdd=15V, ciM=dk2=i 5v) 第—級兩倍電荷幫浦電路2 5之2倍輸出電 2 6二^4^3'提升至該第二級兩倍電荷幫浦電路 剧電壓（V〇ut) 3 5接近6V(如第8圖所示）。由 二級兩倍電荷幫浦電路25為兩倍 4 2接賴，並將^別)提升至輸出時脈之電壓3 器料緩之電壓3 4 2連接該比較 為作為該第二級兩倍電荷幫浦 源，將該輸入時脈9 “ 电纷匕〇之冤 1 3 4 1 π ^ 拉至該比較器，使該輸入時脈 接近1畝山 ）’該輸入時脈，13 4 4之輸出電壓值 接近錢出時脈之雙 值 1 3 4 4與該銓山。士 丹將忒輸入吩脈 電荷幫浦電路；6:::4 2运至該第二級兩倍 本J 出電壓3 4 3 (6V)(如第9圖所示)。 利用電；幫浦式直流轉直流轉換器增益電路係 别級跨壓損失修正電路搭配指數升壓架 1249900 構串接或改變兩倍電荷幫浦電路來提升電壓的倍率，請 芩閱『第1 〇圖』所示，係本發明之2χ2χ2升壓電荷幫浦 電路示意圖。如圖所示：係以三組兩倍電荷幫浦電路申 接成η1指數倍率升壓電荷幫浦電路，當第一級兩倍電荷幫 浦電路2 5輸入電壓和時脈1、時脈2皆為15V ( 一顆電 池的電壓），透過比較器與緩衝電路，產生時脈，1和時 脈’ 2’該時脈’】之電壓也將接近3V，再將該時脈，I 之電壓（3V)與該時脈，】作為第二級兩倍電荷幫浦電路 2 6的輸入’即可產生另一個兩倍電壓輸出，第二級兩 倍電荷幫浦電路2 6之輸出電壓接近6V，再作為另一個 比較器和緩衝器的電源電壓，產生另一組時脈，，1和時 脈2 ’該時脈’’ 1之電壓大小也將趨近第二級兩倍 電荷幫浦電路2 6之輸出電壓的6V，再將該時脈，，】 之電壓（6V)與該時脈’’ 1當作第三級兩倍電荷幫浦電 路2 7的輸入，輸出又提升兩倍至接近12V，將輸出電壓 放大8倍（12/1.5=8)，亦即2χ2χ2=23,得到…（门的丨次 2的升壓倍率（如：2、32.........)，將使本發明之 電何幫浦式直流轉直流轉換器增益電路之整體 :、结構簡化’具有電路級數少，可減少製作成本，可適 用於低輸入電壓的情況下操作（如：只有— =攜帶式電子設備，大幅縮減電池所造成的面:浪 的電數倍率升壓等優點，並可作為直流轉直流 14 Ϊ249900 增益發明之電荷幫浦式直流轉直流轉換器 =路’以_電路結構」作為主要策略，可有效 種種缺點，使其具有電路級數少即可達到所 輸出電餘制、適料低輸人操作 ，點’進而使本發明之産生能更進步、更實用、更符 、i=r所需，確已符合新型專利中請之要件，妥依 叫出專利申請，尚請㈣查判㈣細審，並盼早 曰准予專利以勵創作，實感德便。 准以上所述者，僅為本發明之較佳實施例而已，當 不能以此限定本發明實施之範圍；故，凡依本發明申請 專利範圍及發明說明書⑽所作之簡單料效變化與修 飾，皆應仍屬本發明專利涵蓋之範圍内。 1249900 【圖式簡單說明】 第1圖’係本發明之電荷幫浦輸出 示意圖。 “貝失修正電路 級跨 第 ^貝失修正電路示意圖。 6圖’係本發明之電荷幫浦輸出級跨 電路之電壓模擬圖。 、失t正 第7 A〜7 B圖，係本發明之2χ2 意圖。 以電何寶浦電路示 壓 弟8〜9 ®，係本發明之2χ2升壓 模擬圖。 了^電路之電 第1 0圖，係本發明之2χ2χ2升 圖 电何幫浦電路示意 電路的 表1，係本發明之電荷幫浦輸出級跨壓損失修正 節點電壓及時脈表。 、> 【主要元件符號說明】 Φ 電荷幫浦輸出級跨壓損失修正電路工 第一金屬氧化半導體 11 第一電容 12 第二電容13 第二金屬氧化半導體 14 第三金屬氧化半導體 15 第四金屬氧化半導體 16 16 1249900 第五金屬氧化半導體 17 第六金屬氧化半導體 18 節點A 2 1 VA電壓2 11 節點B 2 2 VB電壓2 2 1 節點C 2 3Road, first the small level of the first stage double charge 1249900 = circuit 2 5 boost the voltage, and then pass the comparator with the buffer, = boost the clock voltage size 'to make the second level double charge pump circuit private The mountain no longer uses the small & press to do the pumping pulse (pumping c|〇ck), the 'power out::: A: reduce the charge consumption of the switch' can quickly get the boat A to the required magnification, Since the voltage of the clock is the same as the second, the output voltage limitation due to the threshold voltage can be overcome. = Even at a small input voltage (Vdd=15V, ciM=dk2=i 5v) Circuit 2 5 times the output power 2 6 2^4^3' is raised to the second level twice the charge pump circuit voltage (V〇ut) 3 5 is close to 6V (as shown in Figure 8). By the secondary double charge pump circuit 25 is doubled 4 2 and will be boosted to the output clock voltage 3 the material is slowed down the voltage 3 4 2 connected the comparison as twice the second stage The charge pump source, the input clock 9 "Electrical 冤 1 3 4 1 π ^ is pulled to the comparator, so that the input clock is close to 1 mu of mountain" 'The input clock, 13 4 4 The output voltage value is close to the double value of the money out clock 1 3 4 4 and the Lushan. Shidan will input the 吩 pulse charge pump circuit; 6:::4 2 will be transported to the second stage twice the J output voltage 3 4 3 (6V) (as shown in Figure 9). Use electricity; pump-type DC-to-DC converter gain circuit is a step-by-step voltage loss correction circuit with an exponential booster frame 1249900 to connect or change twice the charge The pump circuit is used to increase the voltage multiplier. Please refer to the “Figure 1” diagram, which is a schematic diagram of the 2χ2χ2 boost charge pump circuit of the present invention. As shown in the figure, it is implemented by three sets of double charge pump circuits. Connected to η1 exponentially rate boosted charge pump circuit, when the first stage doubles the charge pump circuit 2 5 input voltage and clock 1 and clock 2 are both 15V (one The voltage of the cell), through the comparator and the buffer circuit, generates the clock, and the voltage of 1 and clock '2' the clock' will also be close to 3V, and then the clock, the voltage of I (3V) and the time Pulse, as the input of the second stage double charge pump circuit 2 6 can generate another double voltage output, the output voltage of the second stage double charge pump circuit 6 6 is close to 6V, and then as another comparison And the supply voltage of the buffer, generating another set of clocks, 1 and clock 2 'the clock'' 1 voltage magnitude will also approach the second stage twice the charge pump circuit 2 6 output voltage 6V, then the voltage (6V) of the clock, and the clock ''1 is regarded as the input of the third-stage double charge pump circuit 27, and the output is doubled to nearly 12V, and the output voltage is Enlarge 8 times (12/1.5=8), that is, 2χ2χ2=23, to get... (the step-up magnification of the gate 2 (eg, 2, 32.........), will make the present invention The power of the Hepu-type DC-to-DC converter gain circuit is as follows: The structure is simplified. 'There are fewer circuit stages, which can reduce the production cost and can be applied to low input voltage. In the case of operation (such as: only - = portable electronic equipment, greatly reducing the surface caused by the battery: the power of the wave multiplier boost, and can be used as a DC to DC 14 Ϊ 249900 gain invention charge pump DC transfer DC converter = road 'with _ circuit structure' as the main strategy, can effectively all kinds of shortcomings, so that it has a small number of circuit stages to achieve the output of the remaining power system, suitable for low input operation, and then 'the invention' Produce more progressive, more practical, more consistent, i=r needs, has indeed met the requirements of the new patent, and is called to apply for a patent, but also (4) to investigate (4) to review, and hope to grant patents as early as possible. Reinforced creation, real sense of virtue. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; therefore, the simple effect changes and modifications made by the scope of the present application and the specification (10) of the present invention, All should remain within the scope of the invention patent. 1249900 [Simplified description of the drawings] Fig. 1 is a schematic diagram of the charge pump output of the present invention. "Beibei correction circuit level cross-section correction circuit diagram. 6" is the voltage simulation diagram of the charge pump output stage of the present invention. The loss of the positive 7A~7 B diagram is the invention 2χ2 Intent. The electric He Baopu circuit shows the pressure of the brother 8~9 ® , which is the 2χ2 boost simulation diagram of the present invention. The electric circuit of the circuit is shown in Figure 10, which is the 2χ2χ2 liter diagram of the present invention. According to the present invention, the charge pump output stage voltage-crossing loss correction node voltage and time pulse table., > [main component symbol description] Φ charge pump output stage voltage loss correction circuitman first metal oxide semiconductor 11 first capacitor 12 second capacitor 13 second metal oxide semiconductor 14 third metal oxide semiconductor 15 fourth metal oxide semiconductor 16 16 1249900 fifth metal oxide semiconductor 17 sixth metal oxide semiconductor 18 node A 2 1 VA voltage 2 11 node B 2 2 VB Voltage 2 2 1 node C 2 3
Vc電壓2 3 1 節點D 2 4 VD電壓2 4 1 第一級兩倍電荷幫浦電路 25 第二級兩倍電荷幫浦電路 26 第三級兩倍電荷幫浦電路 27 時脈1 3 1 時脈2 3 2 輸出電壓3 3 第一級兩倍電荷幫浦電路之2倍輸出電壓3 4 輸入時脈1 3 4 1 輸出時脈之電壓342 第二級輸出電壓343 輸入時脈’ 1 3 4 4 第二級兩倍電荷幫浦電路之2倍輸出電壓3 5 17 1249900 < < >< ti.rjt S (Φ| m ♦ m 4H* η 扛 αι η _ r~^ Ο tt G) 胬 K) 〇 < k1 ) low iA ro 0 $ m 4W m 4W 捧 _ 箅 η η 00 n ^l ro ，—>、 σ> < ΟΊ < O X cn < v ) 7\ |S〇 IT CQ 3- '—〆 IT CQ ΖΓVc voltage 2 3 1 node D 2 4 VD voltage 2 4 1 first stage double charge pump circuit 25 second stage double charge pump circuit 26 third stage double charge pump circuit 27 clock 1 3 1 Pulse 2 3 2 Output voltage 3 3 Level 2 double charge pump circuit 2 times output voltage 3 4 Input clock 1 3 4 1 Output clock voltage 342 Second stage output voltage 343 Input clock ' 1 3 4 4 2 times the output voltage of the double-stage charge pump circuit of the second stage 3 5 17 1249900 <<>< ti.rjt S (Φ| m ♦ m 4H* η 扛αι η _ r~^ Ο tt G胬K) 〇< k1 ) low iA ro 0 $ m 4W m 4W holding _ 箅η η 00 n ^l ro , —>, σ>< ΟΊ < OX cn < v ) 7\ |S 〇IT CQ 3- '-〆IT CQ ΖΓ