TWI248162B - Trench semiconductor device and method of forming the same - Google Patents

Abstract

A trench semiconductor device and a method of forming the same are provided. The method includes providing a substrate with a mask structure thereon. A trench is formed in the mask structure and the substrate and exposes sidewall of the mask structure. A capacitor is formed in the trench of the substrate. The capacitor has an upper surface substantially exposing the sidewall of the mask structure. A collar dielectric layer is formed on the sidewall of the mask structure and exposes a portion of the upper surface of the capacitor. A conductive plug is formed in the trench electrically coupling with the capacitor. The mask structure is removed to expose the substrate with the collar dielectric layer and the conductive plug thereon. An epitaxial layer is grown on the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a trench capacitor and a method of fabricating the same. Second, [prior technology]

In "f semiconductor devices or memory devices, capacitors are often used as charge storage. Many memory components, such as dynamic random access memory (DRAM), use bit data for private use. The f-mode is stored in the capacitor structure. As the memory component accumulates two liters, the valley structure must also be reduced. However, the size of the capacitor structure is usually defined by the resolution of the process technology, but at the same time the memory must be maintained. The minimum memory capacity required for the body components. The consideration of the two: Some people have proposed the idea of a trench capacitor. By providing a longitudinal ruler, the surface area is increased to increase the power. In the valley, the volume is reduced and the capacity is still maintained. However, as the accumulation of memory components continues to increase, it is limited by the technical limit of the etched trench depth, and it is impossible to extend the tears downward without limit.

j. So - come to make it generally 70/9. In the nm process, τ: the depth of the ditch below 仟10//m, sometimes even 1 is J in the king /, there is b β Π1. Same as ith, the use of the etchback, such as photoresist recession, multiple etchback process to define the Tiansi Ting Shen X X dao. The arrogance of the wide valley, the ring neck part and the rear position of the buried W, so that The actual length of the trench is only about 6/zm, or the storage capacity of the drain capacitor has a length that is perpendicular to the side of the substrate, and the effective length of the wall is

1248162 V. INSTRUCTIONS (2) The method achieves sufficient capacitance. That is to say, the etching technique is used to increase the etching depth of the trench, and the capacitance requirement required for the device to be reduced can not be effectively achieved. Accordingly, it is an important issue in semiconductor manufacturing to provide a trench type semiconductor device and a method of fabricating the same that can fully utilize the depth of the trench in the substrate to effectively enhance the efficiency of the trench type semiconductor device. <III. SUMMARY OF THE INVENTION One aspect of the present invention provides a method of forming a trench type semiconductor device that effectively overcomes the depth limitation of the etching trench process to control the performance of the trench type semiconductor device. In one embodiment, the method provided by the present invention, for example, forms a trench capacitor having a surface. Forming a mask A trench is formed in the mask structure and the substrate. wall. Then, a side surface of the substrate which substantially exposes the mask structure is formed to be coplanar with the surface of the substrate. A sidewall is formed and the ring-neck dielectric layer exposes the capacitive conductor to the trench and the conductor plug structure exposes the substrate and the elongated epitaxial layer on the substrate. A trench-type semiconductor device is formed. The method of the present invention comprises providing a substrate structure on a surface of a substrate. The trench is formed in a trench in one side of the exposed mask structure, and the capacitor has a wall: preferably, a portion of the upper surface of the capacitor is a portion of the upper surface of the mask structure. Form one: electrically connected to the electric valley. Remove the mask neck dielectric layer and conductor plug. to make

1248162 V. Description of the invention (3) ^ The step of forming a capacitor comprises forming a first electrode of the capacitor in the trench by gas phase doping; forming a capacitor dielectric layer on the first electrode; and filling the substrate with a conductor material The trench in the material is formed to form one of the capacitors on the second electrode = the capacitor dielectric layer. In addition, prior to forming the first electrode of the capacitor, the step of including the trench in the bottle-shaped substrate is such that the bottle-shaped trench has a width greater than a width of the trench of the mask structure. Furthermore, before the step of removing the mask structure and growing the epitaxial layer, a nitride layer is formed to be exposed.

‘body embolism. The method of the present invention further includes the step of forming a transistor device in the epitaxial layer to complete a memory cell. Another aspect of the present invention is to provide a trench type semiconductor device, such as a trench capacitor, which contributes all the trench depth of the substrate to the device to increase the capacitance of the capacitor in the substrate while utilizing the epitaxial layer on the substrate. The layer serves as a device layer for fabricating a cluster such as a transistor. In another embodiment, the present invention provides a trench type semiconductor device comprising a substrate having a surface; a capacitor formed in the substrate, and the capacitor has An upper surface is coplanar with the surface of the substrate; a conductor plug is formed on the substrate, and the conductor plug is electrically connected to the capacitor; a ring neck dielectric layer is formed on the substrate and surrounds the conductor plug; A seed layer is formed on the substrate and surrounds the ring-neck dielectric layer. In addition, the trench type semiconductor device further includes a nitride layer

4NTC04007TW.ptd Page 9 1248162 V. INSTRUCTION DESCRIPTION (4) The body plug includes a first electrode, and a dielectric layer is formed between the first and the first crystal device. The capacitor has a first electrode and a capacitor dielectric layer, and a capacitor between the two electrodes. 4. [Embodiment] The present invention provides a trench type semiconductor device and a method of fabricating the same, wherein the depth of the trench is all contributed to the trench capacitor, and is grown on the substrate for fabrication of a device such as a transistor. Device layer. In this way, the depth limit of the etching trench process can be effectively overcome, & Figure! 7 is a preferred embodiment of the present invention:

Schematic diagram. J Main Tomb Ϊ Figure 1 'In one embodiment' The present invention provides a method of forming a trench-clothing. In this embodiment, the trench type semiconductor device can be a trench capacitor. The method of the present invention comprises providing a substrate having a surface 101. The substrate can be any suitable semiconductor substrate or a conventional twin circle. A mask structure 110 is then formed on the surface 101 of the substrate 100. The step of masking the structure 110 comprises forming a mask structure by using a material selected from the group consisting of oxides, nitrides, polycrystals, and combinations thereof. For example, the mask structure 110 may be a multi-layer iUi in which a combination of a tantalum oxide layer ι 2, a pad layer 104, a boron-containing oxide layer 106, or a polysilicon layer 1〇8 is selected. Note that the mask structure 110 can be arranged. The design of the process or the depth of the ditch can be varied to achieve the desired pattern for the material. Bamboo 1

1248162 V. Description of invention (5)

Then, as shown in Fig. 2, a trench 2 is formed in the mask structure 11 () and the base f 1 , and the trench exposes one side of the mask structure 丨 1 (). The method of forming the trenches 120 includes the use of conventional lithography, etching, and the like. For example, a photoresist layer is coated on the mask structure 丨丨Q, and the photoresist layer is patterned by a pattern transfer technique such as exposure development to define a trench. Thereafter, the mask structure and the substrate are etched by using the pattern = photoresist layer as a mask. It should be noted here that when transferring the trench pattern to the mask structure 11() and the substrate structure, the photoresist or mask structure 110 may be removed or degraded at the same time or removed in subsequent design processes. For example, in this embodiment, when the mask structure 110 and the substrate 100 are etched to form the trench 120, the polysilicon layer 108 in the mask structure 11 can be removed together. Then, the trench 12 in the substrate 1 is selectively bottled so that the bottle-shaped trench 130 has a width wider than that of the trench 12 of the mask structure 11 as shown in FIG. 2A. The step of squeezing the substrate 12 into the trench 12 includes the substrate 100 00 to form an oxide layer in the trench α 2 亦, that is, the current % 瘵 gas generation technology (ISSG), Oxidation is exposed to the sidewall of the substrate of the trench such that the sidewall portion of the substrate becomes the oxide layer 125. Then, the oxide layer 125 is removed to form the bottle-shaped trench 13 in the substrate 1〇〇. When the ISSG technology is used to form the bottled trench 13 , attention must be paid to the control of the etching parameters, because it is also possible to remove part of the pad oxide layer 102 when removing the oxide layer 125, thereby causing undercutting. In addition, the bottled substrate Step 1 of the trench in 1〇〇, optionally etch the substrate with ammonium hydroxide (ΝΗ4〇Η) solution

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100 is performed to obtain a bottled ditch i 30. Further, part of the mask structure 110' may be removed if it contains the ruined oxide layer 1〇6. It should be noted here that the thickness of the mask structure 11 留 can be determined according to the design requirements of subsequent processes. As a result, as shown in FIG. 3, the width of the bottle-shaped trench Uq in the substrate 1 is larger than the width of the trench 12 in the mask structure 110, so that the subsequently fabricated capacitor has a larger capacitance. . For ease of explanation, the following examples are illustrative of the process of making a bottled trench.

Next, as shown in FIG. 4, a capacitor 14 is formed in the trench 130 in the substrate 1 and the capacitor 14 has an upper surface 14i substantially exposing the sidewall 111 of the mask structure 110. Preferably, the upper surface 141 of the capacitor is substantially coplanar with the surface 101 of the substrate 100. The step of forming the capacitor 140 includes forming a first electrode 14 4 of the capacitor 1 4 in the trench 1 3 以 by gas phase doping. For example, arsenic is doped into the sidewall of the substrate 100 exposed to the trench 130 by gas phase doping to form the first electrode 142 of the capacitor 14 。. Then, a capacitor dielectric layer 14 is formed on the first electrode 142. The capacitor dielectric layer 148 can be an oxide layer, a nitride layer, or a combination thereof. Thereafter, the trench 130 in the substrate 100 is filled with a conductor material to form a second electrode 146 of the capacitor 140 on the valley dielectric layer 144. The step of forming the second electrode 146 of the capacitor 140 encloses a polysilicon layer in the trench (1 2 〇 and 130), and etch back the polycrystalline layer to a depth such that the polysilicon layer substantially exposes the mask structure. i 侧壁 sidewall 111. In other words, the polysilicon layer is deposited entirely on the mask structure 110 and the trenches are filled (portions 120 and 130). Then, the polycrystalline germanium layer is etched back, preferably such that the remaining polycrystalline germanium layer substantially fills the base

4NTC04007TW.ptd Page 12 1248162

The trench 130 in the material 100, the polycrystalline layer (the surface 141. ' serves as the second electrode 146 of the capacitor 14 4 。. The upper surface of the second electrode) is also the upper surface of the capacitor 14 〇

= As shown in Fig. 5, a ring-neck dielectric layer is formed (c〇Uar core "" 忖 rri is on the side wall U1 of the mask structure 110, and the ring-neck dielectric layer 15 is violently traversing the surface 1 1 1 A portion of the step of forming the ring-neck dielectric layer 150 includes forming a conformal oxide layer on the mask structure 11 然后. Then, a non-detailed conformal oxide layer is formed. The thickness ratio of the dielectric layer 1 5 〇 to the pad oxide layer 1 0 2 is 〇··丨. Therefore, in the subsequent step, the pad oxide layer 10 2 牯 ' can still retain sufficient ring-neck dielectric layer 丨 5 〇 Thereafter, a conductor plug 160 is formed in the trench 12 2 , and the conductor plug 16 电 is electrically connected to the capacitor 14Q. The step of forming the conductor plug 60 includes depositing a polysilicon layer on the mask structure 110 and filling the trench 1 2 〇 planarizing the polysilicon layer to expose the mask structure 110. In other words, the ring neck dielectric layer 150 and the conductor plug 16 6 can be formed on the substrate 100 by processes such as deposition, etching, chemical mechanical polishing, and the like. Above, the depth of the trench in the substrate 1 完全 completely contributes to the capacitor 1 400, which can effectively increase the capacitance. As shown in FIG. 6, the mask structure 丨10 is removed to expose the substrate 1 〇〇 and the ring-neck dielectric layer 15 〇 and the conductor plug 1 60 on the substrate 100. In addition, the mask structure is removed. After 110, a nitride layer 170 is selectively formed on the exposed conductor plug 160 for use as a protective conductor plug 160. For example, a polysilicon layer as a conductor plug 160 is nitrided by a nitridation process. To form nitriding

4NTC04007TW.ptd Page 13 1248162

Layer 1 70 is at a portion of conductor plug 160 that is not surrounded by ring-neck dielectric layer 150. Then, grow an epitaxial layer of 18 〇, such as an epitaxial layer, on the substrate , ,, as shown in Figure 7 / kg. In addition, the method of the present invention further comprises forming a transistor device in the layer 1 to 80 to complete a memory cell. The transistor device can be completed by conventional microlithography, etching, doping, deposition, etc., and will not be described herein.

Referring to FIG. 7, in another embodiment, the present invention provides a trench type half body suit 10, such as a trench capacitor. The trench capacitor IS substrate 100 of this embodiment has a surface 101. Substrate 100 can be a semiconductor substrate such as a conventional germanium wafer. A capacitor 140 is formed in the substrate 1 〇 , and the capacitor 140 has an upper surface 141 which is substantially coplanar with the surface 1 〇 1 of the substrate 1 〇 0. For example, the capacitor 14A includes a first electrode 142, a second electrode 146, and a capacitor dielectric layer 144, and the capacitor dielectric layer 144 is interposed between the first and second electrodes. A conductor plug 16 is formed on the substrate 1 and the conductor stub 160 is electrically connected to the valley 140. A ring-neck dielectric layer 15 is formed on the substrate 1 and surrounds the conductor plug (10). A stray layer 18 〇, such as a cryptite layer, is formed on the substrate 100 and surrounds the ring-neck dielectric layer 15 〇. It should be noted here that '"substantially coplanarity" means that the upper surface 141 of the capacitor "0 is almost equal to the surface of the substrate 100, and is equal to the surface of the substrate 10, but if the plane of the upper surface 丨4丨 is larger than the surface of the substrate 1 (four) 101 It is still a high one @ ' does not affect the implementation of the present invention. In addition, if the upper surface 141 is lower than the surface 〇1 of the substrate 100, in comparison, it is impossible to completely use all the trenches 13 under the substrate 100 as the portion of the capacitor to store electric charge, and it is difficult to form a good shape. The ring neck dielectric layer 150.

1248162

V. INSTRUCTION DESCRIPTION (9) The trench type semiconductor conductor plug 160 of the present invention. Furthermore, the sarcophagus device further comprises a layer of nitride layer on the device layer, and the ^$#|"0 layer 18 〇 can be subsequently fabricated, such as a transistor layer, into a memory cell having a trench capacitor. In the present invention, the ditch-type capacitors provided by the present invention are arranged such as a trench type semiconductor. This is effective; the conductor plug is formed on the substrate as a part of the capacitor for storing electric charge, and the depth of the ditch is, in order to make the bottle-shaped process more suitable:: electric valley efficiency. In addition, the present invention only requires a capacitor in the length, and more so as the effective channel size of the capacitor is not required. At the same time, U 2 2 helps to meet the component reduction process, and as a service layer such as electricity a ^ ^, it can be used with the device layer of the subsequent device for charging the solar device. The present invention is not limited to the above modifications and variations of the present invention. The present invention is intended to include a description of the only examples of the invention, and the scope of the application of the invention is intended to be the scope of the invention. Modifications and changes to be truly in accordance with the essence of the invention

1248162

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a vertical surface of a substrate having a mask structure according to an embodiment of the present invention; FIG. 2 is an embodiment of the present invention showing that a trench is formed in a mask. 2 is a schematic cross-sectional view showing a trench step in a bottled substrate; v ** FIG. 3 is an embodiment of the present invention showing a bottle inside a substrate Figure 4 is a schematic cross-sectional view showing a capacitor formed in a substrate according to an embodiment of the present invention; Figure 5 is a consistent embodiment of the present invention showing a ring-neck dielectric layer and a conductor plug on a substrate Schematic diagram of the cross section; Fig. 6 彳 发 & 明 明 隹 隹 隹 隹 隹 隹 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Cross-sectional schematic diagram of the trench capacitors symbolic description 10 0 substrate 102 pad oxide layer 10 6 boron oxide layer 110 mask structure 120 trench 101 substrate surface 104 pad nitride layer 108 polysilicon layer 111 Shield structure sidewall 125 oxide layer

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Brief description of the model 130 bottled trench 140 capacitor 141 capacitor upper surface 142 first electrode 144 capacitor dielectric layer 146 second electrode 150 ring neck dielectric layer 160 conductor plug 170 nitride layer 180 stupid layer page 17 4NTC04007TW. Ptd

Claims (1)

1248162 Patent application scope 1 1. A method for forming a trench type semiconductor device, comprising: providing a substrate having a surface; forming a mask structure on a surface of the substrate; forming a trench in the mask In the cover structure and the substrate, the trench exposes a sidewall of the mask structure; ^ forming a capacitance in the trench in the substrate, and the capacitor has an upper surface substantially exposing the sidewall of the mask structure; Forming a ring-neck dielectric layer on the sidewall of the mask structure, and the ring-neck dielectric layer exposes a portion of the upper surface of the capacitor; forming a conductor plug in the trench, and the conductor plug and the capacitor are electrically Connecting the mask structure to expose the substrate and the ring-neck dielectric layer and the conductor plug on the substrate; and growing an epitaxial layer on the substrate. 2. The method of claim 1, wherein the step of forming the mask structure comprises forming the mask structure with a material selected from the group consisting of oxides, nitrides, stone-containing oxides, polysilicones, and combinations thereof. . 3. The method of claim 1, wherein the surface above the capacitor is substantially coplanar with the surface of the substrate. 4 · If the method of claim 1 is applied, the steps for forming the electricity valley include: 1248162 _ 6. The patent application scope is in a gas phase doping manner, forming a first electrode of the capacitor in the trench; forming a capacitor dielectric layer on the first electrode; and filling the substrate with a conductive material The trench is formed to form a second electrode of the capacitor on the capacitor dielectric layer. 5. The method of claim 4, wherein the step of forming the second electrode of the capacitor comprises: filling a polysilicon layer in the trench; and etching back the polysilicon layer to substantially expose the polysilicon layer The side wall of the mask structure. 6. The method of claim 1, wherein the step of forming the capacitor further comprises the step of bottle-forming the trench in the substrate such that the bottled trench has a width greater than the mask structure. The width of the trench. 7. The method of claim 6, wherein the step of bottle sizing the δ 沟 trench in the substrate comprises etching the substrate with a gas oxidizing solution. 8. The method of claim 6, wherein the step of bottle forming the trench in the substrate comprises: oxidizing the substrate to form an oxide layer in the trench by on-site vapor generation techniques And removing the oxide layer. The method of claim 1, wherein the step of forming the ring-neck dielectric layer comprises: forming a conformal oxide layer on the mask structure; And anisotropically etching the conformal oxide layer. The method of claim 1, wherein the step of forming the conductor plug comprises: depositing a polysilicon layer on the mask structure and filling the trench; and planarizing the polysilicon layer to expose the Mask structure. 11. The method of claim 1, wherein the step of removing the mask structure and growing the epitaxial layer further comprises forming a nitride layer on the exposed conductor plug 1 . The method of claim 11, wherein the step of forming the nitride layer comprises nitriding the exposed conductor plug. 1 3. The method of claim 1, further comprising the step of forming an electromorph device in the epitaxial layer to complete a memory cell. 14. A trench type semiconductor device comprising: a substrate having a surface; 4NTC04007TW.ptd Page 20 1248162 6. Patent Application A capacitor is formed in the substrate, and the capacitor has an upper surface substantially coplanar with the surface of the substrate; a conductor plug is formed on the substrate, and The conductor plug is electrically connected to the capacitor; a ring neck dielectric layer is formed on the substrate and surrounds the conductor plug; and a stray layer is formed on the substrate and surrounds the ring neck dielectric layer. 1. The trench-type semiconductor device of claim 14, further comprising a nitride layer on the conductor plug. 16. The trench-type semiconductor device of claim 14, further comprising a transistor device formed on the epitaxial layer. The trench-type semiconductor device of claim 14, wherein the capacitor comprises a first electrode, a second electrode, and a capacitor dielectric layer interposed between the first and second electrodes. 4NTC04007TW.ptd Page 21