TWI246141B - Wafer package and test method - Google Patents

Abstract

A wafer package and test method is provided. The procedures include: (A) Package: fix plural diced chips on an un-split lead frame and then execute the wire bonding and package glue covering steps to make plural transistors connecting each other. (B) Pre-cut: remove the conduction part or redundant portion of the lead frame to let the transistor able to be inspected without individual split. (C) Test: send all un-split transistors to the inspection equipment to execute testing and inspection and find defect transistors. (D) Generation of test file: automatically (by inspection equipment) or manually record the quality and performance of each transistor. (E) Mark: mark product codes, brand and production site on the said package body surface. (F) Cut: use cutter to split the lead frame to let the transistors be individual state. Pick the defect or poor quality finished goods to achieve increasing of QC rate, cost down and gain of in time adjustment of the package equipment to reduce the defect rate.

Description

1246141 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a wafer sealing wafer packaging completed crystal inspection [prior art] Wafer packaging can be easily implemented after wiring and sealing according to the conventional It can be seen that the test is ready for use, and its cost is good in the case of good sealing colloid of the crystal. Secondly, after the cutting and cutting of the truss frame, the transistor has been scattered into the product drawn by manual operation; otherwise, it is bound to detect the rate of the above-mentioned conventional pumping, which can only find that the actual measurement has not been effectively sealed. In the case of unpredictable creation of wafer packaging adhesives, printing transistors or the surface of the transistor, due to the elimination of known testing (ie, cutting of single-shaped particles), this kind of testing should be performed. If you want to take a lot of time to improve and sample testing In the case of the equipment installed before the batch of transistor, in view of the above process, the product of cutting a single micro-processor is like the procedure of the transistor inspection, so it is very important that every transistor is held in quality control. Only a few electric molds of the finished product or the production and testing method are equipped with sequential systems and detectors, but the finished product is sent after quality inspection and testing. It is difficult for all electricians. The method of reducing the wafer sealing process with multiple defects in the dispersion process is especially related to the measurement, and it can comprehensively test all electric meters. Including the main cause, the existing will make the connection crystal It is not easy to detect and put it into practice. The few defects that are often researched and released are the defects that have to be removed in the process of product inspection and inspection. The defects have been pre-determined; the transistors on the product printing process have checked the truth, because their work is unfavorable. Crystal problems, flaws correction, cutting and cutting, by knowing the seal or the character sequence of the display test, it is already working. In addition, the extraction is not. Therefore, this system is manufactured by using OR or welding. The wires can only be scattered due to defects.

Page 5 1246141 V. Description of the invention (2) Various issues and research methods. [Summary of the invention The present invention only refers to the implementation of self-cost, and can statistically test the packaging equipment into the guide assembly procedure described below with the following steps, using the conductive part of the rack and can be sent to the detection device D) The quality of the test body, the shape number, the product line frame are cut open, the quality is not good, and it can be timely. [The implementation is insufficient, but it is anxious to improve and innovate. After years of hard work, it has finally successfully developed the wafer package of the present invention. The main purpose of the tester is to provide a wafer packaging test method. After the wafer packaging is completed, the inspection operation program is designed to mobilize the inspection operation to increase the quality control rate and reduce the quality control of all transistors. Inspection to capture, store and material, and then obtain the effect of the source of the visible defects, to maintain the line, and to reduce the incidence of product defects. Purpose, the implementation content of the package manufacturing method of the present invention includes: (A) Packaging: The cut digital chips are respectively fixed on an uncut wire frame, and a digital transistor is connected with a wire and a peripheral encapsulation to form a digital transistor connection. State; (B) pre-cut: cut off the wires or extra parts to form a state where the transistors are not separated and tested; (C) test: test and inspect all unseparated transistor devices to detect defects Transistor; (File: Automatic recording or manual recording of the effectiveness of each transistor by testing equipment; (E) Printing: printed on the surface of the above-mentioned sealing colloid with the production brand and origin; etc .; (F) cutting: using a cutting machine to guide Make each transistor into an independent state, and draw out the flawed finished product during cutting; thereby achieving the benefit of increasing the quality control rate and reducing the cost of adjusting packaging equipment to reduce the incidence of defects.]

Page 61246141 V. Description of the invention (3) · The manufacturing method, step features, and other functions and purposes of the present invention are described in detail below according to the embodiments of the drawings. Please refer to the first figure. "Circular package test method" includes the following steps: (A) Packaging: Please refer to the second figure, which is to fix the cut multiple wafers 1 to the uncut and separated lead frame 2 (the lead frame 2 For the sake of acquaintance, the detailed structure is not repeated), and several metal wires 3 are connected to the signal contacts of the chip 1 and the pins 21 of the lead frame 2 (wiring operation), and are located on the periphery of the chip 1 or the A plurality of metal wires 3 are provided with an encapsulation procedure covered by a sealing compound 4 to form a digital transistor 10 to guide # the wire frame 2 neatly connected; (B) Pre-cutting: please refer to the third figure. All the untransformed transistors 10 are collectively transported to the cutting equipment or punching and shearing equipment by automated conveying equipment 30 or manually, so as to transfer specific conductive parts of the lead frame 2 (such as selected pins 2) 1) or excess material part 2 2 In addition, in order to form each transistor 10, it is still connected by the lead frame 2, but it is not independently separated and can be detected; wherein the automatic conveying device 30 can be a conveyor belt device or a robot arm device, etc .; (C) Testing: Collect all unseparated transistors 10 collectively by automated conveying equipment 30 or manually at the testing facility for inspection and testing ® to discover and distinguish defects, poor quality, or low efficiency Transistor; among them, the automatic conveying device 30 may also be a conveyor belt device or a robot arm device; and the detection device may include a probe tester to test the use effect, an X-ray inspection machine to inspect the metal inside the sealing compound 4 3 lines

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And other effects such as ultrasonic scanners, electron microscopes, temperature cycling devices, pressure cookers, etc .; (D) Generate test files. · Automatically record or manually record the packaging quality and use of each transistor 10 by the test equipment. Performance; and where the automatic recording includes digital data comparison and storage for pre-stored software, tape! Storage or storage, '': printed storage, etc .; and the manual recording can be operated by quality control operators Transform the test data into digital files, tape storage or paper card files, etc .; @ (E) Printing: collectively transport all unseparated transistors 10 to the printing equipment by automated conveying equipment 30 or manually, The surface of the above-mentioned sealing compound 4 is printed with the product shape number, brand, and place of origin. [Among them, the f automatic conveying equipment 30 can also be a conveyor belt device or a robot arm, etc., and the printing equipment, Contains the known printing equipment, transfer equipment or laser marking equipment, etc .; (F) Cut order: Automated conveying equipment 30 or manual, all unseparated The crystal 1 〇 is then transported to the cutting equipment or punching and shearing equipment, using this cutting equipment or punching and shearing equipment to cut each lead frame 2 so that each transistor] 〇 form an independent single state, and when cutting according to the above detection equipment = Defective or poor quality transistors are extracted from the test data, so that the finished transistor with good packaging and better quality is retained; the above-mentioned implementation procedures, steps and methods of the wafer packaging test method of the present invention have pre-cutting procedures (B), so the digital transistor 10 can be kept in a non-scattered single state for convenient transportation by automated conveying equipment 30 or manually, and follow-up testing procedures with other open equipment (C) and

1246141 V. Description of the invention (5) -------The printing order (E) is printed, so it can achieve the effects of fast conveying movement, convenient comprehensive inspection, and convenient 2 characters to reduce the cost of packaging inspection. Its _person 'is because the present invention performs the private printing sequence (E) after the detection procedure (c), so the printing equipment can be generated according to the detection procedure (C), and the red sequence ( ])) Data, only selected to print on good quality transistors, or to print different shapes according to different qualities, thereby eliminating the defects in the printing and expected to be eliminated, so it can improve the actual printing Speed 'prevents unnecessary printing time and material waste.

In addition, since the wafer packaging test method of the present invention uses the pre-cutting procedure (B) to keep the number of transistors 10 in a single state, so after the inspection procedure (C), the test file can be generated according to Procedure (D) comparison data or statistical data, etc., timely found that packaging equipment or pre-cut equipment (which can be the same as the single-cut equipment) caused those areas or those transistors often have packaging defects or cutting defects. Find out the cause of the product defect based on these data, and adjust, maintain or replace the packaging equipment or pre-cut equipment to improve its packaging process, so as to achieve the benefits of knowing the quality of the product.

To sum up, the "wafer package test method" of the present invention has indeed been applied and creative, and the use of the method is also novel and free of M, and the effect: the two purposes are indeed consistent, and it has been said that the progress has been reasonable to . In order to make a dagger, according to the law, a patent application is filed, but I would like to ask the Diaoyu Bureau for detailed review and grant the patent as a prayer. ,

1246141 Brief description of the drawings [Simplified description of the drawings] The first diagram is a system diagram of an embodiment of a wafer packaging test method of the present invention. The second diagram is a schematic diagram of a wafer packaging completion state of the present invention. The third figure is a schematic diagram of collective transportation of transistors according to the present invention. [Description of main component symbols] (A) Package (B) Precut (C) Test (D) Generate test file (E) Print; (F) Cut order; Transistor 10 Chip 1 Lead frame 2 Pin 21 Material part 2 2 Metal wire 3 Sealing gel 4 Conveying equipment 3 0

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Claims (1)

1246141 VI. Application for Patent Scope 1. A method for testing wafer packaging, including: (A) Packaging: The cut wafers are respectively fixed on uncut and separated lead frames, and wire bonding and peripheral encapsulation are used for encapsulation. Packaging process to form a collective connection state of digital transistors; (B) Pre-cutting: transporting unseparated digital transistors to cutting equipment or punching and shearing equipment collectively, cutting off a specific part of the lead frame to form the individual transistors The crystals are still connected by a lead frame and are not separated independently and can be tested; (C) Testing · The unseparated transistors are collectively transported to the testing equipment for inspection and testing. Defective transistors are found; (D) Generated Test file: Record the quality of each transistor through the testing equipment, (E) Printing: collectively transport the unseparated number of transistors to the printing equipment, and print a mark on the surface of the sealing colloid; (F) Cut: separate the unseparated The transistors are collectively transported to the cutting equipment or punching and shearing equipment, and each lead frame is cut to make each transistor form an independent single state, and the defective transistors are extracted during cutting. body. 2. The wafer packaging test method as described in item 1 of the scope of patent application, wherein the collective transportation of the digital transistors can be automated or manual; and the automated conveying equipment includes a conveyor belt device or a robot arm device. 3. The wafer packaging test method described in item 1 of the scope of patent application, wherein the testing equipment includes a probe tester, an X-ray inspection machine, and other devices such as an ultrasonic scanner, an electron microscope, and a temperature cycling device Page 11 1246141 Six 4 At least one of the scope of patent application and pressure cooker. The wafer packaging test method as described in item 1 of the scope of patent application, wherein the inspection equipment records include automatic recording and manual recording. The wafer packaging test method according to item 1 of the scope of patent application, wherein the printing equipment includes a printing equipment, a transfer equipment or a laser marking equipment. # Page 12