TWI244714B - Method for reducing size of solder ball in semiconductor device - Google Patents

Method for reducing size of solder ball in semiconductor device Download PDF

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Publication number
TWI244714B
TWI244714B TW093138882A TW93138882A TWI244714B TW I244714 B TWI244714 B TW I244714B TW 093138882 A TW093138882 A TW 093138882A TW 93138882 A TW93138882 A TW 93138882A TW I244714 B TWI244714 B TW I244714B
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TW
Taiwan
Prior art keywords
solder ball
solder
tin
ball
electrolyte
Prior art date
Application number
TW093138882A
Other languages
Chinese (zh)
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TW200620505A (en
Inventor
Cheng-Chia Chiang
Chun-Hsiung Lin
Chin-Huang Chang
Chih-Ming Huang
Min-Nan Tsai
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Siliconware Precision Industries Co Ltd
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Priority to TW093138882A priority Critical patent/TWI244714B/en
Application granted granted Critical
Publication of TWI244714B publication Critical patent/TWI244714B/en
Publication of TW200620505A publication Critical patent/TW200620505A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A method for reducing the size of a solder ball in a semiconductor device is provided. A ball-implanting device is used to mount at least one solder ball on a ball pad of a semiconductor element. Then, the solder ball mounted on the ball pad is placed in a suitable electrolytic solution and is electrolyzed to a suitable size. Thereby, the size of the solder ball can be reduced without changing the shape of the solder ball.

Description

1244714 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種半導體製造方法,更詳而言之, 係有關於一種縮小半導體裝置中銲球尺寸之製法。 【先前技術】 帝現今之半導體晶片為符合高性能、多功能以及小體積 之毛T產口口而求,須朝向高度積體化之方向發展,亦即須 將數里更多之電子元件整合於—特定尺寸之半導體晶片 —Y達到減少半導體封裝件體積之目的,習知之封裳s ΐΐίΐ球柵陣列(BGA)型式之半導體封裝件,並運户 二、秀、:广lrebondlng)方式將晶片與晶片*載件才目互玉 惟上H種封裝達職少封裝件體積之目的 在曰月u栅陣列半導體封|件,雖能較輕易將晶片堆^ 銲但是其所採用之導線接合法,會產〇 受線弧高度影響之::據封裝空間以及封裝件整體高度众 裝方法。此箱 lp chlp)型式之球栅陣列半導體封 而佔據㈣空門術確實可以改進因銲線線弧輻射外伸 題。 B以及封裝件整體高度受線弧高度影響之問 然而上述之步曰 導體封裝件古疮復日日t裝方法仍然不能完全解決整體半 X之問題’因為其半導體裝置所接置之鲜球 18210 5 1244714 高度仍然無法有效降低。因此, 件之薛球高度約為6。〇微米,當要;封 付合電子裝置薄型化趨勢時,除日日日片 :二低以 之外,、必須進—步考量將銲球的高度縮小身子度縮小 然,當銲球高度縮小時i 變小,進而造成製程上的種種困難。^的月豆積亦會相對的 銲球接置於基材上時, 七牛例而言,在執行將 行薛球的吸取、移動及/或置放等作掌,置裝置進 細的鮮球設置裝置,但如此顯然不符成新=更精 所面“μΓ 置於前述的半導體元件上, 7 ¢7 fern幻的另一個問題則 ♦ Μ 置入迴銲煻rr η 、、 又置有銲球的半導體元件 因銲球的進行迴銲 銲爐於迴的縮小而降低,即有可能為迴 k鮮衣私中所產生的熱 銲製程中發生銲球戈辰動,而導致在迴 路的不良後果。再Π )現象,造成鲜球短 (如小’因此在沾助鲜劑 備的極限而+,h〜 乂目則業界的銲球設置設 ^ ”求南度在200微米以下便無法實施。 成銲==二習知技術的缺陷,遂有提出以電鑛方式形 小銲球何’然而以電鑛方式形成輝球固然可以達到縮 的在曰球目1之目的’然而欲以電鑛方式形成高度200微米 ^企值^需花費相#長的形成時間,其產出效率完全 ㈣3 球設置與迴焊作業相比擬,難以透入量產 T王此外’電鑛形成銲球的技術除產出效率低落外 18210 1244714 尚有製品良率之p彳eg ^ 良卞之問靖,凊翏閱第 裝置10係透過電鍍方式來 圖所不,半導體 銲球盔法於電铲制f φ少、干ίΓ 11,惟由於電鍍形成之 此無法如二1=Γ制各個銲球的形成過程,因 …丄球型)平整之 整將谇成^曰ϊ+、^ 正的在于球u。外型的不平 -將以成鋅球南度的差異 ㈣不千 程而言,前述的習知㈣求精欲的+導體封褒製 & 。白知诔相然未獲完整的解決。 、、示上所述,如何能夠提供一 有銲球平整外型的銲球製法,遂成為y牛低銲球高度並保 【發明内容】 ” 亟待解決之課題。 在;知技術之種種缺點,本發明之主要目的 在方、七供_種可以形& 2〇〇微米 要目的 體裝置中銲球尺寸之製法。 门度知球之纟但小半導 本發明之另一目的在於提 之縮小半導趙裝置中鲜球二:可㈣成球型辉球 之在&球的=之又目的在於提供—種可以形成外型平整 ,干球的&小半導體裝置中銲球尺寸之H ( 為達成以上所述及其他目的,S之 置中銲球尺寸絮月之鈿小丰導體裝 件…Γ 有:設置銲球於相應之半導體元 接/上’透過迴㈣接置該料於該銲球塾上;將 求:上之銲球置於適當之電解液中,利用電: 方式俾將该鋅球電解離至適當的尺寸 解 置中:;=:Γ求形成技術,本發… 〒球尺权μ,透過電解銲球之方法,可達到同時 18210 1244714 降低銲球高度並保有銲球平整外型之目的。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實於 f :熟悉此技藝之人士可由本說明書所揭示之内: 目,、解本i明之其他優點與功效。本發明亦可 的具體實施例加以施行或應用,本說明書中的各項:= ==於不同硯點與應用,在不悖離本發明之精 ; 種修飾與變更。 退仃各 於本實施例巾,本發日狀縮小半導體裝置巾銲 之衣法係應用於覆晶型式的球栅陣列半導 :形成,:竭說明者,係本發明之縮小半導二= 製衣法设得應用於其他須設置鲜球的半導體封裝件 體裝i’==2D圖’其分別顯示本發明之縮小半導 衣置2〇中鲜球尺寸之製法的製造流程。 —如第2a圖所示,置備一基板2卜該基板21 表面2U及—相對於該第一表面2 面 其中,於該第-表面21a上形成有—曰面2Ib, 該基板接置半⑭日片22=日日片接置區211以供 ¥月豆日日片22之用;該基板21中佑外古十 數之導電跡線的佈線層(未圖示),並同時 兩端部分別形成有該銲球墊2i2,盆中,$第1矣 之輝球塾2丨2係形成於該晶片接置區2ιι ^表面21a 該晶片22以覆晶方式接置於該晶片接置ε 分,俾供 於該篦-丰而mu 日乃接置區211上,而形成 叫之銲球墊212則係用以提供該基板21 18210 1244714 植接複數個呈栅狀陣列排列的料(s〇ldei Baii),俾供該 基板21上之W 22與外部裝置電性連接。需特別說明者, 係該基板21可為傳統半導體基板、硬式有機基板(Ri㈣ 〇职謂SubStl.ate )或聚亞醯胺柔性基板(Polyimide Flex Tape) 〇 一"月茶閱第2B圖,如圖所示,透過銲球設置裝置(未 圖示)將至少一鲜球23接置於相應之半導體元件的銲球塾 212上。该銲球設置裝置可例如為透過真空方式吸取銲 球,再將該銲球設置於該鮮球墊212上。接著透過迴鲜作 ::將玄知球23接置於該銲球墊2〗2上。須特別說明者, 係銲球設絲置可透過其他方式將銲球設置於該銲球墊 212上,惟此非本案技術特徵所在,故不予贅述之。 曰請參閱第2C圖,如圖所示’將接置於該銲球塾212 之#球23置人適當的電解液24中之陽極25上。於本實施 例中j .组成該銲球23之材料可例如為錫/斜比例為 的二融合金(Eutetic A1〗〇y)、錫/銀/銅比例為96/3.5/0.5 的=鉛合金(Lead Free AU〇y )、船/锡比例為9⑽〇或9% 鉛合金(HighLead AU〇y)或如Ni/Au之金銲球等等。 明者,係該銲球23之配置方式以及組成材料當可 只^需要’而為熟習該項技術之人士作等效之替換,為 ^田間潔並避免模糊本案之技術特徵所在,故於此不擬 躬举之。 所、,方面,該電解液24應依據該銲球23之材料而有 差異,藉以針對該銲球23進行解離。舉例而言,若該銲 9 18210 1244714 = 23,前述之錫峨心之辑修透過將該銲球 々士入、當之電解液24中之陽極25上,則可將錫離子與 =子^出來。其原理係當金屬銲球23(陽極)置入電解 文〃:解的金屬陽離子,受電解液24中的極性分子吸 人在24中之陰極26上方向移動’故將該錫/錯共 "&金之銲球23之錫離子與㈣子解離並沉積於陰極26 上0 ,外’影響電解速度之因素則至少包括:電解液之濃 度,濃度低時極化作用較強,這是因為濃度低的電解液,、 更不易補充陰極區域陽離子缺乏的緣故;電流密度,電流 密度提f時極化作用增強,因為離子擴散速度和放電速 度,更落後電子運動速度所致;電解液溫度,升高電解液 溫度可降低極化作用;以及電解過程中之攪拌速度,攪拌 可使離子擴散加快降低極化仙。換言之,透過控制上述 的因素可達到調整電解速度之目的。 6月麥閱第2D目,如圖所示,當透過電解之方式將該 銲球23縮小至理想的高度時,隨即令該銲球23脫離該"電 解液24,藉以完成縮小銲球23之製程,並經迴銲後俾庐 得平整且縮小之銲球23、於本實施财,其理想高度可又 例如為50至100微米間,然可視實際需要進一步予以縮小。 綜上所述,本發明之縮小半導體裝置中銲球尺寸之製 法,透過電解傳統接置於銲球墊之銲球的方法,可達到同 時降低銲球高度並保有銲球平整外型之目的。 上述實施例僅為例示性說明本發明之原理及其功 18210 】0 1244714 效,而非用於限制本發明。任何熟習此項技藝之人士均可 在不達背本發明之精神及範疇下,對上述實施例進行修飾 與變化。因此,本發明之權利保護範圍,應如後述之申枝 專利範圍所列。 月 【圖式簡單說明】 第1圖係習知透過電鍍 封裝件剖面圖;以及 方式所直接形成銲球之半導體 第2A至2D圖分別為本發 尺寸之製法的整體製作流程。% + + 中銲球 【主要元件符號說明】 10 半導體裝置 11 辉球 20 半導體裝置 21 基板 21a 第一表面 21b 第二表面 211 晶片接置區 212 銲球墊 22 晶片 23、235 鲜球 24 電解液 25 陽極 26 陰極 18210 111244714 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor manufacturing method. More specifically, it relates to a manufacturing method for reducing the size of solder balls in a semiconductor device. [Previous technology] The current semiconductor chip of Dili is in order to meet the high-performance, multi-functional and small-volume hair T production port. It must be developed in a highly integrated direction, that is, more electronic components must be integrated for several miles. In-semiconductor wafers of a specific size-Y achieves the purpose of reducing the volume of semiconductor packages. The conventionally-known semiconductor package of the ball grid array (BGA) type is used, and the wafer is used in the second method. It is only compatible with the chip * carrier, but the purpose of the H package is to reduce the volume of the package. The purpose is to use a U-gate array semiconductor package. Although the chip can be easily stacked and soldered, the wire bonding method is used. , It will produce 0 Affected by the height of the line arc: According to the packaging space and the overall height of the package, the crowd mounting method. This box lp chlp) type ball grid array semiconductor package and occupying the hollow gate can indeed improve the problem of arc radiation due to wire bonding. B and the overall height of the package is affected by the height of the line arc. However, the above step says that the method of mounting the conductive package with ulcers can not completely solve the problem of the overall half X because of the fresh balls 18210 connected to its semiconductor device. 5 1244714 The height still cannot be lowered effectively. Therefore, the height of the Xue ball is about 6. 〇micron, when it is necessary to reduce the thickness of sealed electronic devices, in addition to daily films: less than two, you must go further-consider the reduction of the height of the solder ball Time i becomes smaller, which causes various difficulties in the manufacturing process. ^ The moon bean product will also be placed on the substrate with the corresponding solder ball. For example, in the case of seven cows, the suction, movement, and / or placement of the Xue ball is performed as a palm, and the device is placed into a fine fresh product. The ball is provided with a device, but it obviously does not conform to the new = more refined. "ΜΓ is placed on the aforementioned semiconductor element. Another problem of 7 ¢ 7 fern magic is ♦ 回 put back solder 煻 rr η The semiconductor component of the ball is reduced due to the shrinking of the solder ball in the reflow soldering furnace, that is, the solder ball may be moved during the heat welding process generated in the fresh knitting clothes, resulting in defective circuit Consequences. Then Π) phenomenon, resulting in short fresh balls (such as small 'so + + at the limit of freshener preparation, h ~ 乂 eye is the industry's solder ball setting settings ^ ”below 200 microns can not be implemented . Welding == Two shortcomings of the conventional technology, it has been proposed to form small solder balls by electric ore method 'However, the formation of glow balls by electric ore method can certainly achieve the purpose of shrinking ball 1' Mining method to form a height of 200 microns ^ Enterprise value ^ It takes a long time to form, its output efficiency is completely The 3 ball setting is similar to the reflow operation, and it is difficult to penetrate into the mass production of T King. In addition, the technology of forming solder balls in electric mines has a low output efficiency. 18210 1244714 There is still a p 良 eg of product yield. The 10th device is shown by electroplating. The semiconductor solder ball helmet method uses the electric shovel to make f φ less and dry ΓΓ. However, due to the formation of electroplating, it is not possible to form each solder ball as 2 = Γ. The process, because ... 丄 ball type) The whole of the flattening will be ^^ ^ +, ^ is the ball u. Unevenness of the appearance-the difference in the south degree of zinc spheroids will not be considered. For the most part, the aforementioned practice seeks the perfect + conductor sealing system &. Bai Zhizheng was not completely resolved. As shown above, how to provide a solder ball manufacturing method with a flat shape of solder balls has become a low solder ball height and maintains the [contents of the invention] "Problems to be solved urgently. In the various shortcomings of the known technology, The main purpose of the present invention is to make a solder ball size in a square, seven-dimensional, and 200-micron main body device. The degree of the ball is known, but the small semiconductor is another object of the present invention to reduce it. Fresh ball in semi-conductor Zhao device: The ball can be formed into a ball-shaped glow ball. The purpose of the ball is to provide a kind of H that can form a flat, dry ball in a small semiconductor device. (In order to achieve the above and other purposes, the size of the S-centered solder ball is small and the size of the Xiaofeng conductor assembly ... Γ has: set the solder ball to the corresponding semiconductor element connection / connection 'through the back connection to place the material on The solder ball is placed on top; the above-mentioned solder ball is placed in an appropriate electrolytic solution, and the zinc ball is electrolyzed to an appropriate size by using electricity: Mode 求:; … The ball ruler μ can be achieved at the same time by the method of electrolytic solder ball 18210 124471 4 The purpose of reducing the height of the solder ball and maintaining the flat shape of the solder ball. [Embodiment] The following is a description of the actuality of the present invention by a specific embodiment f: Those who are familiar with this technology can be disclosed in this specification: ,, explain the other advantages and effects of this Ming. The specific embodiments of the present invention can also be implemented or applied, the items in this description: = == in different points and applications, without departing from the essence of the present invention; This modification is different from the towel of this embodiment, and the method for welding the semiconductor device of the present invention is applied to a flip-chip type ball grid array semiconductor. Reduced semiconducting second = The manufacturing method is set to be applied to other semiconductor packages that need to be provided with fresh balls. I '== 2D drawing' which respectively show the method of the method for reducing the size of fresh balls in the semiconducting device 20 of the present invention. Manufacturing process.-As shown in Fig. 2a, a substrate 2 is provided, and the surface 2U of the substrate 21 is provided.-The surface 2U is opposite to the first surface. Among them, a surface 2Ib is formed on the first surface 21a. Set a half-day Japanese film 22 = Japanese-Japanese film receiving area 211 for ¥ month It is used for beans and sun-chips 22. The wiring layer (not shown) of the dozens of ancient conductive traces in the substrate 21, and the solder ball pads 2i2 are formed at both ends, in the basin, $ 1辉 之 辉 球 塾 2 丨 2 is formed on the wafer receiving area 2ι ^ surface 21a, the wafer 22 is placed in a flip-chip manner on the wafer placement ε points, and is provided for the 篦 -Feng and mu Ri Nai placement Area 211, and a solder ball pad 212 formed thereon is used to provide the substrate 21 18210 1244714 to plant a plurality of materials (soldei Baii) arranged in a grid array, for W 22 and The external device is electrically connected. The substrate 21 may be a conventional semiconductor substrate, a rigid organic substrate (Ri㈣ 〇SubStl.ate), or a polyimide flexible tape (Polyimide Flex Tape). As shown in FIG. 2B, as shown in the figure, at least one fresh ball 23 is connected to a corresponding solder ball 212 of a semiconductor device through a solder ball setting device (not shown). The solder ball setting device may, for example, suck the solder ball through a vacuum method, and then set the solder ball on the fresh ball pad 212. Then, through the fresh preparation :: Place the Xuanzhi ball 23 on the solder ball pad 2 2. It should be particularly noted that the solder ball arrangement wire can be used to set the solder ball on the solder ball pad 212 by other methods, but this is not the technical feature of this case, so it will not be described in detail. Please refer to FIG. 2C. As shown in the figure, the #ball 23 placed on the solder ball 塾 212 is placed on the anode 25 in a proper electrolyte 24. In this embodiment, j. The material constituting the solder ball 23 may be, for example, a two-fusion gold (Eutetic A1) with a tin / slope ratio, and a lead alloy with a tin / silver / copper ratio of 96 / 3.5 / 0.5. (Lead Free AU〇y), ship / tin ratio of 9⑽ or 9% lead alloy (HighLead AU〇y) or gold solder balls such as Ni / Au, etc. It is clear that the configuration of the solder ball 23 and the constituent materials can be replaced only by those who are familiar with the technology. It is necessary to understand the technical characteristics of the case, so it is here. Don't intend to give it up. Therefore, the electrolyte 24 should be different according to the material of the solder ball 23, so as to dissociate the solder ball 23. For example, if the solder 9 18210 1244714 = 23, the aforementioned repair of the tin-E Xin through the solder ball into the anode 25 in the electrolyte 24, the tin ions and = ^ come out. The principle is that when the metal solder ball 23 (anode) is placed in the electrolytic solution: the decomposed metal cations are attracted by the polar molecules in the electrolyte 24 and moved in the direction of the cathode 26 in 24. Therefore, the tin / misalignment is ; & The tin ions of the gold solder ball 23 dissociate from the ions and deposit on the cathode 26. The factors that affect the electrolysis rate include at least: the concentration of the electrolyte, and the polarization effect is strong when the concentration is low. Because of the low concentration of the electrolyte, it is more difficult to compensate for the lack of cations in the cathode region; the current density, the polarization effect increases when the current density is increased, because the ion diffusion speed and the discharge speed are behind the speed of the electrons; the temperature of the electrolyte , Increasing the temperature of the electrolyte can reduce the polarization effect; and the stirring speed during the electrolysis process, the stirring can accelerate the ion diffusion and reduce the polarization fairy. In other words, by controlling the above factors, the purpose of adjusting the electrolysis speed can be achieved. In June, the 2D head of the wheat reading, as shown in the figure, when the solder ball 23 is reduced to a desired height by means of electrolysis, the solder ball 23 is then released from the " electrolyte 24, thereby completing the reduction of the solder ball 23 After the re-soldering process, flattened and shrunk solder balls 23 are obtained. In this implementation, the ideal height can be, for example, between 50 and 100 microns, but can be further reduced according to actual needs. In summary, the method for reducing the size of solder balls in a semiconductor device of the present invention can reduce the height of the solder balls and maintain the flat shape of the solder balls by electrolyzing the solder balls traditionally connected to the solder ball pads. The above embodiments are only for illustrative purposes to explain the principles and functions of the present invention, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patents mentioned below. [Simplified illustration of the drawing] Fig. 1 is a conventional cross-sectional view of a package through electroplating; and semiconductors directly forming solder balls by means of the method. Figs. 2A to 2D are the overall manufacturing process of the manufacturing method of the size. % + + Medium solder ball [Description of main component symbols] 10 Semiconductor device 11 Glow ball 20 Semiconductor device 21 Substrate 21a First surface 21b Second surface 211 Wafer receiving area 212 Pad ball 22 Wafer 23, 235 Fresh ball 24 Electrolyte 25 anode 26 cathode 18210 11

Claims (1)

1244714 十、申凊專利範圍: 】·種縮小半導體裝置中銲球尺寸之製法,包括·· 設置鋅球於相應之半導體元件的銲球墊上; 透過迴#以接置該鮮球於該銲球墊上;以及 將接置於該銲球墊上之銲球置於適當之電解液 中’俾將該銲球解離至適當的尺寸。 •士申明專利範圍第1項之製法,其中,該半導體元件係 為半導體基材。 3. 如申請專利範圍第!項之製法,其中,該半導體基材係 為傳統半導體基板、硬式有機基板(Rigid Organic SubStrate )以及聚亞醯胺柔性基板(p〇iyimide Fiex τ 之其中一者。 4. 如申請專利範圍第1αΙ之製法,其中,該銲球係為錫/ 鉛比例為63/37的共融合金(Eutetic AU〇y)、錫/銀/銅 比例為96/3.5/0.5的無錯合金(Lead Free Alloy)、錯/ 錫比例為90/10的高雜合金(High Lead Alloy)、敍/錫 比例為95/5的高鉛合金以及Ni/Au之金銲塊(G〇ld Blimp)之其中一者。 5. 如申明專利範圍第丨項之製法,其中,該解離之速度係 透過控制至少一選自由電解液之濃度、電流密度、電解 液溫度以及電解過程中之攪拌速度所組成之因素 控制。 ’' 6· —種縮小半導體裝置中銲球尺寸之製法,包括: 設置銲球於相應之半導體元件的銲球墊上; 18210 12 1244714 透過迴銲以接置該銲球於該銲球墊上; 將接置於該銲球墊上之銲球置於適當之電解液 中,俾將該銲球解離至適當的尺寸;以及 將該銲球予以迴銲。 7.如申請專利範圍第6項之製法,其中,該半導體元件係 為半導體基材。 8·如申請專利範圍第6項之製法,其中,該半導體基材係 為傳統半導體基板、硬式有機基板(Rigid Organic Substrate )以及聚亞醯胺柔性基板(Polyimide Flex Tape) 之其中一者。 9.如申請專利範圍第6項之製法,其中,該銲球係為錫/ 錯比例為63/37的共融合金(Eutetic Alloy )、錫/銀/銅 比例為96/3.5/0.5的無錯合金(Lead Free Alloy )、船/ 錫比例為90/10的高鉛合金(High Lead Alloy)、鉛/錫 比例為95/5的高鉛合金以及Ni/Au之金銲塊(Gold Bump )之其中一者。 10·如申請專利範圍第6項之製法,其中,該解離之速度係 透過控制至少一選自由電解液之濃度、電流密度、電解 液溫度以及電解過程中之攪拌速度所組成之因素予以 控制。 13 182101244714 X. Application scope of patent:】 · A method for reducing the size of solder balls in semiconductor devices, including: · setting zinc balls on the solder ball pads of corresponding semiconductor components; through the back # to place the fresh balls on the solder balls Pads; and placing the solder balls attached to the solder ball pads in an appropriate electrolyte to dissociate the solder balls to the appropriate size. • The method of claim 1 of the patent scope, in which the semiconductor element is a semiconductor substrate. 3. If the scope of patent application is the first! The manufacturing method according to clause 1, wherein the semiconductor substrate is one of a conventional semiconductor substrate, a rigid organic substrate (Rigid Organic SubStrate), and a flexible flexible substrate of polyimide (poiyimide Fiex τ). The manufacturing method, wherein the solder ball is a lead free alloy with a tin / lead ratio of 63/37 eutetic AU〇y and a tin / silver / copper ratio of 96 / 3.5 / 0.5 One of High Lead Alloy with 90/10 wrong / tin ratio, High Lead alloy with 95/5 Syria / tin ratio, and Gold Blimp of Ni / Au. 5. As stated in the method of claim 丨, the dissociation speed is controlled by controlling at least one factor selected from the group consisting of electrolyte concentration, current density, electrolyte temperature, and agitation speed during electrolysis. '6 · —A method for reducing the size of a solder ball in a semiconductor device, including: setting a solder ball on a solder ball pad of a corresponding semiconductor element; 18210 12 1244714 placing the solder ball on the solder ball pad through reflow; Place on the solder ball pad The solder balls above are placed in an appropriate electrolyte, and the solder balls are dissociated to an appropriate size; and the solder balls are re-soldered. 7. If the manufacturing method according to item 6 of the patent application scope, wherein the semiconductor element is It is a semiconductor substrate. 8. The manufacturing method according to item 6 of the patent application range, wherein the semiconductor substrate is a conventional semiconductor substrate, a rigid organic substrate (Rigid Organic Substrate), and a polyimide flexible tape (Polyimide Flex Tape). One of them. 9. According to the manufacturing method of item 6 of the patent application scope, wherein the solder ball is an Eutetic Alloy with a tin / wrong ratio of 63/37 and a tin / silver / copper ratio of 96 / 3.5 /0.5 Lead Free Alloy, High Lead Alloy with 90/10 ship / tin ratio, High Lead Alloy with 95/5 lead / tin ratio, and Ni / Au gold solder bumps (Gold Bump). 10. The manufacturing method according to item 6 of the patent application range, wherein the dissociation rate is controlled by at least one selected from the group consisting of the concentration of the electrolyte, the current density, the temperature of the electrolyte, and the electrolysis process. Factors in the mixing speed Control. 13 18210
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