1244266 五、發明說明（1) 【發明所屬之技術領域^ 本毛明係提供—種邏輯 :種當該分析儀進行檢測—待資料顯示方④，尤指 f立時，該分析儀之控制電：可電路中發生觸發條件 數的波數後，gp作， 可根據其所計管 幕將發生觸發停二將檢測數據儲存至記情ί，二脈波 知玍觸《條件成立後且 U體並透過螢 出來。 間之檢測數據顯示 【先前技術】 、 按’邏輯分析儀為一種 二數位電路中之檢測數據，以；==儀器，它能 Format)# -山十 ’條理的格式（ 數位電路的動作過：，· ： ：J用者能利用它很方便的將 輯分析儀内部為心有:己；體3分析儀的螢幕上。而邏 生檢測錯誤前之於 °〜_匕可以用來收集並儲存發 察到發生檢測供二1ί數據，但由於使用者也希望能同時觀 析儀也罝有#二块則後之檢測數據，所以大部分的邏輯分 定的時舰、r r檢測數據收集在檢測錯誤發生後，並經過設 由 τ 。1〇ck)數目後才停止的能力。 易的在菸^ ^分析儀具有組合觸發之功能，所以它能很容 料的收:檢測錯誤狀況下，發出一個觸發信號來停止資 觸發（f 並顯不觸發前所收集的資料’這種方式稱為前 是很有 r e — t r i g g e r )，這在數位系統的分析 =t认用的’因為它讓使用者能分析觸發前發生的信號， 呈 ^出某些異常狀況發生的原因。為了使邏輯分析儀 /、備分析觸發後之資料的能力，大部分邏輯分析儀也具 第4頁 12442661244266 V. Description of the invention (1) [Technical field to which the invention belongs ^ This Maoming provides-a kind of logic: when the analyzer is tested-to be displayed by the data ④, especially when f stands, the control power of the analyzer: After the wave number of the triggering condition number occurs in the circuit, gp works, and the trigger screen will be triggered according to its count. The detection data will be stored in the memory. The second pulse wave knows that "After the condition is established and the U body is Come out through the firefly. Display the previous test data. [Prior technology], press' Logic Analyzer 'as a test data in a two-digit circuit, with == instrument, it can Format) #-山 十' logical format (the action of the digital circuit: ， ： ： J The user can use it to easily edit the inside of the analyzer. The body is on the screen of the body 3 analyzer. The logic detection error before ° ~ _ can be used to collect and store I found out that the detection data for the 2 1 ί was detected, but because the user also hopes that the analyzer also has # 2 blocks of detection data at the same time, most of the logically assigned time ship and rr detection data are collected in the detection. The ability to stop after an error has occurred, and after setting a number of τ.10ck). The easy-to-use analyzer has a combined triggering function, so it can receive data very well: under the detection of an error condition, it sends a trigger signal to stop the triggering (f and displays the data collected before the triggering. The method is called “re-trigger”, which is used in the analysis of digital system = t is accepted because it allows the user to analyze the signal that occurred before the trigger and present the cause of some abnormal conditions. In order to make the logic analyzer and / or the ability to analyze the triggered data, most logic analyzers also have page 4 1244266
有、、觸發延遲，/ ( τ r i g g e r n ,a , D e 1 a y )的功能 心由數位延遲產生器」Dlgltai Dei" 作?卢m t〇 r)來兀& (如第-圖所示）。當觸發 時，它先被送到數位延遲產生器中，而數 it為接收到此二觸發信號後，開始計數由使用者 叹疋、犄脈數目。當計數之時脈到達預設值時，其數位 延遲產生器便產生一個後觸發信號（p 〇 s t _ t r i g g e Γ )到邏輯分析儀之記憶體，以停止資料的 收集。 、 由於有了此種觸發延遲功能，使用箸可以在待測的一 串資料中，任意定義出一個記憶窗口 （ M e m 〇 r y Window)(如第二圖所示）。由於資料可能非常的 長’而記憶容量有限，所以我們移動延遲窗口，即可以有 限的記憶容量觀察一大串資料使用。 惟，一般傳統邏輯分析儀之觸發延遲（ Trigger De 1 ay)的功能’其缺點有下列幾 一、 使用者必須要很清楚的知道需要設定多少個延遲時脈 ’才會到達所需要資料的時間點。 二、 延遲時間的長度容易受到限制，例如延遲時間以1 〇 n s ( 0· 0 0 0 〇 〇 〇 〇 〇 1秒）為一單位，假如 使用者如需延遲的時間為1秒的話’則其計數器就必 須要很大，所以其延遲時間的長度容易受到限制。 三、 使用者看不到時間延遲時的即時波形資料。Yes, trigger delay, / (τ r i g g e r n, a, D e 1 a y) The function of the core is a digital delay generator "Dlgltai Dei" as "Lu m t0 r) to Wu & (as shown in Figure-). When triggered, it is first sent to the digital delay generator, and after counting the two trigger signals, it starts counting the number of sighs and pulses by the user. When the counting clock reaches a preset value, the digital delay generator generates a post-trigger signal (p s t _ t r i g g e Γ) to the memory of the logic analyzer to stop data collection. With this trigger delay function, using 箸, you can arbitrarily define a memory window (M e m 0 r y Window) in a series of data to be measured (as shown in the second figure). Since the data may be very long, and the memory capacity is limited, we move the delay window, that is, we can observe a large amount of data with limited memory capacity. However, the function of the trigger delay (Trigger De 1 ay) of conventional logic analyzers has the following disadvantages. The user must clearly know how many delay clocks need to be set to reach the required data time. point. Second, the length of the delay time is easy to be limited. For example, the delay time is in units of 10ns (0, 000, 000, 0001 seconds). If the user needs to delay for 1 second, then its The counter must be large, so the length of its delay time is easily limited. 3. The user cannot see the real-time waveform data during the time delay.
1244266 五、發明說明（3) 是以，若 情況下，又能 能更加強大完 在。 【發明内容】是以，發 (Trigg 子儀器之製造 種解決的方法 開發設計出全 誕生，俾能摒 本發明之 資料顯示方法 中發生觸發條 控制資料，計 波數之波數， 存至其記憶體 制電路即停止 生觸發條件成 為便 責 置特徵及其功 酉己合圖式’詳 洋細說明： 本發明係 能開發設計出一種右 ^ , 裡在不更改儀态太多結構之 將上述的缺點改進，便邏輯 整，gp氧你塞卜卜y J便t輯刀析儀的功 P為k事此仃業者所亟待努力之 明人有鑑於前 e r Del 經驗和技術累 ’在經 新之— 除先前 t要目 ’其主 件成立 算取樣 繼續將 ’直到 將檢測 立後且 過不斷 種邏輯 技藝之 的，係 要於分 時，可 時間的 自待測 取樣之 數據儲 延遲一 審查委員能對 效，做更進一 細說明如下。 述習用邏輯分析儀 a y)的缺失，乃 積’針對上述缺失 的研究、實驗與改 分析儀之資嵙顯示 諸多缺失。 提供一種全新之邏 析儀進行檢測一待 令控制電路依據事 停止脈波數，再根 數位電路所傳送之 時間到達該停止脈 存至記憶體，並透 段時間之檢測數據 本發明之目的、形 步之認識與瞭解， 之觸發延遲 依其從事電 悉心研究各 良後，終於 方法的發明 輯分析儀之 測數位電路 先被設定之 據該停止脈 檢測數據儲 波數後，控 過螢幕將發 顯示出來。 狀、構造裝 兹舉實施例 種「邏輯分析儀之資料顯示方法」，係當1244266 V. Description of the invention (3) That is, if it is, it can be more powerful and complete. [Summary of the Invention] The development and design of the Trigg sub-instrument manufacturing method are all designed and developed. It is not possible to eliminate the occurrence of the trigger bar control data in the data display method of the present invention, and store the wave number of the wave number in it. The memory system circuit stops the triggering condition and becomes a responsible feature and its function. The detailed description: The present invention can develop and design a right ^, which will not change the structure of the state too much. improved shortcomings, they whole logic, GP oxygen you will Sebo Bu t y J P Series power analyzer knife is k matter of this effort Ming Ding urgent in view of the industry before er Del accumulated experience and technology 'in the new warp In addition to the above, except for the previous t 'the main component is established and the sampling continues,' until the detection is established and the logical skills are continuously developed, it is necessary to delay the review of the data storage of the sample to be tested in time sharing. Members can make further improvements and explain in more detail as follows. The lack of the conventional logic analyzer ay) describes the lack of research, experimentation, and improvement of the analyzer's resources for the above-mentioned defects. Provide a brand-new logic analyzer to detect a standby control circuit to stop the number of pulses according to the event, and then the time transmitted by the digital circuit reaches the stop pulse to be stored in the memory, and the detection data for a period of time. The knowledge and understanding of the step-by-step, the trigger delay is based on the electrical and careful research of each good, and finally the method of the invention's invention. The digital circuit of the analyzer is first set. After the number of stored waves is detected based on the stop pulse, the screen will be controlled. Hair show up. State, structure and installation Examples include a "data display method of a logic analyzer", which is
1244266 五、發明說明（4) __— — 該分析儀進行檢測一待測數位電路中 ，令控制電路依據事先被設定之控制;料觸I條件成立時 的停止脈波數，再根據該停止脈波數之j j计异取樣時間 測數位電路所傳送之檢測數據儲存至1 ^ ，繼績將自待 之時間到達該停止脈波數後，控制電路;直到取樣 =， Γ觸發條件成立後且延遲 丰又日守間之檢測數據顯示出來。 【實施方式】 在本發明中，請參閱第三圖所示，該事先被設定之控 制貢料乃為使用者藉由輸入裝置（如：鍵盤、滑鼠、軌跡 球、觸控板等）對該邏輯分析儀進行設定，其控制資料則 包括有顯示頁數、記憶體大小（r A M S i z e )和觸 發點（丁 r i g g e r p 〇 i n t )的位置，由該第三 圖所示’其中T 1為取樣時間（S a m p 1 e c 1 〇 c k )的停止波數，即記憶體大小（r a M Size)減觸發點（Trigger Point); 而觸發點（Tr igger Point)都是同一點（ 第一頁···第N頁）；第二頁抓資料是由第一頁的觸發 點（Tr igger Point)抓起，第二頁再覆蓋 於第一頁上面。 在本發明中，請參閱第四圖所示，當該邏輯分析儀被 開啟時，將依下列步驟進行處理： (4 0 1 )讀取使用者由輸入裝置處設定之控制資料（如 :選擇顯示第η頁數、記憶體大小、觸發點位1244266 V. Description of the invention (4) __— — The analyzer detects a digital circuit under test, so that the control circuit is based on the control set in advance; the number of stop pulses when the condition of material I is satisfied, and then according to the stop pulse The detection data transmitted by the jj counting different sampling time measuring digital circuit is stored to 1 ^, and the control circuit is controlled after the waiting time reaches the stop pulse number; until sampling =, Γ is triggered after the trigger condition is established and delayed The test data of Feng Youri Mori showed. [Embodiment] In the present invention, please refer to the third figure, the control tribute set in advance is for the user to use an input device (such as: keyboard, mouse, trackball, touchpad, etc.) The logic analyzer is set, and its control data includes the number of display pages, memory size (r AMS ize), and the position of the trigger point (丁 riggerp 〇int), as shown in the third figure, where T 1 is the sampling The stop wave number of time (S amp 1 ec 1 〇ck), that is, the memory size (ra M Size) minus the trigger point (Trigger Point); and the trigger points (Tr igger Point) are all the same point (first page ·· · Page N); The second page grabbing data is picked up by the trigger point of the first page, and the second page covers the first page. In the present invention, please refer to the fourth figure. When the logic analyzer is turned on, it will be processed according to the following steps: (4 0 1) Read the control data set by the user from the input device (such as: select Display the nth page, memory size, trigger point
第7頁 1244266 :、發明說明（5) 置等）； (4 0 2 )將该貧料存在記憶體，以便當觸發（ 丁 r 1 g g e r )條件成立時，可根據該資料 1算取樣時間的停止脈波數； 田"亥刀析儀進行檢測一待測數位電路中發生觸 發條件成立時； 給τ知王觸 々控制電路依據事先被設定之控制資料，管 取樣時間的停止脈波數； ^ 3 Ξ =測數位電路所傳送之檢測數據儲存 將取樣時間的停止脈波數減1 ; 判=該取樣時間的停止脈波數是否為Q;若是 ’矣k績下列步驟（4 η β ). 4 0 8 (4 〇 5 ) ( 4 〇 8 ) ’否則，進行步驟 2將檢測數據儲存至記憶體 儲存之檢測數據，透過螢幕將 ？= 然而 ::;r:段時間之檢測數據 以形成一單機形式之^^為可直接設立於分析儀上，用 電腦所有，此種方^ :析儀’另’其螢幕亦可為外部 電腦相連接，ϊϋί::析儀處設立-傳輸介面來與 過傳輪介面將記憶體中檢測數據儲存至記憶體後，透 儀相連接之電 利二=測=據傳送到—與該分析 “間之檢測數據，藉由該電腦之榮ί:;:: 1244266 五、發明說明（6) 〇 以上所述，僅為本發明最佳具體實施例，惟本發明之 構造特徵並不$限於此，任何熟悉該項技藝者在本發明領 域内，可輕易心及之變化或修飾，皆可涵蓋在以下本 專利範圍。 μ 綜上所ί碹i ϊ:上述之邏輯分析儀之資料顯示方、去 於使用時，為確貝此達到其功效及目的，故 $去 實用性優異之創作，為符合發明專利之:月喊為- 提出申請：盼審委早曰賜准本案，以保障牛/依法 創作’倘若鈞局審委有任何稽*，請之辛苦 明人定當竭力配合，實感公便。 不函丸示，發 1244266 圖式簡單說明 【圖式簡單說明】 第一圖 係為習用數位延遲產生器之方塊示意圖。 第二圖 係為習用記憶窗口之方塊示意圖。 第三圖 係為本發明設定控制資料之示意圖。 第四圖 係為本發明之動作流程圖。Page 7 1244266 :, description of the invention (5) settings, etc .; (4 0 2) the lean material is stored in the memory, so that when the triggering condition (but r 1 gger) is established, the sampling time can be calculated according to the data 1 The number of pulses to stop; The field " Hydraulic analyzer detects a trigger condition in the digital circuit to be tested; when the triggering condition is met in the digital circuit to be tested, the control circuit is used to control the number of pulses to stop the sampling time based on the control data set in advance. ; ^ 3 Ξ = store the detection data transmitted by the measuring digital circuit and reduce the stop pulse number of the sampling time by 1; judge = whether the stop pulse number of the sampling time is Q; if it is' 矣 k the following steps (4 η β ). 4 0 8 (4 〇5) (4 〇 8) 'Otherwise, go to step 2 to store the test data to the test data stored in the memory. = However ::; r: The detection data for a period of time to form a stand-alone form ^^ can be directly set up on the analyzer, owned by a computer, this way ^: The analyzer 'other' screen can also be an external computer Connected, 设立 ί :: Analyzer setup-transmission interface to connect with the transmission wheel interface to store the test data in the memory to the memory, and the electric instrument connected to the instrument will be measured = data transmitted to-and the analysis " The test data of this computer is based on the glory of this computer :::: 1244266 V. Description of the invention (6) The above is only the best embodiment of the present invention, but the structural features of the present invention are not limited to this Any changes or modifications that anyone skilled in the art can easily understand in the field of the present invention can be covered by the following patents. Μ In summary: 碹 显示 i ϊ: The above data display method of the logic analyzer, When using it, in order to make sure that it achieves its efficacy and purpose, it goes to a creative creation with excellent practicability. In order to comply with the invention patent: Yueyuewei-File an application: I hope the review committee will grant this case early to protect the cattle / Create according to the law 'If there is any inspection by the jury of the Bureau, please work hard The Ming people must cooperate with every effort, and feel the convenience. Do not send a pill, send a 1244266 diagram. [Schematic description] The first picture is a block diagram of a conventional digital delay generator. The second picture is a conventional memory window. Block diagram. The third diagram is a schematic diagram of setting control data of the present invention. The fourth diagram is a flowchart of operations of the present invention.
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