1244264 九、發明說明： 【發明所屬之技術領域】 本發明提供一種具有遲滯特性之電流比較器，尤指―考重 可界定出轉態點之具有遲滯特性曲線之電流比較器。 【先前技術】 請參考第1圖，第1圖為習知具有遲滯特性之電流比較 器10之電路圖。電流比較器1〇包含五個NMOS電晶體 Μ卜M2、M5、M6與M8以及三個PMOS電晶體M3、M4 與M7。 電晶體Ml與M2的閘極相連接，並由節點N1的輪入 電壓經由閘極以驅動兩電晶體。電流比較器1〇中的電晶體 M5與M6係為電流槽（current sink)，由節點N2的輪入電 壓經由閘極以驅動兩電晶體。電晶體Ml與M3的汲極分別 連接至節點N3。另外，連接電晶體M1與M3汲極的節點 N3另連接於電晶體M3與M4的閘極。 同樣地，電晶體M2與M4的汲極分別連接至節點 另外，連接電晶體M2與M4汲極的節點N4另連接於命 1244264 體M7與M8的閘極。此外，電流 分別為節點N5與N6，係八別、車垃又〇的兩個輸入端 、㈣.係刀別連接於電晶體⑷與⑽的 祕，電流比較器Η)的輸出端係連接於節 :二：極分別連接於電一 ^ =二_的汲極亦連接於電壓源，，電晶體^ y連接於即點Ν5，電晶體副的源極連接於節點鳩。 在:1圖中，節點Ν5接收輪入電流η，而節點Ν6接收一 芩考電流12。 請參考第2圖，第2圖為第！圖電路之電流/電壓圖，電 晶體M7與M8以及參考電流12係用以控制電流比較器ι〇 之遲滯特性曲線的大小。請再次參閱第丨圖，當輸出電壓 ▽_為低電壓，將啟動電晶體厘7，而電晶體厘7輸出電流 Im7至節點N5，另一方面，輸入電流n亦流入節點N5，以 使電流比較器10改變輸出電壓v〇ut的狀態。此時，輸出電 壓Vout為_2\/((11+^)-12)，而（ii+iM7)-I2的值必須為負值才 可改受輸出電壓v〇ut為而電壓。相反地，當輸出電壓 為高電壓，將啟動電晶體M8，而電晶體M8輸出電流IM8 至節點N6，另一方面，參考電流12亦流入節點N6，以使 笔 比較裔10改變輸出電壓Vout的狀態。此時，輸出電壓 Vout為-Zv(I1-(I2+Im8))，而I1_(I2+Im8)的值必須為正值才可 改變輸出電壓ν。^為低電壓。 1244264 由於當電晶體M7導通且（Π+ΙΜ7)-Ι2為負數時，輸出電 壓將從低電壓轉態為高電壓，即轉態點a處輸出電壓 Vout轉態。相反地，當電晶體M8導通且I1-(I2+IM8)為正數 時，輸出電壓將從高電壓轉態為低電壓，即轉態點b 處輸出電壓VQUt轉態。因此，第2圖中的轉態點a與b的 位置，係分別受電晶體M7與M8的控制。然而，電晶體 M7與M8係為不同極性之元件，電晶體M7係為PMOS電 晶體，而電晶體M8係為NMOS電晶體，在製程上，很難 去控制電晶體M7與M8的參數漂移的一致性，以控制遲滯 特性曲線中轉態點a與b的位置，而造成電流比較器輸出 錯誤。舉例來說，假設所需的滯特性曲線為參考電流12為 零，轉態點a與b分別為-200uA與200uA之遲滯特性曲線， 但在製程中可能一些製程的變化或差異使得遲滯特性曲線 之轉態點a與b偏移，如轉態點a偏移至_230uA，而轉態 點b偏移至210uA，而無法得到所要的遲滯特性曲線。 【發明内容】 本發明係提供一種具有遲滯特性之電流比較器，以解決 f 上述之問題。 本發明係揭露一種具有遲滯特性之電流比較器，其包含 、一第一電流比較單元，用以比較一第一參考電流以及一輸 1244264 入電流，以及據以輸出一第一電壓，一第二電流比較單元， 用以比較一第二參考電流以及該輸入電流，以及據以輸出 一第二電壓，以及一控制電路，連接於該二電流比較單元， 用來根據該二電流比較單元輸出之電壓產生一輸出電壓或1244264 IX. Description of the invention: [Technical field to which the invention belongs] The present invention provides a current comparator with a hysteresis characteristic, in particular-a current comparator with a hysteresis characteristic curve that can define the transition point. [Prior art] Please refer to Fig. 1. Fig. 1 is a circuit diagram of a conventional current comparator 10 having a hysteresis characteristic. The current comparator 10 includes five NMOS transistors M2, M5, M5, M6, and M8, and three PMOS transistors M3, M4, and M7. Transistor M1 is connected to the gate of M2, and the two transistors are driven by the turn-in voltage of node N1 through the gate. The transistors M5 and M6 in the current comparator 10 are current sinks, and the wheel-in voltage of node N2 passes the gate to drive the two transistors. The drains of the transistors M1 and M3 are connected to the nodes N3, respectively. In addition, the node N3 connected to the drains of the transistors M1 and M3 is also connected to the gates of the transistors M3 and M4. Similarly, the drains of the transistors M2 and M4 are connected to the nodes. In addition, the node N4 of the drains of the transistors M2 and M4 is connected to the gates of the transistors 1244264 and M7 and M8. In addition, the currents are nodes N5 and N6, respectively. The two input terminals of Yabei and Chera0 are connected to the transistor ⑷ and ⑽, and the output terminals of the current comparator Η) are connected to Section two: The poles are respectively connected to the drain of the electric one ^ = two _ and the voltage source, the transistor ^ y is connected to the point N5, and the source of the transistor pair is connected to the node dove. In the figure: node N5 receives the turn-on current η, and node N6 receives a test current 12. Please refer to Figure 2, Figure 2 is the first! The current / voltage diagram of the circuit, transistors M7 and M8 and reference current 12 are used to control the magnitude of the hysteresis characteristic curve of the current comparator ι〇. Please refer to the figure again. When the output voltage ▽ _ is low, the transistor 7 will be activated, and the transistor 7 will output the current Im7 to node N5. On the other hand, the input current n will also flow into node N5 to make the current The comparator 10 changes the state of the output voltage vout. At this time, the output voltage Vout is _2 \ / ((11 + ^)-12), and the value of (ii + iM7) -I2 must be negative to change the output voltage vout to be the voltage. Conversely, when the output voltage is high, transistor M8 will be activated, and transistor M8 will output current IM8 to node N6. On the other hand, reference current 12 also flows into node N6, so that pen comparator 10 changes the output voltage Vout. status. At this time, the output voltage Vout is -Zv (I1- (I2 + Im8)), and the value of I1_ (I2 + Im8) must be positive to change the output voltage ν. ^ Is low voltage. 1244264 Because when the transistor M7 is turned on and (Π + IM7) -II2 is negative, the output voltage will transition from a low voltage to a high voltage, that is, the output voltage Vout transitions at the transition point a. Conversely, when transistor M8 is turned on and I1- (I2 + IM8) is a positive number, the output voltage will transition from a high voltage to a low voltage, that is, the output voltage VQUt transitions at the transition point b. Therefore, the positions of the transition points a and b in Fig. 2 are controlled by the transistors M7 and M8, respectively. However, transistors M7 and M8 are components with different polarities, transistor M7 is a PMOS transistor, and transistor M8 is an NMOS transistor. In the manufacturing process, it is difficult to control the parameter drift of the transistors M7 and M8. Consistency to control the positions of the transition points a and b in the hysteresis characteristic curve, which causes the output of the current comparator to be incorrect. For example, suppose the required hysteresis characteristic curve is zero reference current 12 and the transition points a and b are -200uA and 200uA hysteresis characteristic curves, respectively. However, some process changes or differences in the process may cause the hysteresis characteristic curve. The transition points a and b are shifted, for example, the transition point a is shifted to _230uA, and the transition point b is shifted to 210uA, and the desired hysteresis characteristic curve cannot be obtained. SUMMARY OF THE INVENTION The present invention is to provide a current comparator with hysteresis to solve the above-mentioned problems. The present invention discloses a current comparator with hysteresis characteristics, which includes a first current comparison unit for comparing a first reference current and an input current of 1244264, and outputs a first voltage and a second voltage accordingly. A current comparison unit for comparing a second reference current and the input current, and outputting a second voltage according to the current comparison unit; and a control circuit connected to the two current comparison units for using the voltage output by the two current comparison units Generate an output voltage or
根據該二電流比較單元輸出之電壓及該控制電路之前—狀 態的輸出電壓產生一輸出電壓Q 【實施方式】 明麥考第3圖’第3圖為本發明具有遲滯特性之電流比 較器20之電路圖。電流比較器2〇包含一第一電流比較單 兀22、一第二電流比較單元24以及一控制電路％。控制 電路26包含兩個N0S電晶體MN1與MN2、三個pM〇s 電晶體MP卜MP2與MP3,以及兩個反向器Invl與^。 如第3圖所示，第一 NM〇S電晶體厘犯，其閘極係連 接於第一電流比較單π 22之輸出端V1，汲極係連結於— 第一節點第二NMOS電晶體MN2，其開極係連接於 第二電流比較單元24之輸出端V2，汲極係連接於第— NMOS電晶體MN1之源極，源極係連接於接地端。而第一 Ρ Μ Ο S電晶體μ p丨，其閘極係連接於第二電流比較單元2 4 之輸出端V2，汲極係連接於第一節點ρι，源極係連接於 -電壓源Vdd。第二_S電晶體MP2，其閘極係連接於 1244264 第一電流比較單兀22之輸出端乂丨，汲極係連接於第一節 點P1。第三PMOS電晶體MP3,其汲極係連接於第二pM〇s 電晶體MP2之源極，源極係連接於電壓源Vdd，閘極係連 接於控制電路之輸出端Vo。另外，第一反向器Inw，其輸 入端係連接於第一節點P1，輸出端係連接於控制電路之輸 出端Vo ’而第二反向器ιην2，其輸入端係連接於控制電路 之輸出立而Vo ’輸出端係連接於第一節點p 1。 第一電流比較單元22與第二電流比較單元24的功能相 同，兩者皆接收一輸入電流I以及一參考電流(Irefl或 Iref2) ’藉由比較此兩電流以輸出一電壓。舉例來說，當輸 入電流I小於參考電流Irefl時，第一電流比較單元22所 輸出之第一電壓VI為高電位；相反地，當輸入電流I大於 參考電流Irefl時，第一電流比較單元22所輸出之第一電 壓VI為低電位。第二電流比較單元24的運作與第一電流 比較單元22相同，因此不再贅述。 控制電路26係連接於兩電流比較單元22與24,第一電 流比較單元22輸出之第一電壓vi係控制電晶體MN1與 MP2，當第一電壓VI為高電位時，電晶體MN1導通；當 第一電壓VI為低電位時，電晶體MP2導通。同樣地，第 二電流比較單元24輸出之第二電壓V2係控制電晶體MN2 與MP1，當第二電壓V2為高電位時，電晶體MN2導通； 1244264 當第二電壓V2為低電位時，電晶體MP1導通。而電晶體 MP3係由控制電路26之輸出電壓Vo所控制。以下將詳述 電流比較器20之運作方式。 首先討論輸入電流I由小電流轉變為大電流之狀況，請 參閱第4圖與第5圖，第4圖為第3圖中電路之電流/電壓 圖，而第5圖為各點電壓之狀態表，並請配合第3圖之電 路圖。假設第一參考電流Irefl小於第二參考電流Iref2， 當輸入電流I皆小於參考電流Iref 1與Iref2時，此時兩電 流比較單元22與24所輸出之電壓VI與V2皆為高電位， 因此電晶體MN1與MN2皆為導通的。由於電晶體MN1 與MN2導通，因此第一節點P1之電壓V3係為接地電壓， 意即電壓V3為低電位。而電壓V3經由反向器Invl反向 後，控制電路26之輸出電壓Vo即為高電壓，如第4圖中 與第5圖中之狀態1。注意的是，此時電晶體MP3為關閉 的，因為輸出電壓Vo為高電壓。 接著，當輸入電流I大於參考電流Irefl，但仍小於參考 電流Iref2時，此時電壓VI轉為低電壓，電壓V2仍為高 電壓，因此僅導通電晶體MP2與MN2，而其餘電晶體 MN1、MP1與MP3為關閉的。雖然電晶體MN2導通，但 由於電晶體MN1係為關閉的，因此電壓V3並無連接至接 地端。再者，雖然電晶體MP2導通，但由於電晶體MP3 1244264 仍處於關閉狀態，且電晶體MP1也為關閉的，因此電壓 V3並無連接至電壓源Vdd。由於使用反向器Invl與反向 器Inv2，此時電壓V3應維持於前一狀態之電壓，即為低 電壓狀態，而控制電路26之輸出電壓Vo仍為高電壓。由 於電壓V3不連接於接地端，亦不連接於電壓源Vdd，此時 若有雜訊可能會使電壓V3飄移。為了確保電壓V3不會飄 移，因此使用反向器Inv2以使電壓V3仍與輸出電壓Vo 維持相反之狀態，而不至偏移。此時各電壓之狀態為第4 圖與第5圖中之狀態2。 最後，當輸入電流I皆大於參考電流Iref 1與Iref2時， 此時電壓VI與V2皆為低電位，所導通的電晶體為MP1 與MP2，而電晶體MP3仍為關閉的，因為輸出電壓Vo仍 為高電壓。當電晶體為MP1導通時，電壓V3即連接於電 壓源Vdd，電壓V3即轉變為高電壓，而同時使得控制電路 26之輸出電壓Vo也由高電壓轉態為低電壓，此時各電壓 之狀態為第4圖與第5圖中之狀態3。另外，由於輸出電 壓Vo轉態為低電壓，因此導通了電晶體MP3。 接下來，討論輸入電流I由大電流轉變為小電流之狀 況。如前所述，假設第一參考電流Irefl小於第二參考電流 Iref2，當輸入電流I皆大於參考電流Irefl與Iref2時，電 壓VI與V2為低電壓，而由於電晶體MP1導通，因此電 12 1244264 壓V3為高電壓且輸出電壓Vo為低電壓，如第4圖與第5 圖中之狀態3。注意的是，此時的電晶體MP3已被導通， 因為輸出電壓Vo為低電壓。 接著，當輸入電流I小於參考電流Iref2，但仍大於參考 電流Irefl時，此時電壓VI仍為低電壓，而電壓V2轉態 為高電壓。因此電晶體MP2導通而電晶體MP1被關閉， 但由於電晶體MP3此時仍然保持導通狀態，所以電壓V3 經由電晶體MP2與MP3的導通仍連結於電壓源Vdd，而 仍處於高電壓，如第4圖與第5圖中之狀態4。 最後，當輸入電流I皆小於參考電流Irefl與Iref2時， 電壓VI與V2皆為高電壓，而電壓V3經由電晶體MN1 與MN2的導通而連結於接地端，此時輸出電壓Vo將由低 電壓轉態為高電壓，如第4圖與第5圖中之狀態1。 依此我們得以歸納出以下的結論，控制電路26係根據 第一電流比較單元22輸出之第一電壓VI與第二電流比較 單元24輸出之第二電壓V2,以輸出一輸出電壓Vo,或根 據第一電流比較單元22輸出之第一電壓VI、第二電流比 較單元24輸出之第二電壓V2以及控制電路之前一狀態的 輸出電壓Vo，以輸出一輸出電壓Vo。 1244264 相較於先前技術，本發明先利用兩個電流比較單元22 與24之參考電流Irefl與Iref2界定出轉態點之位置Irefl 與Iref2,如第4圖所示，再結合邏輯電路（即控制電路26)， 以產生具有遲滯特性之電流比較器20。當輸入電流I由小 電流轉變為大電流且大於參考電流Iref2時，輸出電壓Vo 將由高電壓轉態為低電壓，即轉態點Iref2之處。相反地， 當輸入電流I由大電流轉變為小電流且小於參考電流Irefl 時，輸出電壓Vo將由低電壓轉態為高電壓，即轉態點Irefl 之處。本發明具有遲滯特性之電流比較器20的優點在於輸 入電流I與參考電流Irefl與Iref2可利用同類型的電流源 產生，例如可全使用PMOS電流源產生。由於輸入電流I 與參考電流Irefl與Iref2是由同類型的電流源產生，且這 三個電流源的電路佈局位置可設計的很接近，因此對於製 程參數的漂移具有較佳的一致性，可有效降低電路的遲滯 特性受製程參數漂移的影響。因此，本發明較習知技術可 輕易地控制遲滯特性曲線。 以上所述僅為本發明之較佳實施例凡依本發明申請專 利範圍，所做之均等變化與修飾，皆應屬本發明專利的涵 蓋範圍。 【圖式簡單說明】 14 1244264 第1圖為習知具有遲滯特性之電流比較器之電路圖。 第2圖為第1圖電路之電流/電壓圖。 第3圖為本發明具有遲滯特性之電流比較器之電路圖。 第4圖為第3圖中電路之電流/電壓圖。 第5圖為第3圖中電壓之狀態表。 【主要元件符號說明】 10、20 電流比較器 22 第一電流比較單元 24 第二電流比較單元 26 控制電路An output voltage Q is generated according to the voltage output by the two current comparison units and the output voltage before the control circuit. [Embodiment] Ming McCao Figure 3 'Figure 3 shows the current comparator 20 with hysteresis characteristics of the present invention. Circuit diagram. The current comparator 20 includes a first current comparison unit 22, a second current comparison unit 24, and a control circuit%. The control circuit 26 includes two NOS transistors MN1 and MN2, three pMOS transistors MP2 MP2 and MP3, and two inverters Invl and ^. As shown in Figure 3, the first NMOS transistor has a gate connected to the output terminal V1 of the first current comparison π 22, and the drain is connected to the first node, the second NMOS transistor MN2. The open electrode is connected to the output terminal V2 of the second current comparison unit 24, the drain is connected to the source of the first NMOS transistor MN1, and the source is connected to the ground. The gate of the first P MOS transistor μ p 丨 is connected to the output terminal V2 of the second current comparison unit 24, the drain is connected to the first node ρ, and the source is connected to the voltage source Vdd. . The second_S transistor MP2 has a gate connected to the output terminal 乂 of the first current comparison unit 22 and a drain connected to the first node P1. The third PMOS transistor MP3 has a drain connected to the source of the second pMOS transistor MP2, a source connected to the voltage source Vdd, and a gate connected to the output terminal Vo of the control circuit. In addition, the input terminal of the first inverter Inw is connected to the first node P1, the output terminal is connected to the output terminal Vo 'of the control circuit, and the input terminal of the second inverter Inw is connected to the output of the control circuit The Vo 'output is connected to the first node p1. The function of the first current comparison unit 22 is the same as that of the second current comparison unit 24. Both of them receive an input current I and a reference current (Irefl or Iref2) 'to output a voltage by comparing the two currents. For example, when the input current I is less than the reference current Irfl, the first voltage VI output by the first current comparison unit 22 is high; on the contrary, when the input current I is greater than the reference current Irfl, the first current comparison unit 22 The output first voltage VI is a low potential. The operation of the second current comparison unit 24 is the same as that of the first current comparison unit 22, and therefore will not be described again. The control circuit 26 is connected to the two current comparison units 22 and 24. The first voltage vi output by the first current comparison unit 22 is a control transistor MN1 and MP2. When the first voltage VI is high, the transistor MN1 is turned on; When the first voltage VI is low, the transistor MP2 is turned on. Similarly, the second voltage V2 output by the second current comparison unit 24 is the control transistor MN2 and MP1. When the second voltage V2 is high, the transistor MN2 is turned on; 1244264 When the second voltage V2 is low, the voltage is The crystal MP1 is turned on. The transistor MP3 is controlled by the output voltage Vo of the control circuit 26. The operation of the current comparator 20 will be described in detail below. First discuss the situation where the input current I changes from a small current to a large current. Please refer to Figure 4 and Figure 5, Figure 4 is the current / voltage diagram of the circuit in Figure 3, and Figure 5 is the state of the voltage at each point Table, and please match the circuit diagram in Figure 3. Assume that the first reference current Irefl is smaller than the second reference current Iref2. When the input current I is smaller than the reference currents Iref 1 and Iref2, at this time, the voltages VI and V2 output by the two current comparison units 22 and 24 are both high potentials. The crystals MN1 and MN2 are both on. Since the transistors MN1 and MN2 are turned on, the voltage V3 of the first node P1 is a ground voltage, which means that the voltage V3 is a low potential. After the voltage V3 is inverted through the inverter Invl, the output voltage Vo of the control circuit 26 becomes a high voltage, such as state 1 in Figs. 4 and 5. Note that the transistor MP3 is turned off at this time because the output voltage Vo is high. Then, when the input current I is larger than the reference current Irfl, but still smaller than the reference current Iref2, the voltage VI turns to a low voltage and the voltage V2 is still high. Therefore, only the crystals MP2 and MN2 are turned on, and the remaining transistors MN1 and MN1 MP1 and MP3 are closed. Although transistor MN2 is turned on, since transistor MN1 is turned off, voltage V3 is not connected to the ground terminal. Furthermore, although transistor MP2 is on, since transistor MP3 1244264 is still off and transistor MP1 is also off, voltage V3 is not connected to voltage source Vdd. Since the inverters Invl and Inv2 are used, the voltage V3 should be maintained at the voltage of the previous state, that is, the low voltage state, and the output voltage Vo of the control circuit 26 is still high. Since the voltage V3 is not connected to the ground terminal or the voltage source Vdd, if there is noise, the voltage V3 may drift. In order to ensure that the voltage V3 does not drift, an inverter Inv2 is used so that the voltage V3 is still maintained in the opposite state to the output voltage Vo without being shifted. At this time, the state of each voltage is state 2 in Figs. 4 and 5. Finally, when the input current I is greater than the reference currents Iref 1 and Iref2, then the voltages VI and V2 are low, and the transistors that are turned on are MP1 and MP2, while the transistor MP3 is still off because the output voltage Vo Still high voltage. When the transistor MP1 is turned on, the voltage V3 is connected to the voltage source Vdd, and the voltage V3 is changed to a high voltage. At the same time, the output voltage Vo of the control circuit 26 is also changed from a high voltage to a low voltage. The state is state 3 in FIGS. 4 and 5. In addition, since the output voltage Vo transitions to a low voltage, the transistor MP3 is turned on. Next, the case where the input current I changes from a large current to a small current is discussed. As mentioned above, assuming that the first reference current Irefl is smaller than the second reference current Iref2, when the input current I is larger than the reference currents Irfl and Iref2, the voltages VI and V2 are low voltage, and because the transistor MP1 is turned on, the voltage 12 1244264 The voltage V3 is a high voltage and the output voltage Vo is a low voltage, such as state 3 in FIGS. 4 and 5. Note that the transistor MP3 is turned on at this time because the output voltage Vo is low. Then, when the input current I is smaller than the reference current Iref2, but still larger than the reference current Iref1, the voltage VI is still low and the voltage V2 is changed to a high voltage. Therefore, the transistor MP2 is turned on and the transistor MP1 is turned off, but since the transistor MP3 is still turned on at this time, the voltage V3 is still connected to the voltage source Vdd through the conduction of the transistor MP2 and MP3, and is still at a high voltage, as Figure 4 and state 4 in Figure 5. Finally, when the input current I is less than the reference currents Irfl and Iref2, the voltages VI and V2 are both high voltages, and the voltage V3 is connected to the ground terminal through the conduction of the transistors MN1 and MN2. At this time, the output voltage Vo will change from the low voltage The state is high voltage, such as state 1 in Figures 4 and 5. Based on this, we can conclude the following conclusion. The control circuit 26 outputs an output voltage Vo according to the first voltage VI output by the first current comparison unit 22 and the second voltage V2 output by the second current comparison unit 24, or according to The first voltage VI output by the first current comparison unit 22, the second voltage V2 output by the second current comparison unit 24, and the output voltage Vo of the previous state of the control circuit to output an output voltage Vo. 1244264 Compared with the prior art, the present invention first uses the reference currents Irefl and Iref2 of the two current comparison units 22 and 24 to define the positions of the transition points Irefl and Iref2, as shown in FIG. 4, and then combines the logic circuit (ie control Circuit 26) to generate a current comparator 20 with hysteresis. When the input current I changes from a small current to a large current and is greater than the reference current Iref2, the output voltage Vo will transition from a high voltage to a low voltage, that is, at the transition point Iref2. Conversely, when the input current I changes from a large current to a small current and is smaller than the reference current Irfl, the output voltage Vo will transition from a low voltage to a high voltage, that is, at the transition point Irfl. The current comparator 20 with hysteresis of the present invention has the advantage that the input current I and the reference currents Irfl and Iref2 can be generated using the same type of current source, for example, they can be generated using all PMOS current sources. Since the input current I and the reference currents Irfl and Iref2 are generated by the same type of current source, and the circuit layout positions of the three current sources can be designed very close, it has better consistency for the drift of the process parameters and can be effective Reducing the hysteresis of the circuit is affected by process parameter drift. Therefore, the present invention can easily control the hysteresis characteristic curve compared with the conventional technique. The above description is only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the present invention should fall within the scope of the patent of the present invention. [Schematic description] 14 1244264 Figure 1 is a circuit diagram of a conventional current comparator with hysteresis. Figure 2 is the current / voltage diagram of the circuit of Figure 1. FIG. 3 is a circuit diagram of a current comparator having a hysteresis characteristic according to the present invention. Figure 4 is a current / voltage diagram of the circuit in Figure 3. Fig. 5 is a state table of the voltage in Fig. 3. [Description of main component symbols] 10, 20 Current comparator 22 First current comparison unit 24 Second current comparison unit 26 Control circuit
Invl、Inv2 反向器 MN1、MN2 NMOS 電晶體 MP1、MP2、MP3 PMOS 電晶體 M3、M4、M7 PMOS 電晶體Invl, Inv2 inverters MN1, MN2 NMOS transistors MP1, MP2, MP3 PMOS transistors M3, M4, M7 PMOS transistors
Ml、M2、M5、M6、M8 NMOS 電晶體 Nl、N2、N3、N4、N5、N6、P1 節點 15Ml, M2, M5, M6, M8 NMOS transistors Nl, N2, N3, N4, N5, N6, P1 node 15