TWI244192B - Input/output buffer - Google Patents

Abstract

An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.

Description

1244192 V. Description of the invention (1) " '--- The technical field to which the invention belongs ^ The present invention relates to an input / output buffer', especially to a pressure input / output retarder, which can be accepted higher than System Voltage Prior Art ^ Traditionally most 1 c devices are powered by a 0 to 5 volt system 2:. f In these Ic devices, the signal of the high voltage level is set to "= The signal of the voltage level is set to ground ... And, = the progress of the technology, because the gate oxide layer in the IC device has become low = low糸 ΐ Voltage can be reduced to 3.3 volts, and may be lower in the future ;, :: lower. However, 'practically a new installation of 3.3 volts :: ΐ with peripheral circuit of Γ volts. For example, in -Personal Electricity Month 1 is used for a 3.3 volt VGA card system, which is always on. Therefore, there will be problems between 'applicable to 3.3 volt lc devices and sales ICs.', B Figure 1 It is a schematic diagram showing the circuit structure applicable to a 33 volt 2: I / 〇r buffer 14. As shown in the figure, the I / O buffer 2 set 4 is coupled to an input buffer 16 and a 1 (: Device ... 14 The I / O buffer 14 is composed of a first circuit, a second electric_δ20, a crystal P1 and a NMOS transistor N1. In the PMOS electric input mode, PMOS The transistor P1 and the ^ B body of the transistor are in an on state. In order to do so, the circuit 10;: == 入 不 导 ##, such as 3.3V 'to PM〇s transistor p gate: level of electricity Wear locking member while the second circuit 12 will be: Low =

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1244192 V. Description of the invention (2) No. 'for example 0V, to the gate of NMOS transistor N1, so that the surface transistor is turned off. However, if the bonding potential 2 Π d / r 2: ,, r Tr receives a 5V input signal, the gate voltage of the PMOS transistor P1 is 3.3V, and the electrode voltage is 5V, and the source is 3.3V. Since the closed-circuit voltage (33v) of the PMOS transistor P1 is lower than its drain voltage (5V), this drain voltage will cause the pMOS transistor to enter the reverse conduction path. Furthermore, because in general, the PMOS transistor is formed on an n-type substrate, and its passive source is a P-type, a-contact is formed between the passive and source_well regions 19.面 二 极 体 18。 Surface diode 18. And the drain of the crystal is coupled to the bonding pad 20, and now receives an input signal (5V) higher than the system voltage, and its substrate is connected to a system voltage of 3.3V, this junction diode 18 will The forward bias causes an unnecessary large current between the external 5V voltage source and the internal 3.3V voltage source. In order to solve the above problems, U.S. Patent No. 6,011,409 discloses an I / O buffer suitable for 3.3V. Figure 2 is a schematic diagram of another conventional 1/0 buffer 30, which is suitable for receiving an input voltage higher than the system voltage. When the I / O buffer 30 is operated in the input mode, both the pMOS transistor P5 and the NMOS transistor N1 enter a non-conducting state. In addition, the control signals TN = 0 (〇V) and / ΤΝ = 1 (3 · 3ν) will be transmitted to the 1 / 〇 buffer 30 'to turn off the NMOS transistor N3 and turn on the nmOS. Transistor N5. Therefore, if the signal on the I / O bonding pad 32 is 5V, it will be transmitted to the foreign-type N-type well region 36 through the pMos transistor P1, so that the floating n-type well region 36 is set to 5V. When the signal on the I / 〇 pad 3 2 changes from 5 v to 0 v, the PMOS transistor P1 will be turned off. At this time, since the NMOS transistor N2 and μ are turned on,

0697-10222TWF (nl); P2003-011; DENNIS.ptd Page 6 1244192 V. Description of the invention (3) = ϊ ΐ The system that puts the gate of transistor P2 so that the N-type transistor is installed in the transistor The voltage can be transported to the sub-type N-type ascending region 3 6 through # _ guess 2, # 提 没 止 μ% 丨 from ^ 3 3V., T makes the sub-type N-type well region 36 be set at 夂, Therefore, it is possible to avoid unnecessarily large buffers that need to be controlled by the two external numbers TN, / TN from the internal circuit ('丨 1 *. Second, but this I / O buffer is slightly longer than I). The floating D-type well area 36b = 1 / the control circuit is more complicated and needs to take t ^ a potential to less than 3.3V, so that the invention content-occupies a larger chip area. In view of this, the primary purpose of the present invention is to generate no when receiving an input voltage higher than the system voltage; 2: 1: electricity according to the above purpose to avoid unnecessary leakage currents. According to the above purpose (I / O), the circuit includes a first invention. The invention provides an I / 0 buffer, which can avoid and does not require external control information from the core circuit in the I / O buffer of the invention. · PM0δ transistor, a first-off 08 transistor = = second NMOS transistor. The 1/0 circuit has a cymbal pass! = To join 塾. The 刚 -gang S transistor has a floating manhole area, and J 2 is the transmission end: the first NMOS transistor has-gate:-a gate control t or. A P-type gate control circuit is used to pass γ- ~~: gate f control signal to the gate of 苐 -PM0S transistor. -Feedback and Betty are transferred between the transmission end and the -N control circuit in the well area, and are used for: the voltage on the pad to output a feedback signal. One W = 1/0 is used to control the two electric two according to the feedback signal from the feedback Wei test device ^

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1244192

The potential on the N-well area of the crystal. When the I / 〇 buffer operates in the input mode, the input 1 on the transmission side says the right horse b V (in the 3 · 3 V system), the door is a 0V EM γ ^ ^) back The detection and detection side device will output 1 υ ν day 1 u crossover to ν well area control Lei Yi P M 0 S Lei Yue Ban Xi μ Pu Jing area control circuit will be the PM0S electric power body N well. If the voltage on the potential adjustment on the area changes from 5V to 0V (below 3 ^ ^ p and more transmission and F closes the input voltage of a gamma two Γ system voltage), the feedback detection side clothing 罝 θ I will produce a The feedback of 5 V is used in the control circuit of the second well area of the North Road, m, and the control circuit of the N well area will be a PM0s transistor-type well area. QQ Τ /, I—, The potential is from Zhou Yu to the system MC3 · 3V). Therefore, 1/0 buffers the crying stream. Inverse Γ ° σ Γ to avoid unnecessary leakage power is more obvious and easy to understand. For detailed description, in order to make the above-mentioned objects, features and advantages of the present invention, a preferred embodiment is given below, and in conjunction with the attached drawings: The third figure of the embodiment is the 1/0 buffer 100 of the present invention-a schematic diagram of this 1/0 buffer state 1 0 0 is capable of receiving input higher than the system association # 厌 vrv ππ π system voltage v CC signal. In this embodiment, the system voltage is taken as an example of 3 · 3V, and the input signal is switched between οV and 5V ', but it is not intended to limit the present invention. As shown in Figure 3, the 1/0 buffer includes a 1/0 circuit 14 and 1? A type interrogation control circuit 120, an N-well area control circuit 130, and a feedback detection device. In this embodiment, the feedback detection device may be an inverter INV1. The I / O circuit 140 includes a pMOS transistor pi, two NMOS transistors N1, N2 ', and has a 1/0 transmission terminal 132, which is coupled to the I / O bonding pad. PM0S electricity

0697-10222TWF (nl); P2003-011; DENNIS.ptd Page 8 1244192 V. Description of the invention (5) '---- The crystal P1 has a floating N-type well region VNW, and a drain as 1 / 〇 The I / O transmission end 132 of the circuit ljO. The gate of the NM0s transistor N1 is used to receive a first gate control signal NG, and the NM0S transistor N2 has a source and a drain, which are respectively coupled to the I / O bonding pads 11 and 03. The drain of transistor N1 and a gate are coupled to the system voltage VCC. The P-type gate control circuit 12 is coupled between a second gate control signal PG and the PMQS transistor Pi to transmit the second gate control signal ^ the gate of the PM0S transistor Pi. Inverted · ΙΝνι, which is coupled between the 1/0 transmission terminal 132 and the N-well area control circuit 13〇, its input terminal is coupled to the 1/0 transmission terminal 132, and its output is coupled to the N-well area control circuit 13 〇. inverter

According to the input voltage on the I / O junction 塾 110, a feedback signal SF is output to the N-N well area control circuit 130. The N-well area control circuit 30 adjusts the potential of the floating n-type well area VNW of the PMOS transistor based on the feedback signal SF output from the inverter INV1. When the I / 〇 buffer 100 is operated in the input mode, the first gate control signal NG will be in a low voltage state, so the NMOS transistor N1 will be turned off. At the same time, the two gate control signal PG will be in a high voltage state, so the PM0s transistor is turned off. If the input signal at the transmission end 132 is higher than two:; voltage), the inverter INV1 will output a 0V feedback signal to the N-well area control circuit 130, and the N-well area control circuit 13 will send pM The potential on the VNW of the \ -type well region of the 0s transistor is adjusted to 5V. In addition, if the voltage at the transmission end 132 changes from 5 V to 0 V (less than the 3 · 3 V system voltage), the inverter j Nv 丨 will output a 5V feedback signal to the N-well area control circuit 130, n The well area control circuit 13 will adjust the potential of the N-type well area VNW of the PM0S transistor P1 to the system voltage.

1244192 — 丨 丨 丨 丨 V. Description of the invention (6) 'er ----(3 · 3V). Therefore, the 1 / () buffer can avoid unnecessary leakage current. Therefore, the 1 ^ 0 buffer of the Ming can receive an input voltage signal higher than the system voltage, and an external control signal is required to avoid unnecessary leakage current. Fig. 4 shows the circuit structure of the I / 0 buffer of the present invention. As shown in FIG. 4, the 1/0 buffer 100 includes six PM0S transistors P1 to P6, five NMOS transistors N1 to N5, and an inverter INV1, which is composed of a pM0s transistor P7 ^ one NMOS It consists of transistors N6 and N7. In addition, the 1 / 〇 buffer 100 is connected via a 1/0 transmission end 132 to a bonding pad 1 1 of a 1C device (not shown), and the I / O buffer 100 is operated by two Controlled by each gate control signal NG, PG. ^ In this embodiment, the I / O circuit 140 is composed of a PMOS transistor P1 and NMOS transistors N1 and N2. In the I / O circuit 140, the NMOS transistor N1 has a gate which is connected to a gate control signal NG, a source to ground, and a drain. The NMOS transistor N2 has a gate coupling system voltage vcc, a source coupled to the drain of the NMOS transistor \ 1, and a drain coupled to the I / O bonding pad through the 1/0 transmission end 132. 10 . The PM0S transistor P1 has a floating N-type well area, a gate coupled to node B, a source coupled to the system voltage vcc, and a pole coupled to the I / O through the I / O transmission terminal 132. Bonding pad 丨 1〇. The N-well control circuit 130 is composed of NMOS transistors N3, N4, and PMOS transistors P2, P3, and P4. In the N-well control circuit 120, the NMOS transistor N3 has a gate coupled to the pMOS transistor P7 and the drain of the NMOS transistor N6, a source grounded, and a drain. The NMOS transistor N4 has a gate coupling system voltage VCC, a source coupled to the drain of the NMOS transistor N4, and a drain coupled to the node A. PM0S transistor P2 has a gate coupling system voltage

0697 · 10222TW (η 1); P2003 · 011; DENNIS · ptd Page 10 1244192 V. Description of the invention (7) VCC, a source coupling is formed on a floating well on the board of an IC device (not shown) The region vm-drain is connected to the 1/0 bonding pad 1 1 0 through the I / G transmission terminal 13. PMOS transistor P3 #Carp pile at τ / n 4 Liren & 0 you are coupled to 丨 / 〇 pad and node A] 9 ', with -gate_connect system voltage vcc, -source by I / O transmission end 1 3 2 consumes I / 〇 pad 1 1 〇, and a

And, the and pole are coupled to the node A. The PMOS circuit has a gate connected to node a, a drain connected to the system voltage \ CC, and a source connected to the floating n-type well area vnw. Furthermore, in this example, the P-type Gate control circuit 120 is composed of PM0S transistor 5, P6 and NMOS transistor N5. In p-type gate control circuit 12 (), NMOS transistor N5 and PMOS transistor P5 form a transmission gate, NM. s transistor N5 has a gate coupling system voltage vcc, and a drain / a source are respectively connected to the gate control signal PG and node B. The pM0s transistor has a gate connected to node A ' And one pole / one source is connected to the closed pole control signal PG and node B respectively. PM0S transistor p6 has a pole coupling system voltage VCC, one pole is connected to node β and the source is connected to floating. The n-region VNW. The inverter INV1 has an input terminal coupled to the 1/0 transmission terminal 132 and an output terminal coupled to the N-well control circuit 30. The inverter INV1 is composed of a pMOS transistor P7 and an NMOS transistor. N6, N7. In the inverter INV1, the pM〇s transistor P7 has a gate system which is coupled to the 1/0 bonding pad 110 by the NMOS transistor N7. A source is coupled to the system voltage VCC and a drain is coupled to the gate of the transistor 0 / transistor N3. The NMOS transistor N6 also has a gate coupled to the I / O bonding pad through the transistor N7 11〇, a drain is coupled to the gate of the transistor core, and a source is grounded. NMOS transistor N7 is coupled to 1/0 transmission 0697-10222TW (nl); P2003-0ll; D ^ IS.ptd Page 11 1244192____ V. Description of the invention (8) " One "-Between terminal 1 32 and PMOS transistor P6, NMOS transistor N6, there is a gate coupling system voltage VCC, and a source Pole / one sink are respectively coupled to 1 / 〇 transmission

The terminal 132 is connected to the gate of the PMOS transistor P6 and the NMOS transistor N6. And the floating N-type well region VNW is connected to the substrate forming all the PMOS transistors pl ~ p5. When the I / O buffer 100 is operated in the input mode, the gate control signal ... will be in a low voltage state, so the NMOS transistor N1 will be turned off. At the same time, the gate control signal pg will be in a high voltage state, so the PM0S transistor P1 will also be stopped. ς If the input signal at the transmission end 132 is 5ν (higher than the 3 · 3ν system voltage), the voltage on the gate of the PMOS transistor P2 is 3.3V, which will be lower than the source connected to the I / O transmission end 132 5V voltage on the pole, so the PMOS transistor P2 will be turned on, and the 5V voltage will be transferred to the floating v-well region VNW, so the floating N-well region VNW will be adjusted to a potential of 5V. In addition, the inverting EINV1 will output a feedback signal SF to the OFF transistor N3 based on the 5V input signal, so the NMOS transistor N3 will be cut off, and the 5V input signal will be transmitted to the PMOS transistor through the pmos transistor P3. The crystals P4 and P5 cause the PMOS transistors P4 and P5 to stop. When the voltage on the transmission end 1 3 2 changes from 5 V to 0 V, the PMOS transistors P2 and P3 will be cut off, and the inverter INV1 will output a 5V feedback signal SF to the NM0S transistor based on the 0V input signal. N3, so the NMOS transistor N3 will turn on. At this time, the node A will be grounded (0V), so by the conduction of the PMOS transistor P4, the system voltage v CC will be transmitted to the floating N-type well area VNW, so that the floating N-type well area VNW is adjusted to 3 3V. Therefore, it is possible to avoid unnecessary leakage current in the conventional 1/0 buffer, and no external control signal is needed.

0697 · 1 〇22OTF (n 1); p thin _ 〇 丨 丨; DENNI sptd Page 12 1244192 V. Description of the invention (9) In addition, when the I / O buffer 100 operates in the output mode, the 1/0 buffer state 1 00 will output a signal of a low voltage level (LOW logic) or a signal of a high voltage level (HIGh 10gic) according to the gate control signals ^^ 1 G, pG. For example, when the gate control signals are all low logic level (L 0w logic), the pmos transistor pi is turned on and the NMOS transistor N1 is turned off to output a high voltage signal (HIGH logic). signal. At this time, the PM0S transistor P1 will not be affected by the transistors P2, p3, p6, N3, and ㈣, and the inverter INV1. On the other hand, when the gate control signals are all at a high logic level (HIGH loglc), the PM0S transistor P1 will be turned off and the NMOS transistor N1 will be turned on to output a low voltage signal (L0w 1〇gic )signal of. Therefore, in the input mode, the I / O buffer 100 can accept an input signal higher than the system voltage without using an external control signal? Tiger can avoid unnecessary leakage current. The I / 0 buffer is 100 and can output a correct output signal according to the gates NG and PG in the output mode. Figure 5 is a schematic waveform diagram showing node A and floating N-type well area Λ. Electric 纟. The curve II shows that the I / O buffer with feedback control in the present invention is medium, and the potential on the N-type well area is set. The curve C2 is a floating I / O buffer without feedback control, and the floating N Potential on the type well area: The post-C3 series shows the f! Potential in the ㈤ buffer with feedback control in the present invention. The curve C3 shows the potential of "0" and "buffering two" without feedback control. Figure 6 is a schematic diagram of the waveform for display.亍 V〇 Potential at the transmission end. The curve C5 shows the potential at the 1/0 transmission end in the 0 1/0 buffer in the present invention, and the curve C6 shows; the potential at the transmission end in the 1/0 buffer of the feedback control. have

0697-10222W (nl); P2OO3-011; DENNIS.? Td Page 13 1244192_, V. Description of the invention (10) · As shown in Figure 6, in the output mode, the present invention with feedback control I / In the O buffer, the output signal will drop faster than the I / 0 buffer without feedback control, that is, the I / 0 buffer of the feedback control of the present invention will be faster than that without the feedback control. The I / 0 buffer has better performance. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the patent application.

0697-10222TWF (η 1); P2003-Oil; DENNIS.ptd Page 14 1244192 Simple illustration of the diagram ^ Figure 1 shows the circuit structure of a conventional I / 0 buffer suitable for a 3.3V IC device . Fig. 2 is a schematic diagram of another conventional I / 0 buffer. Fig. 3 is a schematic diagram of an I / 0 buffer according to the present invention. Fig. 4 shows the circuit structure of the I / 0 buffer of the present invention. Figure 5 is a schematic waveform diagram showing the potentials at node A and the floating N-type well area. Figure 6 is a schematic waveform diagram showing the potential on the I / 0 transmission end. Explanation of symbols Conventional technology 10: First-circuit; 12: Second and second circuit; 14, 30: I / 0 buffer 16: Input buffer; 18: Junction diode; 19: N-type well area, 2 0 3, 2: bonding pads, 3 6: floating N-type well area; / TN, TN: I / O control signals; P1, P6, N; 1 ~ N6: M0S transistor; 140: I / O circuit of the present invention 1 2 0: P-type gate control circuit;

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Claims (1)

/ 、、 Exploring profit margins; an input / output buffer (I / 0 buffer), driven by a system% Μ, including: -NM (^ / output (Μ) circuit, including-第- ⑽ ”crystal and a J JMOS transistor, the 1 / 〇 circuit has a transmission end lightly connected to a 1 / 0th :, wherein the first NMOS transistor has a gate for receiving a :: Control signal 'and the above-mentioned pM0s transistor has a drain as the above-mentioned transmission end, and an N-type well area. The top-type second-type control circuit uses the two dedicated output-the second intermediate-pole control signal to load the first PMOS transistor gate; a feedback detection device with an input terminal coupling: according to one of the above-mentioned junctions input voltage root: 1 well area control circuit & coupled to the p-type gate control circuit For the above-mentioned feedback signal of the above-mentioned feedback debt measuring device, the potential on the n-type well area of the Γ PMOS transistor is applied. Mystery 2. Input / round out as described in the first item of the scope of patent application Slow: When the above input voltage exceeds the system voltage, the control circuit of the upper well area will reduce the potential of the The potential of the input voltage is positive to J. 3. The input voltage of the N-well area control circuit in the input / roundout described in item 2 of the patent application range is lower than the above-mentioned input voltage. The potential on the well area = the potential of the system voltage. The force is up to the above 4. Input / round out buffer as described in item No. of the scope of patent application, which is 1244192 Queen No. 9213237R Sixth, the scope of patent application Λ_Ά Modification: t, 丨 / 〇 circuit further includes a second NMOS transistor with one and-open pole ^ connected to the drain of the 505 transistor and the above-mentioned bonding pads, A 1 桎 is coupled to the above system voltage. 5. If the scope of the patent application In the fourth item, the control circuit of the above-mentioned N-well area includes: Hande, its crystal / type-well = electricity Y 'has a source lightly connected to the first PMOS electrical surface and connected to the bonding pad 1 pole. The above system power, and the -75m ^-PMOS transistor, has a gate coupled to the above-mentioned f * voltage, a source lightly connected to the above-mentioned bonding pads, and '' no pole; * H system power Repeat 'a fourth PMOS transistor, and the drain of the ancient crystal, _ a The first electrode is coupled to the third voltage region; ^ The original electrode is lightly connected to the first-timer transistor to form a third NMOS transistor with the above-mentioned feedback signal of a test circuit, from the above-mentioned feedback source. Connected to the above third_electrical =, is the pole connected to the above-mentioned system electricity, the above-mentioned fourth 卩 _transistor is closed]: the source of the body 'and-the non-polar coupling 6 · As in item 5 of the scope of patent application The P-type gate control circuit includes: an input / output buffer described above, a transmission gate having a fifth body, wherein the fifth NMOS transistor if crystal and a fifth PMMOS transistor control Signal, a drain is coupled on = yes-the source is coupled to the second gate and an open-pole is coupled to the gate of the f-PM0S transistor, with the fifth PMOS transistor having a page 18 0697-10222HVFl (nl); P2003-011; DENNIS.ptc 1244192 Amendment No. 92132375 VI. Patent application scope 3 f 2 Connect the above-mentioned second gate control signal, and the drain is coupled to the above-PMOS anode and gate And a gate coupled to the drain μ of the third PMOS transistor, and a sixth PMOS transistors, all of which are on the previous, tt # 士 /, there is a gate coupled to the above system voltage, and a pole is coupled to the first pMOS transistor nununn ^ the gate of the body, and a The source is coupled to the upper region. The source of the four PMOS transistors and the input / output buffer described in item 1 of the range 1 = 2 in the n-type well of the first response transistor above. A. The feedback detection circuit is an inverter. . 8 · The input / output buffer described by the 7th, +, China, +, g 4 1 member of the scope of patent application, the above-mentioned inverter includes: a sixth NMOS transistor, which has a ^, There is a grounded source, and a drain is coupled to the gate of the third NMOS transistor; a seventh PMOS transistor is ancient ^ ^, and a source is coupled to the above system The voltage, 乂, and 〆 are connected to the drain of the sixth NMΓΚΦ mentioned above, and a seventh NMOS transistor, and the ancient "_. T ^ ^ ^ has a gate coupled to the above. A system voltage, a drain electrode is coupled to the above-mentioned bonding pads, and a source electrode is coupled to the sixth NMOS electric solar body and the gate of the seventh PMOS transistor. The input / output buffer (I / O buffer) includes: a floating N-type well area; # a first NMOS transistor, which is an ancient «a ^ ^ chip, with a gate coupled to a first gate Control ^ 5 tiger 'and a source ground;' a first 'an NMOS transistor, and the right one / ^ has a gate coupled to a system voltage, one The source side is connected to a bonding pad, and the first and the second% MOS are connected to the above first NMOS transistor. Page 19 0697-10222TWFl (nl); P2003-011; DENNIS.ptc 1244192 6. There is no pole in the scope of patent application; an inverter is provided at the end, which has an input terminal lightly connected to the above-mentioned bonding pad, and-input two NMGS transistors, which has a _ gate electrode # connection terminal, and a source ground; A 4W wheel is a fourth NMOS transistor, which has a crystal and a Fentor P; ^ Pe α has / the original pole surface is connected to the drain of the third NMOS circuit, and a gate is coupled to the system voltage A first PM0S transistor, and the first right, the towers are lightly connected to the system voltage from the source, and a drain electrode is coupled to the bonding pad; and a second PM0S transistor has- The source is lightly connected to the above-mentioned bonding pad, one is repeatedly charged, and the other is light-connected to the floating N-type well gate to be coupled to the above-mentioned system voltage region; a source is coupled to the above-mentioned bonding pad, and one and one are drain-coupled The gate-connected raNMOS circuit has a gate coupled to the third pMOS circuit and a source surface. A third PM0S transistor gate is coupled to the source of the system voltage crystal; a fourth PM0S transistor crystal is drained, and a drain is coupled to the floating N-type well area of the system voltage; A transistor with a fifth stage and a so-called "transistor" = the fifth transistor has-the source-the second gate control (5), a drain coupled to the first PM0S transistor The gate is coupled to the system voltage. The above iPM0s transistor has a source coupling—the first gate control signal, and a drain coupled to the gate of the first pMOS transistor. And a gate coupled to the drain of the third PM0S transistor; page 20 0697-10222TWFl (nl); P2OO3-〇n; DENNIS.ptc 1244192 And == MOS transistor, which has a gate electrode—the above is a drain coupled to the first PM0S transistor; described above = the fourth pM0sJ crystal of the transistor = it is called A A A \ Type well area is electrically connected to the substrate forming the first to sixth PM0S solar cells. 1 0 · If the scope of patent application for the q library office, +, where the inverter includes the input / output buffer of 34, the drain coupling = the sixth NMOS transistor 'has-source ground, and connected to the above A gate of three NMOS transistors; a seventh PMOS transistor having and a drain coupled to the sixth gate; a seventh NMOS transistor having a drain coupled to the bonding pad; and a crystal and a seventh The gate and source of the PMOS transistor are coupled to the system voltage and the drain of the transistor; and a gate is coupled to the system voltage, and a source is lightly connected to the sixth NMOS circuit.