1244188 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種異方性導電膜層的形成方法及結 構:尤指-種適用於細間距覆晶封裝（間距小於4〇微米） 5之兴方性導電膜層的形成方法及結構。 【先前技術】 目前半導體元件微小化的發展迅速，使得其閘極寬度 已可縮小至U)〇nm以下，傳統以錫鉛凸塊接合㈣der 1〇 bump)為王的覆晶封裝技術已經無法滿μ求，必須發展 新的封裝技術。尤其當晶片的輸出入接腳間的間距進一步 地縮小至50微米以下時，現有覆晶基板製程中所使用的锡 Γ塊接合法已經無法使用，而業界大部分使用異方性導 心（An⑽。P1C _duetlve fllm，acf)技術來克服此 15 術瓶頸。 現今業界所使用之異方性導電膜係利用在一高分子 _中添加若干導電粒子與絕緣粒子的方式製作，同時並 藉由卩周整所添加之導電粒子 <形狀、材質與數量的方式（如 ；:擇f形之導電粒子，其平均粒徑3至，且整體添加量 20%以下）私制所產生〈異方性導電膜的侧向導電性盘1244188 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method and structure for forming anisotropic conductive film layers: in particular, a type suitable for fine-pitch flip-chip packaging (pitch less than 40 microns) 5 Forming method and structure of square conductive film layer. [Previous technology] At present, the miniaturization of semiconductor devices has been rapidly developed, which has reduced the gate width to less than U) 0nm. The traditional flip-chip packaging technology that uses tin-lead bump bonding (㈣der 10bump) as the king is no longer sufficient. μ requires that new packaging technologies must be developed. Especially when the distance between the input and output pins of the chip is further reduced to less than 50 micrometers, the tin Γ block bonding method used in the existing flip-chip substrate manufacturing process is no longer available, and most of the industry uses anisotropic guides P1C_duetlve fllm (acf) technology to overcome this 15 bottleneck. The anisotropic conductive film used in the industry today is produced by adding a number of conductive particles and insulating particles to a polymer, and at the same time, by adding the conductive particles < shape, material and quantity (Such as :: f-shaped conductive particles, the average particle size of 3 to, and the total amount added below 20%)
耐熱性。此外，藉由施加-外㈣料 H 電粒子與絕緣粒子，異方性導雨^ 等 丨等兒膜所具有之導電異方性可 進一步增加增加。雖然如此，受限於導電粒子之尺寸，即 20 1244188 使施加一外加磁場仍無法使導電粒子均句分佈於整個異方 陡導電腠中且同時維持其導電異方性（即侧向導電性遠小 =縱向導電性），且導電粒子的數量有限，導致其電阻値較 高（一般為Ω級）。所以，目前業界所使用之異方性導電膜 5無法應用於細間距的覆晶構裝（間距小於40微米）用途。 Q此業界亟品種可運用於細間距構裝之異方、性導 電膜層及其形成方法，以做為一兼具高導電度及高導線異 方性之連接導線並應用於配合後續之具有更高密度之輸出 入埠晶片的封裝製程中。 10 【發明内容】 本發明之形成異方性導電膜層的方法，包括：（A)提 供一具有複數個微孔洞之奈米模板；（B)形成至少一金屬 導電膜層於此奈米模板之表面，且分別成長複數個金屬奈 15米線於此等微孔、洞中；（c)除去此奈米模板；⑼形成至少 T磁性披覆層於每-此等金屬奈米線之表面；⑻施加一磁 %於此寺金屬奈米線及此金屬導電膜層，且形成一固定層 於此金屬導電膜層之表面及此等金屬奈米線之間；以及⑺ 選擇性地移除此金屬導電膜層，形成一異方性導電膜層。 卜可&凡成之兴方性導電膜的表面以濺鍍法形成規則 且近間距的電極，而形成導電烊墊電極。 一本發明之異方性導電膜層，包括：一具有一上表面及 -相對於此上表面之下表面的絕緣層；以及複數個排列於 1244188 此絕緣層之奈米導線；其中 穿透此絕緣層至此下表面。 此等奈米導線係由此上表面 所以，運用本發明> 、 月<形成異方性導電膜層的方法形成 之異方性導電膜層可且古4丄 、 /、有核咼之縱向導電度（來自各個金 5屬奈米導線）及極低的侧向壤兩洽/十A ^/入p 等Μ*度（來自包覆各個金屬奈米 導線間的高分子材質固定層）。此外，由於各個金屬奈米導 、泉的門=係由奈米換板 < 複數個微孔洞的排列決定，所以 可依據實際的需要（如晶&认 (曰曰片知出入埠的排列及密度），利用 本發明之形成豈方攸道兩f , m生導讀層的方法成長並形成具有適當 10排列與密度的金屬奈米導岣咕rl ^ 田 蜀丁、木導線陣列及具有此一金屬奈米導線 陣列之異方性導電膜層。 15 I月之形成井方性導電膜層的方法可運用任何具 有導電功能之金屬披覆在奈米模板的一側，較佳為金或 本u之$成異方性導電膜層的方法可運用任何材質 之奈米模板，較佳為陽極氧化之氧化㉟（Anode alUmimUm。心）或聚碳酸酉旨㈣ycarbonate fllter)。本發 明^形成異万性導電膜層的方法可形成任何材質之金屬奈 米導線，較佳為銀、鎳絲。本發明之形成異方性導電膜 層的=所運用之奈米模板可藉由任何強驗溶液移除，較 佳為氫氧化鈉溶液。本發明之形成異方性導電膜層的方= 切性披覆層可以任何方式形成於金屬奈米導線之表面: 車乂佳為電鍍法、濺鍵法或蒸鍍法。本發明之形成異方性 電膜層的方法之磁性披覆層可為任何具磁性之材質，較佳 20 1244188 為鈷、鐵或鎳。如上所述之導線及磁性金屬材料，亦可將 此核殼結構的奈米導線製作為磁性導線當成核心，其外披 覆奈米導電層。本發明之形成異方性導電膜層的方法所運 用之固定層可為任何可熱固化或光固化之高分子材料，較 佳為聚亞醯銨或環氧樹酯◦本發明之形成異方性導電膜層 的万法之固定層可以任何方法形成於金屬導電膜層之表 面，較佳為灌注法。 曰 10 15 、，另外，本發明之形成異方性導電膜層的方法步驟(f) ^後，可更包括一步驟（G)，以形成複數個電極於此異方性 導電膜層之表面’㈣成導電焊#電極。其中，此等電極 的形成方法較佳為濺鑛法或蒸㈣。本發明之形成異:性 導電膜層的^法之雜可具有任㈣狀，較佳為方形或圓 形〇 20 或鎳 、本發明之異方性導電膜層之絕緣層可為任何可熱 化或光固化之高分予材料，較佳4聚亞醯銨或環氧樹醋。 本發明之異方性導電膜層所具有的奈米導線可由任何 材質構成’較佳為銀、鎳或鉛。本發明之異方性 所具有的奈米導線可選擇性具有—磁性披覆料其: 且此磁性披覆層可為任何具有磁性之材質，較佳為始 5\/ /¾¾ 〇 【實施方式】 圖1A及圖1B係本發明-較佳實施例之形成異方性導 電膜層的方法示意圖’其中圖所示之流程係接續圖u 1244188 所示之形成異方性導電膜層的流程。首先，如圖1A所示， 提供一具有複數個微孔洞121之奈米模板12及並於其表面 以濺鍍方式形成一金薄膜U。其中，奈米模板12係為 Whatman公司出產之型號An〇discTM 13, 25, 47的陽極處 5理氧化紹模板（Anodic aluminium oxide，AAO)，其所具有之 被孔洞121的孔隙密度為25-50% (porosity: 25-50%)。接 著’便利用電鍍的方法成長銀奈米導線13於微孔洞121 中，而電鍍時所使用之電鍍液為約i〜％硝酸銀離子溶液 及約20 wt%的醋酸銨離子溶液構成之混合溶液，其酸鹼值 10約為6.5左右。此外，於進行電鍍成長銀奈米導線時，持 續通入氮氣（電鍍時所使用之電流約為〇·4 mA，電鍍時間 約需3小時）。 當銀奈米導線13成長完畢時，將金薄膜11與奈米模 板12浸入一氫氧化鈉溶液（圖中未示）中，移除奈米模板12 15並形成複數個銀奈米導線13於金薄膜丨丨的表面。接著， 如圖1B所不，再次利用電鍍的方式於複數個銀奈米導線 13的表面成長一層材質為鈷的磁性薄膜丨4。此時，所形成 之銀奈米導線13的平均直徑約為1〇〇至2〇〇 nm ,而磁性 薄膜14的平均厚度約為30至40 nm。 ^由於磁丨生溥膜14具有明顯的磁異方性特性，所以接著 =加外加磁場（圖中未示）於複數個銀奈米導線13及金薄 )1以彳呆控複數個銀奈米導線13的排列並使其平行於 、每方向排列。當複數個銀奈米導線13排列整齊後，便以 1244188 灌注法將一聚亞醯銨（P〇lylmide，PI)材質的流體形成於金 薄膜11的表面及複數個銀奈米導線13的周圍，且加熱至 120 °C以使前述之聚亞醯銨材質的流體熱固化，而形成固 定層15。最後，再利用機械研磨的方法移除金薄膜u，形 5成一異方性導電膜層16。而在此異方性導電膜層16中， 複數個銀奈米導線13的平均長度約為3〇微米，平均線徑 約為0.2微米，平均間距約為〇 〇3微米，且異方性導電膜 層16的導電異方性大於1〇6(縱向導電度與側向導電度的 比值）。 10 圖2係運用本發明一較佳實施例之形成異方性導電膜 層的万法所形成之異方性導電膜層的電子顯微鏡圖形，其 中銀奈米導線之表面鍍有一層鈷金屬膜。 八 如W 3所示，€用本發明一較佳實施例之形成異方性 導電膜層方法所形成之異方性導電膜層M，在實際應用於 15覆晶封裝製程前，必須運用錢鑛法於其表面形成複數個電 私32而le些弘極32必須對應於所配合之相關封裝基板（圖 中未示）及晶片（圖中未示）所具有之坪塾㈣）的排列及相 關位置。 待鍍上後數個電極於異方性導電膜層之表面以後，此 、有複數個私極（圖巾未示）於其表面之異方性導電膜層W 便於覆晶封裝製程中被置於封裝基板42及晶片43之間。此 時，位於兴万性導電膜層41表面（上表面及下表面）之複數 10 1244188 個私極（圖中未示）分別對應於封裝基板42的複數個烊墊 421及晶片43的複數個烊墊431，如圖4所示。 需、/王意的是，封裝基板42的複數個焊墊421及晶片43 的複數個焊墊43 1必須涵蓋複數個個位於異方性導電膜層 5 41表面的電極（圖中未示）。以20微米間距（pitch)的焊墊^ 例，井方性導電膜層4丨上之電極間距為2微米，所以每一晶 片的綷墊可以與25個電極連接以確保晶片與異方性導電膜 層41之間具有良好的導電性。 10 15 但另一万面，由於異方性導電膜層41之各銀奈米導線 411係被聚亞醯銨（Polyimide，ρι)材質的固定層4丨2固定位 置，所以各銀奈米導線411之間均具有絕緣性的固定層。因 此，本發明之異方料電膜層41的導電異方性大於ι〇6(縱 向導電度與側向導電度的比値），使得晶片43各焊塾奶之 間及封裝基板42各焊独丨之間並不會發生短路㈣象。Heat resistance. In addition, by applying -exogenous H electric particles and insulating particles, the anisotropic conductivity of the film such as anisotropic rain can be further increased. However, due to the size of the conductive particles, that is, 20 1244188, the application of an external magnetic field still cannot make the conductive particles evenly distributed in the entire anisotropically steep conductive puppet while maintaining their conductive anisotropy (that is, the lateral conductivity is far away). Small = longitudinal conductivity), and the number of conductive particles is limited, resulting in a high resistance 値 (generally Ω level). Therefore, the anisotropic conductive film 5 currently used in the industry cannot be applied to fine-pitch flip-chip packaging (pitch less than 40 microns). QIn this industry, the varieties can be applied to fine-pitch structured anisotropic and conductive conductive film layers and their forming methods, as a connection wire with high conductivity and high wire anisotropy, and applied to the subsequent Higher density I / O port chip packaging process. [Summary of the Invention] The method for forming an anisotropic conductive film layer according to the present invention includes: (A) providing a nano template with a plurality of micro-holes; (B) forming at least one metal conductive film layer on the nano template A plurality of metal nanometer 15-meter wires are grown in these micro-holes and holes; (c) removing the nanometer template; ⑼ forming at least T magnetic coating on the surface of each of these metal nanometer wires; ⑻ apply a magnetic% to the temple metal nanowire and the metal conductive film layer, and form a fixed layer between the surface of the metal conductive film layer and the metal nanowires; and ⑺ selectively remove this The metal conductive film layer forms an anisotropic conductive film layer. The surface of Bu Ke & Fan's Xingxing conductive film was formed by sputtering with regular and close-spaced electrodes to form a conductive pad electrode. An anisotropic conductive film layer according to the present invention includes: an insulating layer having an upper surface and an opposite surface to the upper surface; and a plurality of nanowires arranged in the insulating layer of 1244188; The insulating layer thus reaches the lower surface. These nanowires are formed on the upper surface. Therefore, the anisotropic conductive film layer formed by using the method of the present invention for forming the anisotropic conductive film layer may be as old as 4 丄, /, nucleated. Longitudinal electrical conductivity (from each of the 5 metal nanowires) and extremely low lateral soil contact / ten A ^ / p p, etc. (from the polymer material fixed layer covering the metal nanowires) . In addition, since the gate of each metal nanometer and spring is determined by the arrangement of the nanoplate changing plate < multiple micro-holes, it can be based on the actual needs (such as crystal & recognition) And density), using the method of the present invention to form a two-layer, two-layer guide layer to grow and form a metal nanometer guide with proper arrangement and density. ^ Tian Shuding, wooden wire array and having this An anisotropic conductive film layer of a metal nanowire array. The method of forming a well-shaped conductive film layer in January may use any metal having a conductive function to cover one side of a nano template, preferably gold or The method of forming an anisotropic conductive film layer in this method may use a nano template of any material, preferably anodized ytterbium oxide (Anode alUmimUm) or polycarbonate fyter. The method of the present invention for forming a heterogeneous conductive film layer can form a metal nanowire of any material, preferably silver or nickel wire. The nano-template used to form the anisotropic conductive film layer in the present invention can be removed by any strong test solution, preferably a sodium hydroxide solution. The square of the anisotropic conductive film layer of the present invention can be formed on the surface of a metal nanowire in any manner: the car is preferably an electroplating method, a sputtering method, or an evaporation method. The magnetic coating layer of the method for forming an anisotropic electrical film layer of the present invention may be any magnetic material, preferably 20 1244188 is cobalt, iron, or nickel. As mentioned above for the wires and magnetic metal materials, the core wires of the core-shell structure can also be made into magnetic wires as the core, and the nano-conductive layer is coated on the outside. The fixing layer used in the method for forming an anisotropic conductive film layer of the present invention may be any thermally or light-curable polymer material, preferably polyammonium ammonium or epoxy resin. The fixed layer of the conductive film layer can be formed on the surface of the metal conductive film layer by any method, and the pouring method is preferred. In addition, after the step (f) of the method for forming an anisotropic conductive film layer of the present invention, a step (G) may be further included to form a plurality of electrodes on the surface of the anisotropic conductive film layer. '㈣ 成 conductive 焊 #electrode. Among them, the method for forming these electrodes is preferably a spitting method or a steaming method. The method of forming the anisotropic conductive film layer of the present invention may have any shape, preferably square or circular, or 20 or nickel. The insulating layer of the anisotropic conductive film layer of the present invention may be any heat Chemically or light-curing high-grade materials, preferably 4 polyimide or epoxy resin vinegar. The nanowires included in the anisotropic conductive film layer of the present invention may be made of any material ', preferably silver, nickel or lead. The anisotropy of the nanowire of the present invention can optionally have a magnetic coating material: and the magnetic coating layer can be any material with magnetic properties, preferably from 5 \ / / ¾¾ 〇 [Embodiment 1A and 1B are schematic diagrams of a method for forming an anisotropic conductive film layer according to a preferred embodiment of the present invention, wherein the flow shown in the figure is a process following the flow for forming an anisotropic conductive film shown in FIG. 1244188. First, as shown in FIG. 1A, a nano template 12 having a plurality of micro holes 121 is provided, and a gold thin film U is formed on the surface of the nano template 12 by sputtering. Among them, the nano template 12 is an anode type Anodic aluminium oxide (AAO) at the anode of the model AnOdiscTM 13, 25, 47 produced by Whatman. The pore density of the hole 121 is 25- 50% (porosity: 25-50%). Next, it is convenient to grow silver nanowires 13 in the micro-holes 121 by electroplating. The plating solution used in the electroplating is a mixed solution composed of about i ~% silver nitrate ion solution and about 20 wt% ammonium acetate ion solution. , Its pH value is about 6.5. In addition, when electroplating to grow silver nanowires, nitrogen gas is continuously applied (the current used during electroplating is about 0.4 mA, and the plating time takes about 3 hours). When the silver nanowire 13 is grown, the gold thin film 11 and the nano template 12 are immersed in a sodium hydroxide solution (not shown), the nano template 12 15 is removed, and a plurality of silver nanowires 13 are formed. The surface of the gold film. Next, as shown in FIG. 1B, a magnetic film made of cobalt is grown on the surface of the plurality of silver nanowires 13 by electroplating. At this time, the average diameter of the formed silver nanowire 13 is about 100 to 200 nm, and the average thickness of the magnetic thin film 14 is about 30 to 40 nm. ^ Because the magnetic film 14 has obvious magnetic anisotropy characteristics, the next step is to add an external magnetic field (not shown in the figure) to the plurality of silver nanowires 13 and thin gold) 1 to control the plurality of silver nano The rice wires 13 are arranged parallel to each other. After the plurality of silver nanowires 13 are aligned, a fluid of polyimide (PI) is formed on the surface of the gold thin film 11 and around the plurality of silver nanowires 13 by a 1244188 infusion method. , And heated to 120 ° C to thermally solidify the aforementioned polyimide ammonium fluid to form a fixed layer 15. Finally, the gold thin film u is removed by mechanical polishing to form an anisotropic conductive film layer 16. In this anisotropic conductive film layer 16, the average length of the plurality of silver nanowires 13 is about 30 micrometers, the average wire diameter is about 0.2 micrometers, and the average pitch is about 0.03 micrometers. The conductive anisotropy of the film layer 16 is greater than 106 (the ratio of the longitudinal conductivity to the lateral conductivity). 10 FIG. 2 is an electron microscope pattern of an anisotropic conductive film layer formed by a method for forming an anisotropic conductive film layer according to a preferred embodiment of the present invention, in which a surface of a silver nanowire is coated with a cobalt metal film . As shown in W 3, the anisotropic conductive film layer M formed by the method for forming an anisotropic conductive film layer in a preferred embodiment of the present invention must be used before it is actually applied to the 15 flip-chip packaging process. The mining method forms a plurality of electric privates 32 on its surface, and some Hongji 32 must correspond to the arrangement of the related packaging substrates (not shown) and the wafers (not shown). Related locations. After the several electrodes are plated on the surface of the anisotropic conductive film layer, there are a plurality of private electrodes (not shown in the figure) on the surface of the anisotropic conductive film layer W, which is convenient for the flip-chip packaging process. Between the package substrate 42 and the chip 43. At this time, the plurality of 10 1244188 private poles (not shown) located on the surface (upper and lower surfaces) of the Xingwan conductive film layer 41 correspond to the plurality of pads 421 and the plurality of wafers 43 of the package substrate 42, respectively. The pad 431 is shown in FIG. 4. It is important to note that the plurality of bonding pads 421 of the package substrate 42 and the plurality of bonding pads 43 1 of the wafer 43 must cover a plurality of electrodes on the surface of the anisotropic conductive film layer 5 41 (not shown in the figure). . Taking a 20-micron pitch pad as an example, the electrode spacing on the well-shaped conductive film layer 4 is 2 micrometers, so the pads on each wafer can be connected to 25 electrodes to ensure that the wafer is conductive to anisotropy. The film layers 41 have good electrical conductivity. 10 15 But on the other side, since the silver nanowires 411 of the anisotropic conductive film layer 41 are fixed in position by the polyimide (poly) fixed layer 4 丨 2, each silver nanowire is fixed. There are insulating fixing layers between 411. Therefore, the conductive anisotropy of the anisotropic electrical film layer 41 of the present invention is greater than ι〇6 (the ratio of the longitudinal conductivity to the lateral conductivity), so that each of the solders of the wafer 43 and each of the packaging substrate 42 are soldered. There is no short circuit phenomenon between the two.
20 圖5八係運用本發明另—較佳實施例之形成異方性導 電膜層方法於灌注固定層之步驟前的半成品*意圖，其中 奈米導線52的材質為具有磁性性質的鉛金屬，:覆蓋^奈 米導線52表面的薄膜係為銀薄膜53。同樣地，此種处構了 奈米導線亦可以利用外加磁場的方式控制其排列方: 前述之披覆一磁性薄膜的銀奈米導線相同。但是，由於 材質之奈米導線52所具有的磁異方性會隨著其線徑的= 而減少’所以在實際運用時，奈米導線52的平 : 於50奈米為佳。 ’二Α ψ20 FIG. 5 is a semi-finished product of the method of forming an anisotropic conductive film layer according to another preferred embodiment of the present invention before the step of injecting the fixed layer. The intention is that the material of the nanowire 52 is a lead metal having magnetic properties. : The thin film covering the surface of the nanowire 52 is a silver thin film 53. Similarly, the nanowire structured in this way can also be controlled by applying a magnetic field: the silver nanowires covered with a magnetic film are the same as described above. However, since the magnetic anisotropy of the nanowire 52 made of the material decreases with the diameter of the wire ', the flatness of the nanowire 52 is preferably 50 nanometers in actual use. ’二 Α ψ
11 1244188 一至於包含此半成品之異方性導電膜層的形成方法，則 與前述之銀奈轉線大致相同。即將-具有-金薄膜51 於，、表面之奈米模板（圖中未示）浸入一電錢液中（由約$ Wt%硫酸錄離子溶液及約2Gwt%的醋酸錢離子溶液混合 5而幻，利用電鍍方式成長奈米導、線52並於電鑛時持續通 入氮氣（使用之電壓約為2·1ν，電艘時間約需7小時）。 一旦鉛奈米導線52成長完畢時，便以_氫氧化納溶液 (圖中未示）中，移除奈米模板（圖巾未示）而形成一複數個鈷 奈米導線52於金薄膜51的表面。接著，再次利用電鐘的方 ίο ^於複數個鉛奈米導線52的表面成長一層銀薄膜53。接 著，便施加一外加磁場（圖中未示）於複數個鈷奈米導線U 及金薄膜51，以操控複數個鈷奈米導線52的排列並使其 平行於磁場方向排列。當複數個鈷奈米導線52排列整齊 後’便以灌 >王法將-聚亞酸銨（pQlyimide，ρι)材質的流體形 15成杰至薄膜5 1的表面及複數個鈷奈米導線52的周圍並加 熱至120 QC，使前述之聚亞醯銨材質的流體熱固化，而形 成固足層（圖中未示）。最後，再利用機械研磨的方法移除 金薄膜5 1，形成異方性導電膜層54，如圖5B所示。 上述貫施例僅係為了方便說明而舉例而已，本發明所 20主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 12 1244188 5 10 15 =:發明一較佳實施例之形成異方性導電膜層的方 二所示之本發"佳實施例之形成異方 膜層的方法之流程示意圖。 圖2係運用本發明一齡社杳y丨 方、去 土貫也例之形成異方性導電膜層的 成之異方性導電膜層的電子顯微鏡圖形。 圖3係運用本發明—奈以土 法所…： 例之形成異方性導電膜層方 成性導電臈層的示意圖，其中複數個電極形 成於異方性導電膜層的表面。 y 圖4係運用本發明_ 、土& / 奴佺貫施例之形成異方性導電膜芦方 法所形成之異方性導電膜犀痺 ' 圖从係運用本發明另—晶構裝的示意圖。 展古丄、 車乂佺κ鉍例之形成異方性導電腺 "法於灌注固定層前之半成品示意圖。 、 運用本發明另-較佳實施例之形成異方性導電膜 層方法所形成之異方性導電膜層的示意圖。 電膜11 1244188 As for the method of forming the anisotropic conductive film layer including this semi-finished product, it is approximately the same as the aforementioned silver nano-conversion line. Immediately-have-gold thin film 51, the nano-template on the surface (not shown) is immersed in an electric money solution (mixed with about 5 Wt% sulfuric acid ion solution and about 2Gwt% acetic acid ion solution to mix 5) To grow the nanowires and wires 52 by electroplating, and continue to introduce nitrogen gas during the electric mining (the voltage used is about 2.1v, and the time required for the electric boat is about 7 hours). Once the lead nanowires 52 are grown, they will In the sodium hydroxide solution (not shown), the nano template (not shown) is removed to form a plurality of cobalt nano wires 52 on the surface of the gold thin film 51. Then, the square of the electric clock is used again. ίο ^ A layer of silver film 53 is grown on the surface of the plurality of lead nanowires 52. Next, an external magnetic field (not shown) is applied to the plurality of cobalt nanowires U and the gold film 51 to control the plurality of cobalt nanowires The rice wires 52 are arranged parallel to the direction of the magnetic field. When a plurality of cobalt nano wires 52 are arranged neatly, they are formed into a fluid made of pQlyimide (rho) by the method of filling > Wang. The surface of Jiezhi film 51 and the surroundings of the plurality of cobalt nanowires 52 are heated. 120 QC, heat curing the fluid of the aforementioned polyimide material to form a solid layer (not shown). Finally, the gold thin film 51 is removed by mechanical grinding to form an anisotropic conductive film layer 54, as shown in FIG. 5B. The above-mentioned embodiments are merely examples for the convenience of description. The scope of the rights claimed by the present invention should be based on the scope of the patent application, rather than limited to the above-mentioned embodiments. Brief description of the formula] 12 1244188 5 10 15 =: Schematic flow chart of the method of forming an anisotropic film layer shown in the second embodiment of the invention " best embodiment " of forming an anisotropic conductive film layer in a preferred embodiment of the invention. Fig. 2 is an electron microscopy image of an anisotropic conductive film layer forming an anisotropic conductive film layer using the present invention's first-year-old society, and detoxification. Fig. 3 is an application of the present invention-Nai Yi Earth law institute: Example of a schematic diagram of forming an anisotropic conductive film layer into a square conductive conductive layer, in which a plurality of electrodes are formed on the surface of the anisotropic conductive film layer. Figure 4 shows the application of the present invention. / The formation of anisotropic conductive film The anisotropic conductive film formed by the method is shown in the schematic diagram of another crystal structure using the present invention. Examples of the formation of anisotropic conductive glands in the case of Zangu 丄 and Che 乂 佺 bismuth " Method for perfusion fixed layer Schematic diagram of the previous semi-finished product. Schematic diagram of the anisotropic conductive film layer formed by using the method for forming an anisotropic conductive film layer in another preferred embodiment of the present invention.
【主要元件符號說明】[Description of main component symbols]
11金薄膜 13銀奈米導線 16異方性導電膜 41異方性導電膜層 42封裝基板 12奈米模板 14磁性薄膜 31異方性導電膜層 411銀奈米導線 421焊墊 121微孔洞 15固定層 32 電極 412固定層 43 晶片 13 1244188 431焊墊 51金薄膜 52 奈米導線 53銀薄膜 54異方性導電膜層11 gold thin film 13 silver nano wire 16 anisotropic conductive film 41 anisotropic conductive film layer 42 package substrate 12 nano template 14 magnetic film 31 anisotropic conductive film layer 411 silver nano wire 421 solder pad 121 micro hole 15 fixed layer 32 electrode 412 fixed layer 43 wafer 13 1244188 431 solder pad 51 gold film 52 nanometer wire 53 silver film 54 anisotropic conductive film layer
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