TWI244015B - A clock tree synthesizing tool synchronously considering low clock skew and low power consumption - Google Patents

Abstract

The invention brings up a method, which is applied with the skill of insertion, removal, swap and shift buffers to quickly determine the type and location of every buffer type in the clock tree, and pertinent to the combinational design process of designed clock tree to quickly determine the type and location of skew buffer, making the entire design meet the database design specification and the clock skew meet condition limitation respectively. The computation tool of the invention that quickly determines the buffer type and position in the clock tree comprises the inputted clock tree structure to be processed containing the information of each circuit and buffer insertion location, the database for inputting specific component containing the characteristics of input load, power consumption, clock delay, conversion time for output signal, etc., and initial state configuration. Determine if the lock tree structure complies with the feasible solution of design specification; if no, apply the load balancing and buffer balancing methods to get a feasible solution. Quickly determine the buffer type to reduce the power consumption of the clock tree. Apply the optimal technique integrating simulated annealing method to acquire the global optimal solution of the integrated buffer with minimum power consumption.

Description

1244015 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a high-speed super large-scale integrated mine. The low-power clock tree circuit synthesis of the computer aids the design of the computer. It can add tears, weave, remove, replace, and shift the buffers on the clock tree to reduce the clock tree's miscellaneous power and clock distortion. Technology [Prior technology] As an indicator of the processing speed of lean materials. And for each of the riches in the transmission, we must maintain the integrity of the signal, that is, it must meet the following timing requirements ^^ f ^ € (Clock ^? Poor material warehouse 'needs to meet its design specifications. Clock delay means the longest time it takes for the clock signal sender to transmit to the receivers of each synchronization system. Shortening the clock delay can help speed up the transmission of the clock signal. In other words, it can increase the operating frequency of the circuit. Clock clock signal transmission The path #time difference between any two receivers in the M-tree is too large. If the value is too large, the clock signals received by the receivers of the synchronization systems will be out of sync, which may cause signal distortion and logical malfunction. For special buffering 1. Its TransitiQn Time reads $ Zanzai, which has a tolerance and lower limit. ^ When the input 5 hole number conversion time or the output load is greater than or less than the upper and lower limit, it will cause the buffer to be unavailable. Expected operating conditions, so the buffer tree and flip-flop on the clock tree's operating state must meet the design specifications. With the rapid development of ultra-large integrated circuit deep sub-micron process technology In terms of timing considerations, the delay of the signal on the interconnect is much larger than the delay on each component. Let's talk about 244015 clock tree synthesis to reduce the delay of the tree path. In the conventional technology, the first- This design method is to check the length of the financial path as much as possible. Wei Changqi, the longer the time delay on the money path, the greater the power consumed by the transition of the line towel in the same way. In the design of large-scale integrated circuit layout, 'the optimal length of the circuit is considered to reduce the time delay. The second design method is to cushion the person who reads t, and the compensation can be segmented to reduce the line-view delay.' The power amplifier can round the capacitor, which can reduce the equivalent load of each section of the line, reduce the rise time for the tiger to charge the speed, and achieve the purpose of reducing the line delay. At the same time, for the consideration of the circuit's miscellaneous power, when the input signal is converted _ Reduce, at the same time can reduce the component consumption b ®-for the clock tree network expansion, the clock signal input connection is called the root (Root) 'Flip-Flop' clock signal receiving end is called the leaves. You then ( Root) The clock signal receiving end mi i㈣) from the positive to the negative, including the buffers and connection lines along the way to form a complete path (Path). The accumulated buffer and line delay is the path delay (y) There are two paths to the root machine 1 and F1.3 respectively. The path delay difference is-the skew rate of the group clock. Insert the buffer ⑽ at an appropriate position on the clock tree network 除. In addition to reducing the time L, the method of changing the time delay of each receiving end by selecting different types of buffers can still reduce the time in the clock tree. Clock skew for each path. 22 is a conventional technology (U.S. Patent 5, Qing 22) a design layout layout unified layout. And mouth pass * only place (54) and winding (62). Use logic to synthesize ㈣. Do her pure) tool generation-group description of the logic gate and its connected grid wiring list_ist), followed by Wei Zhizheng will represent the standard unit between various types of logic in the grid wiring list (Standard Ce 戦 on the chip The location of the selected place, 1244015, usually the distance between the locations Ang / I ,,, 罔 The connection relationship of each component in the line list is

Off, the purpose of which is to reduce the optional A and again of the winding later. , 62, and 9 (62) are actually connected according to the result of the placement. The current design adds the clock tree to the yak ~, the heart into steps (⑽, ㈣ 归 〇) into the layout design. Step (56) optimizes the synthesis and winding of the clock tree network, so the content of the logic synthesis grid routing table is modified. In addition step _ still contains-analysis hardware description processor (brain duties

Wn 'According to a given timing design specification, the analysis logic synthesizes the most recognized _secret input in the grid wiring list, and the relative positions of its slow _ plus Luline line towel and other components can be inserted as a buffer in the next step The basis of the physical design: ^^ * Placed properly when describing each step__㈣ # butterfly_ Follow steps. After entering the buffer, other components that have been placed will be affected. Therefore, step ㈣ must be read again. In addition, the transfer rush into the county segmented from the clock gas 2 = to the connections of each Γ end. Therefore, the clock tree network that has been completed in step (S6) must be modified. In general, in order to minimize the clock delay, the adjusted The position of turning over is not put. _ &Amp; Priority to transfer wealth = Bu Buxin) Calculate that every person who receives from the post to the post receives == standing and turning over wealth and material, and then enter step (62). The component's actual includes the wheel ^ _ line, otherwise, you must _ step ㈣ readjust the position of the element position scale clock _ road physical winding. However, 'as shown in the clock tree network synthesis process in Figure 2, all the inserted buffers only use the same 1244015-a kind of buffer', but the actual design towel is thinned down, _ Ke Xudong Llbrary) with the outline of the coffee 她 ^, $ Empty is more dependent on meeting timing design specifications as its main disadvantage. If it is appropriate for each clock on the clock tree, it will be difficult for each ship to be queued, and the lack of clocks will make it meet the timing design specifications, and the clock will be used to identify the consumption. Generally, the design of a single Lin Fan-type database buffer is different, so how can the area of the buffer be different from each other, so the Γ sound circuit's _ acoustic-general surface _ aviation _ smaller can drive a large load to accelerate Signal rise time of the load. However, the larger buffer itself also has a large delay and a large power consumption. How to take a compromise between clock delay and power consumption is one of the key considerations of the algorithm of the present invention. When selecting the buffer type, it is assumed that there are n types of buffer types to choose from, and m__ need to be inserted on the clock tree network. If a carpet-like search method is used, it is necessary to determine which of the mn buffer combinations can obtain the minimum clock delay and conform to the clock skew surface system. -In general, in considering both the buffer insertion and the buffer type selection, the results of the establishment of the timing sequence are repeatedly repeated ^ T ^^ 0 »£ ^ t ^ P ^» (Circuit Level Simulations), Jc design process caps cost a lot of compilation room. In terms of the design of ultra-large integrated circuit design tools, how to quickly find out the current buffer type from a given buffer timing design database during the clock tree circuit synthesis phase to reduce simulation Time, which conforms to the clock distortion rate time gauge specifications and the minimum God consumption, occupy a very important position in the clock tree circuit and cylinder. 1244015 In the conventional technology, (by A. Vittal, M. Marek-Sadowska, "Low-Power Buffered Clock Tree Design," IEEE Trans. On CAD of Integrated CAS, Vol. 16, No. 9, pp. 965- 975, proposed in 1997), applying the method of inserting buffers and constructing an H-tree architecture to achieve the best solution of area and power consumption; the technique of applying inserting buffers is proposed in the conventional technology to reduce the clock distortion rate of the clock tree (by J · L. Neves and EG Friedman, "Design Methodology for Synthesizing Clock Distribution Networks Exploiting Nonzero Localized Clock

Skew ,,, IEEE Trans. On VLSI Systems, Vol. 4, No. 2, pp. 286-291, proposed in 1996); and the conventional technology proposes the application of the technique of inserting buffers to reduce the differences in buffers and reduce the short-circuit current. To avoid extra current consumption (by S. Pullela, N. Menezes and LT Pillage, "Low Power IC Clock Tree Design ", Proceedings of the IEEE Custom Integrated

Circuits Conference 1995, pp. 263-266); and other conventional technologies (by κ · m · Cairig etc. A New Direction in ASIC High-Performance Clock Methodology ,,,

Proceedings of the IEEE Custom Integrated Circuits Conference 19985 pp. 593-596) should reduce the number of people and reduce power consumption. In the above method, only the same type of buffer II is used, which is inconsistent with the actual circuit design process. In addition, Wei did not make shame removal, replacement, or shifting of the clock on the clock tree. The clock tree connection achieves the most order and power consumption of the buffer combination. Other U.S. patents US6696863 use cluster insert buffers to achieve the same clock delay, avoiding 22 application-level buffers, like zero-day _ scale, us_37 balance day _ low clock skew rate, and 67_ GU balance all levels ^ The system conforms to the design specifications. The depth of the linden tree is selected in detail to reduce the power consumption. The above patents aim at the artificial creation of the clock tree. However, none of the goals of the clock distortion rate can be put forward-a kind of effective algorithm for 1244015 to simultaneously buffer multiple clock types, and apply buffer clocks and clocks. The curvature and power consumption of the inventor, the inventor of the inventor of the Republic of China ^ historiography standard circuit synthesis tools ", Shu Duo Gao = ^ ^ = buffer type and meet the needs of time, appropriate selection of each body on the clock tree Circuit towel clock tree circuit synthesis: design specifications for timing distortion of the clock, but its buffer,; ,, and minimum clock delay and formula 'and no optimization analysis for the impact of power consumption f * ^ only provide replacement buffer square

f SUMMARY OF THE INVENTION J The purpose of the present invention is to propose a method for applying insertion and removal of punch types. The shirts, shifts, and shifts of the clock tree ease the existing kimonos and road shafts. The design process quickly determined that the buffer was placed on the clock tree, and the high-clock tree was combined to design the r Φ n to meet the% order design specifications. The position and axis of the SI in the process are in the traditional chip design

Among 4 in 4½: W includes clock tree electrical group wiring list, clock tree each heart order. At this time, the input packet punch power __ road delay, buffer delay and slow 1 speed kiss fine position and type 1 car Electric_wire column. The reason why the method proposed by this meal is that the low-power-rate sun-keeper clock tree can be synthesized is to read the placement position of each buffer and determine its type. Its characteristics are as follows: ⑴ This invention Yuanzhengzhi: sample structure 'Record the relationship between the front stage and the back stage of each buffer. During each optimization process of 10 1244015, the clock delay and power consumption of each buffer can be calculated in linear time; () A crooked design specification. The present invention adopts the rule of thumb in the relationship between the buffer type and the load in each layer of the clock tree to optimize the adjustment in order to obtain the minimum power consumption and meet the design specifications for strict clock skew restrictions. (3) Applying the concept of Heuristic for optimization calculations, regardless of the exhaustive method of carpet search, can save the time to find the best solution. There are a limited number of buffers in the clock tree, but the placement is not infinite. ^ This post describes the heuristic method of mosquito mitigation. A fine simulated annealing algorithm (Simulated Annealing, SA) can be used to obtain the local best.知 知 加 〇ptima]

Solution) 'With the technology of load balancing, we can obtain the most comprehensive domain in the world _ 〇 邱 细 S—); (4) Under the allowable range of equipment, the hair of the hair duck lay soft red with processing of millions of logic. Toward super-large integrated circuit. In the specific implementation of the method, the method of determining the buffer placement and type of the low-consumption speed test of the present invention 'includes the following steps ... (1) Enter the list of 4 scientific clock tree power grids, including information and buffers for each line The position of the person is also input into the buffer database and flip-flop database to provide the basis for the program; (2) the initial miscellaneous state office '· (3) whether the circuit structure meets the design specifications of the clock distortion rate , And whether the circuit database will be violated during the operation of the device. ^ If the violation of the above Lai Fan's steps of inserting, removing, replacing, and shifting the buffer to obtain a feasible solution for clock tree synthesis, The heuristic algorithm relies on the Weiche algorithm to obtain the best solution that minimizes power consumption and meets design specifications. [Embodiment] As mentioned above, the purpose of the present invention is to propose a kind of fast decision clock to shoot all buffers 1244015 and a differentiating tool, so that the power consumption of the clock is minimized and it meets the clock distortion rate as a design specification. Running a lion by a rider provides a limited, the easiest way to solve the above optimization problem is to search for the carpet one by one to replace the type of each buffer in the clock tree and compare the power consumption of each group and the clock. Skew, until the best combination of buffer types is selected, which has the lowest power consumption and meets clock skew timing design specifications. The main disadvantages of the thin b method are: _ operation time; _ buffer insertion, removal, shift and other steps, the program is not easy to find the best solution.

Based on the above-mentioned principles, She Wei-she quickly decided to slow down the editing, editing, and recording of clocks in the clock tree. Then she reached: ⑴ Insert the original clock tree design that does not meet the design violations, insert the buffer, and move it. Steps such as division, replacement, shift, etc., are deserving of bribes; (2) leveling __ shape heuristic cutting algorithm, which effectively determines the low energy consumption, time and time, the youngest sister is in line with the clock design, the most money punch Location and type combination. FIG. 3 shows a block diagram of a system according to a specific embodiment of the present invention. Enter the clock tree synthetic electrical line list of the specific embodiment _, the upper limit of the clock skew design specification (outline, and include the distinction between buffer ϋ and positive and negative n, timing: # 料 库 _, and determine whether it meets the design by step _ Specifications and clock distortion rate limits. Assuming that the above-mentioned restrictions are violated, the steps (addition) are adjusted. The synthesis method of the clock tree is adjusted to meet the design specifications. Otherwise, the steps are performed (⑽, replacing the buffer type to quickly reduce the clock tree power consumption). However, in this step, there is a risk of violating the design specification. Therefore, in step 4), it is judged whether the clock tree still meets the design specification. If it is violated, the step (11_override to the pre-state) is performed. The optimization algorithm of power consumption is to turn to (12_ the invention ends the hybrid tree reduction algorithm ends. 12 1244015 The edge of the specific database is in the low-energy clock tree synthesis calculation axis. For the Individual design database of _ power consumption miscellaneous can provide suppression, turn _ broken wire, _ correct shape buffer buffer database, correct _ five caps under the structure _ Xie analysis diagram, ㈣Buffer Lion CLKBUFXL with editing, difficult Zheng Zai, Gong Butterfly Driving capacity, _UFX1 has the second-smallest input load, the second-smallest power consumption, and the second-smallest driving capacity, while CLkbuFX20 has the most maximum input load, maximum power consumption, and maximum driving capacity. Consider the map, A.B. Levels C and C, where level a is the main driving buffer of a fixed type, let it be CLKBUFX8; level B is a slow transition, and its type and number can be changed, which are the X-axis and Y-axis of Figure 4. Tier c is the load flip-flop, the fixed flip-flop is turned over, and the fixed number of flip-flops is the number of loads. The load value can be estimated as the input capacitance of the flip-flop plus the load of the translation circuit. (Slow charm) Is the master of the α riding towel Wei Mi Na, the buffer _ is the B-level buffer-'The B-level buffer can reach at most Qing, load on the buffer (152), and the average load c-level positive according to the number of B-level buffers Inverter _. The power consumption diagram in Figure 4 is the sum of the apparent power consumption at that time, including the power consumption of the buffer, the power consumption of the inverter and the power consumption of the line signal conversion, where the power consumption is 0. Qilong library design of this kind of clock tree architecture Standard, so 0 is discussed. Its input signal conversion time or output load cannot be known through the database look-up table (TableLOOk_up), and four known input signal conversion times and load capacitance values will be used to detect four. The power consumption value at the corners is then calculated by the polynomial linear interpolation method (PolynomialInterpolation) to calculate the interpolation power to approximate the buffer power consumption. The present invention uses the empirical equation to determine 13 1244015 through the four corners. Z, B, C, Z), and then substitute the actual input signal conversion time and round-out load to solve. Through the presentation of this power miscellaneous 0: it can be found that its power consumption is ―concave distribution, in the ⑽ buffer. In the case of a small number, the input conversion time of the flip-flop is increased due to the increase of the load, thereby increasing the power consumption of the flip-flop part. However, in the design of a larger B-stage buffer size, the input loss can be reduced. Signal conversion time, however, the power consumption in the buffer section increases slightly. Through the above analysis of the power consumption of a specific database, the present invention can provide a clock tree synthesis buffer selection algorithm that adopts different strategies when the database has different characteristics.

Steps for searching clock delay and applying clock delay considerations The specification aspects of the remaining timing design of the present invention are related to calculating the path delay from the input terminal to the output phase, that is, accumulating a complete path from the root of the tree to the leaves, and the buffer delay is wide. The sum of line delays. The calculation principles are summarized as follows: ⑴ In order to achieve the purpose of calculating the path delay quickly, the line circuit «data generation grid edueed standafd p_itie f_ < ^ is described, at this time, the replacement buffer H_ class only affects the compilation delay and has nothing to do with the line delay.

For example, Tu Kun) is the electrical parameters of its chat format line, where the PI model (R1, C1, C2) is the first third-order Taylor expansion approximation of y⑻, which can be regarded as the equivalent line money buffering and kissing, against the line Cl + C2 〇R2O 0 ^ ^ and ignore the effect of line delay, that is, the buffer under the buffer, whose input I delay time is evenly scaled. The lioness __ coffee order = 14 1244015 —The table shows that, as shown in Figure 6, the approximate buffer delay value can be obtained by applying polynomial interpolation, and the method for obtaining the output signal conversion time is the same. (2) The types of replacement buffers should be changed relatively slowly. Known person: Valley value (PlnCapaeitance). As observed by the output of its pre-stage buffer, the delay of the buffer will also change as the load is changed. For example, in Figure 7, if the type of buffer (bias) is changed, the equivalent load of buffer_ will be changed, so both buffer_ and _ must re-check the table and refer to the delay. (3) Shifting the buffer Because the load of the buffer will also be affected by the change of the line, the delay of the buffer will also be affected. For example, in Figure 6, if the relative position of the buffer (162) and buffer_) is changed in physical design, Then change the equivalent load of the buffer_ so the buffer_and (the paste must be re-checked to calculate the delay. (4) the positive and negative of the synchronization system is the last-stage buffer, usually one buffer will receive multiple positive buffers. Inverters, in other words, the number of overall flip-flops is greater than the number of last-stage buffers. Figure 8 shows the low power consumption of the present invention to quickly determine the buffer position and type in the clock tree. Whether the clock tree design meets the design specifications The detailed flow 2 of step _ includes w mode, _ correction and inverse check on the day ___, and day _ load balancing step _, and each module must perform path delay calculation and design specification check after adjustment_输) t loses and expects. The profit sharing is explained in the following. The first is to check the program and _, including two observation points: 拖 in the database of the buffer power consumption and clock delay calculations 拖 州 ㈣ Green riding L signal conversion between day guard and rotation load size. Therefore, for the target gallop-level buffer, changing the setting or type will cause a 1244015 change of the front-level buffer's rotation signal conversion time. The conversion time of the input signals of components (buffers and flip-flops) in the "same%" lean library is limited by the upper and lower bounds. If the conversion time of the input signal is less than the allowable lower bound, or it is transferred to any Zhi ^ chang # is larger than the allowable upper bound, which will cause the component to fail to predict its phenomenon during operation, which is called a violation of design specifications. Similarly, for the components connected to the target buffer, the load value is in the data Kuyu has a mosquito and τ boundary Gu will also cause the buffer benefits to be unable to assess its neglect in detail, which is a violation of design specifications. ⑺ In digital circuit design, the clock tree is the longest-a signal line, and the clock signal is passed to the chip via clk. , J pass the clock Lai Qing Office, _shirt delete, coffee _ _ series of delay time is approaching _ the better, of which the circuit design to regulate the longest delay time and the shortest delay in property rights-_ It is also necessary to judge whether the curvature of the circuit meets the design specifications. The step of this program will become the most tender input in the present invention. The age judgment program must improve the efficiency as much as possible. The solution process towel The main consideration is @ 素 即 树 Buffer Zhen Zai. In addition to the above points, her design is feasible and affects the overall power consumption. It has significant effects on the clock delay and output signal conversion time of the buffer. It is reasonable to avoid the impact of Guang Yang ^ 'the input of the lack of buffers on the load of her time design rules' makes the clock delay effect approach π results. The time of turning the mind and body has a positive effect. The method in step (204) for quickly resolving clock skew design specifications is for the strict time limit of 16 1244015 clocks to the curvature limit. The clock delay caused by the -stage buffer is therefore the original clock. In the tree design # in force xcs, moaning bell distortion rate limitation, ~ the right exists-the flip-flop and other pros and cons are on the same level, which will cause the clock distortion rate limit to be violated. The position on the bell tree is not reconnected to the positive and negative __ on the rails, picking rails, this step will choose to buffer the balance and size of the front axis of the same object, so that the delay effect of the buffer meets the strict Clock skew limit. The force of the moon dagger and the loaded turn _) are those of the M ′ balanced clock shot buffer taken when the above-mentioned steps of moving the flip-flop still fail to meet the clock skew.

Cry, τ 6 flood 5 tiger from the input pin to the buffer. Second inversion-late outside ’can also reduce the power consumption of the buffer and the flip-flop. As shown in the figure (:: 7 E Chong A __ buffer Chong c, and the output from the buffer A is calculated to the rear stage. The round load is less than the largest buffer type of buffer A ^, U ^ (252) ^ 1A ^ W ^^

The job title '(254) coffee M (256) buffer M, read _, can be associated to lose money, the scale woman Bell tree buffer Lai group A, has a feasible solution. Consider buffers B and c—stage buffers, in which buffers D, E, and F are buffered by ⑽), and buffers G, Η 1, K, and L are driven by (256) buffer nc. , The current level is slow_to: the length of the physical scale of the under-level and slow-level is approximately the same length, and the input load of the human-level buffer is equal, so (254) the output and load of buffer B , (256) easing C 'It will cause the clock delay on (254) buffer B to be smaller than (256) buffer c, so the clock delay on buffer D, E, F is greater than buffer g, h, 1 J , K, L 'will violate strict clock skew design specifications. In this step, in order to avoid the excessively large lazy distortion rate, a load balancing strategy is adopted to comply with the design specification 2. If there are two or more buffers on the same level in the clock tree, select the record LQA ^,, the new buffer B and the _ device caused by the submarine caused by the submarine in the puncher. K-phase_., J remove-K and buffer.嚷 relationship, and reconnect buffer B and buffer κ. After this reload, it will be less than Yu ^ ,, and I have made sure that the new round-out balance increase of B: the reduced input and the turnover of the two buffers will tend to contain the howl) The load of the C key punch C: the human-level element is a flip-flop, and its judgment is based on the lion class. This is the application of the tree tree to the phase and the ship through the clock tree. ^ The root direction of the handle tree is considered at the same level at the same time, and the adjustment is performed. If it is still not satisfied, return to the step. The progress of (fine) meets the design specification, and the step of adjusting the circuit to a feasible solution ends (214). Right can be the most powerful edge rate

Figure 10 is the steps (called the detailed frequency of finding money and good solutions. For the clock tree design that conforms to the material-like seam curvature, the green T for fast axis rotation is performed. Pay mouth sigh juice = :, reduce _ 之 延 _- feasible method,-is:: =: class slow _ this step __, on the common path from all buffers in the U of the clock tree to the root of the tree, if Existing order — it is the buffer to remove the old and old swords, or the state of rush, ~ ^ 'Because the removal of the buffer to the clock of all flip-flops 18 1244015 caused a delay. A design rule that violates clock skew has been generated. However, the removal of the buffer must be tested with a wire-level buffer. Whether the load capacity is sufficient to drive the lower-level components, and whether the violation of the component right design specifications is caused. (2) For the buffers of the same level on the clock tree, if the connection status of the former and secondary buffers is similar, the job-based transfer can be moved to the target of “No, No This item has a wider range of implicated elements: Zai Lin, Qi Zhenxie Zai, and no time to lose. After calculating the specifications and calculating the clock shots, the clock clock is sufficient, and the clock tree structure is the basic structure that provides the optimization steps after removing and removing the necessary steps through step_. Step Tao provides a method to quickly determine the type of buffers on the clock tree. For the size of the flip-flops of the last-stage buffer riding load on the clock tree, change the size of the last_stage buffer step by step. Touch; the most __ steps step Tao, observe whether the scale crack curvature meets the design specifications, if one of the items fails to meet the design specifications, then step _ increase the type of buffer ϋ level, and decorate the buffer at all levels during calculation Clock delay, input signal conversion time, and output load all meet the database design specifications.

The clock distortion rate limit is limited to 'to Jane 312) End the fast-determined "Clock Tree Slow Touch Type" program. In the present invention, the main flow chart of the low-energy clock tree design is shown in Figure 3. Step (114) is re-injected to determine the rapid decision. The question of whether to meet the financial specifications is met in the step (31G) of the requirements of the design specification-in the step (31G), you ca n’t meet the design specifications, so it ’s difficult to return to the steps. Explained) The initial state before the 'in order to enter the optimization of the current design is indeed sufficient: miscellaneous library design specifications and timely 19 1244015 clock distortion limit. Figure X-for steps ⑽) Apply the rule of thumb to adjust buffer- Detailed flow chart of this kind, _scale bell sacrifice reading analysis, select. Appropriate _ should _ _ into, set _ _. The optimization method of the butterfly burst begins, to step _) to balance the load flip-flop The steps are the same as those in step ⑽), but only the flip-flops with the maximum clock delay and the flip-flops with the minimum clock delay are considered, not all the flip-flops are considered at the same time. This strategy can reduce the program operation time, and Balance the buffer load process to reduce physical fitness—Qing __ Difficult, as The above steps affect the clock tree structure, which is the clock tree structure that violates the specification of the butterfly, and the enamel canister. The clock tree maintains a feasible solution structure during the fine-grained process. In the optimization process, the temperature reduction τ 'is introduced, and the cooling tree is used to reduce the temperature to obtain the optimal power disassembly clock clock buffer combination. In this step, in order to reduce the conversion buffer, the clock skew rate in the design specification The same-level strategy in the clock tree is adopted to adopt the same-type strategy: in addition to solving the above-mentioned effects, the computational complexity of the optimization process can be reduced. Steps (4 free judgment after the simulated annealing algorithm Is the clock tree power consumption better than the previous stage? If it is true, continue with the flip-flop balancing operation of step (404), in order to obtain the best solution to reach the global best solution; if not, step (414) returns to the previous —The optimal solution buffer combination, and the optimization process ends in step (416). Figure 12 shows the virtual code based on the simulated annealing method. The low clock proposed by Ben Sheming Distortion rate and Power clock tree synthesis program, its steps can be divided into two major parts: 20 1244015: First, the violation will be in line with the state ... _ county post 0_, and then the next step. The step of optimization and the computational complexity of different methods are described as follows: 乂 In _ whether it is a feasible solution step, the turn-by-turn chat will be used to drag the Bip bow, and the conversion time will be transferred to the buffer state of the heart. Ai ’s connection information calculates its load size, and it ’s necessary to calculate the conversion time and power consumption. 箄 ~ a * Ten cars 乂 look up the meter. 〖Liyang Taosi Beixun. The number of clock pulse buffers is M, positive Inverter

Towel recording is about ten times lighter. Let the complexity of Zhu Kusi's calculation be the potential, and the computational complexity of judging whether it is a feasible solution is __. In the part of changing the feasible solution, the key step is to balance the tree structure, and load balance the buffer with the maximum delay and the buffer with the minimum delay time. Considering a complete binary tree, the number of last-stage buffers accounts for about one-half of all buffers, that is, M / 2. Considering the worst case (Worst Case), the rank of light f is in line with Wei. The computational complexity at this time is 0 (/ > * ⑽ + * * from 2) 〇 In addition, when performing the step of the optimization method, the optimization step of the present invention uses a simulated annealing algorithm to calculate the power consumption. Because this algorithm also uses the same way to change the buffer type— # Hierarchical Change 'for a complete binary tree containing M buffers, the number of levels (tree height) it contains is approximately It is necessary to determine whether it meets the design specifications. The complexity of this operation is 0 (P * (M + iV) * tog2M) In addition, when changing the size of the buffer, it must be considered whether it will overlap with existing buffer benefits and flip-flops. It violates the specification, so when each buffer changes, it can be judged as 3: the complexity of the step is 0 (from + state. Therefore, the operation required by the simulated annealing algorithm is a total of 0 (P * (Μ + Λ〇 * / 〇g2JVf). Based on the above analysis, the complexity of the clock tree synthesis 21 1244015 proposed by the present invention is ⑽ * + 0 (P 气 M + N) 2Hog2M). The invention of a clock tree that considers power consumption and minimum clock skew at the same time is equal to the method of setting a butterfly, _ a large integrated circuit called a tree can contain a bit of slowness, riding a touch to calculate the degree, and the converter The righteous step is to simultaneously replace the same level of the clock tree to achieve strict oblique control, so The power consumption target of the low clock tree will reach an approximate optimal solution. Apply the economic algorithm shown in Figure 3 to the tables of the cold shoes—sort them out and provide them as a test for the five embodiments of the present invention. The benefits of case 2 and 5 flip-flops; test case 3 includes a buffer and a flip-flop; _ Lion Post contains 251 Jing shirt 5_ 仏 Shun filial example 5 contains 821 buffers and 1 There are flip-flops. The table lists the power consumption and clock distortion of the original clock tree wiring list. Table 2 uses the algorithm proposed by the present invention to analyze each test case. At the same time observe the change in power consumption. From Table 2, it can be found that the circuit proposed by this algorithm can reduce the power of the wire after changing the wiring list. In addition, if you strictly design the clock distortion rate, Increase the power consumption of the clock tree, but it is still less than the power of the original ten structures. _: The towel is also available, and the buffer is added when the tree looks at the grid. , But Dan = " t clock L late and fetch small clock delay increase at the same time Under the circumstances, it will not affect the operation of the circuit. Yesterday, this U mentions a technique of inserting, removing, replacing, and shifting the buffer. Each method on the clock tree can be set slowly, which can be matched with the set The clock tree combination 22 1244015 Cheng Han calculation process quickly determines b τ as a kind of pain and value, so that the overall design conforms to the database design specifications, and the clock skew rate can meet the constraints. The fast decision clock tree of the present invention Buffer type and location manager presents-Dagger · Input clock tree structure to be processed, including the _Easy_Insert position of each line; database of input specific components, including input load, power consumption, clock delay , Output signal conversion time and other characteristics; initial state setting; when judging = force wood structure 疋 whether it meets the feasible solution of the design specification, if there is no doubt about load balance and buffer 彳 readable 'quick determination of the impact ^ when the surface is low The power consumption depends on the optimization η global optimal solution combined with the simulated annealing method. "When the combination of buffers with small power consumption cannot limit the equal changes and modifications made by the scope of the present invention, it will still be more than the above-mentioned. According to the spirit and scope of the patents claimed in the present invention, they should all be regarded as missing the essence of the present invention, and without departing from the further implementation of the present invention. Brief Description of the Drawings Figure 1 is an expanded view of a clock tree network. Figure 2 is a basic IC design layout flow chart. The input and output block diagrams of the implementation of the three-line calculation safty of the present invention. Schematic diagram of the power consumption analysis of the wiring structure in the lean warehouse. Schematic diagram of the connection structure of the buffer. The delay value of the buffer, the conversion of the output, and the parasitic Rc circuit connected to the meter by the power consumption of the meter look-up parasitic Rc circuit (b) are the electrical parameters of the Liaoning Light Road. The flow chart of the feasible solution steps is shown in Figure 9. Figure 9 is a schematic diagram of the clock tree load balancing steps, ⑻ is before balancing, and ⑼ is after balancing. 23 1244015 Figure 10 is a flowchart for quickly determining a low-energy clock tree buffer combination. = 十- Model Flowchart of low energy clock tree optimization algorithm based on annealing method. The eleventh is a virtual code of low energy clock tree optimization algorithm based on simulated annealing method. [Description of main component symbols] Conventional symbols (10) pads (12) clock tree network (14) sub-circuits (16) flip-flops (18) buffers (52) start (54) placement (56) optimization of clock beam network synthesis and Analysis of the winding table kization buffer insertion method (58) Inserting the buffer to adjust the placement position (60) Whether the timing limit is violated (62) Winding (64) Ending the symbol of the invention 〃 (102) Clock tree synthesis grid list (104) Clock distortion upper limit (106) Buffer, flip-flop power, timing database (108) Check that the original circuit design is a design specification? (110) Turn this circuit into a feasible solution (112) Quickly seek for the type of buffer Best feasible solution (114) Reverse design specifications or increased power consumption (U6) Return to the previous state (118) Use the rule of thumb to adjust the buffer size one by one 1244015 (120) End of the program / (152) (154) buffer (156) flip-flop (162) (164) buffer (166) parasitic RC circuit (202) Passage (204) to the last stage flip-flop (206) (212) whether or not a feasible solution (208) the program ends (210) clock tree distribution g equilibrium inside the end member (214) Program? -

(252) Buffer A

(254) Buffer B

(256) Buffer C (258) Buffer (302) Circuit feasible solution (304) Buffer removal step (306) Determine the buffer type (308) as a feasible solution based on the flip-flop load. (310) Adjusted to the maximum buffer Repair (312) End (402) Start of the optimization step (404) Balance the distribution of flip-flops (406) Does the signal skew decrease? (408) (414) Reply to the previous state (410) Simulated annealing (412) Does the power consumption decrease? (416) End of execution 25 1244015 Attachment I Table I. Test example analysis Test case 1 Test case 2 Test case 3 Test case 4 Test case 5 Number of buffers 7 30 113 251 821 Number of flip-flops 123 500 1234 5000 10000 Original circuit power consumption (m \ V) 4.9822 21.4612 52.0567 210.505 419.8569 Maximum clock delay ㈣ 0.6404 0.8741 1.1298 1.2143 1.5029 Original circuit clock skew rate (ns) 0.0035 0.0140 0.0204 0.0547 0.0586 1244015 Appendix II Table 2. Optimized power of test examples 2. Clock skew analysis test case test case test case three test case four test case five test one clock skew rate limit (ns) 0.005 0.02 0.05 0.1 0.2 maximum clock delay change -12% + 14% + 33% + 15% +90 % Optimized power consumption (mW) 4.373 18.728 45.038 192.383 359.918 Power reduction (%) 12.22 12.73 13.48 8.60 14.27 Test 2 Clock distortion rate limit (ns) 0.003 0.01 0.02 0.05 0.1 Maximum clock delay change -13% + 1% +7 % + 14% + 60% Optimized power consumption (mW) 4.610 19.858 51.434 195.837 400.698 Power reduction (%) 7.47 7.47 1.19 6.96 4.56 Test three clock skew limit (ns) 0.002 0.005 0.015 0.03 0.05 Maximum clock delay change -12% -6% + 4% + 4% + 12% Optimized power consumption (mW) 4.794 21.394 51.723 204.903 419.832 Power reduction (%) 3.78 0.31 0.64 2.66 0.01

Claims (1)

XX Correction 6 · 24 1244015 X. Patent application scope ^ Considering a clock tree synthesis method with low Mm curvature and low energy consumption, the steps include ... (): 二 :: 理 的 _Synthetic computer wiring list, Contains the electrical parameter information of each line and the buffer gain sequence and power database information; (b) The upper limit of the timing specification of the input clock is skewed; Set the calculation tank to the clock tree from the auxiliary root to the clock tree Each: the conversion time of gas and positive and negative $, and the load value of each buffer, determine whether the buffer combination meets the design specifications of a particular database; ⑼ Xie Heng, clock tree, and E Fanzhi New, delete the situation where the distortion rate of the bell is greater than the design limit; (the power consumption of the tree is slow_____________, the general__; to get the full power consumption of the clock tree (the rule of thumb for the simple library of paste, simple drafting The optimization based on the annealing method is to find a combination of buffer connection methods on the clock tree, and the domain is the best solution. 2 · 1 Apply 4 Benefits $ 丨 Steps of Remuneration Consider the light weight and low energy consumption The time domain synthesis method, the design specification of which consists of: The characteristics of ϋ ϋ 'to determine whether the conversion time of the input signal meets the Lai specification; ⑼ For the characteristics of the coffee 判断 to determine whether the fine input is in line with the design specifications; Lai Qi Chu' should be a sacrifice round coffee, and the difference method is used to calculate different buffers Clock delay and output signal conversion time. 3 'As described in the patent application side item-when Saki considers low clock distortion and low power consumption 26! 244〇15 The clock tree is green, and its clock tree is aging. Chi Cheng contains: ㈤ farming scales rely on the sun wheel μ material scales, tree riding wealth reversing devices rely on the time to collapse-_, like this _ domain shirt targets are finely connected) _ «back-level buffers are loaded by the positive Inverter, in order to consider the overall clock delay of the minimum 7 M flip rate, so delete the output load after the bell woman-Saki; c) Gang Zhong axis, her _ ring clock clock distortion rate, so balance the wheel of the buffer The output load will effectively solve the limitation of the clock skew rate. In addition, balancing the load can improve the power consumption of the E-switching and the N-switching. 4. ^ Please refer to item 1 of the patent scope—a clock synthesizing method that considers low clock skew and low power consumption synchronously. The steps for quickly seeking the buffer combination include:,, last in the scale tree clock—hierarchical buffer For the load, choose the same: change all the buffers in the clock tree to the one c = the meaning of all material buffers, choose to meet the design specifications and minimize the consumption ', and this is the quick steps to find the buffer combination step solution. 27 1244015 Power Consumption, (C) Applying conventional techniques to simulate annealing, I am looking for the best combination of buffers, in order to consider the strict clock distortion limit and the operation complexity of the P-low / Bayer method. The change of the buffer combination takes the hierarchy as the unit, and seeks the local optimal solution of power consumption; ⑼Improve the load flip-flop balance of the next level of the clock tree again, and re-apply the simulated annealing method to find the combination of clock buffers. Power > Xiao Consumption Global Best Solution. Eleven, schema: as the next page 28