TW200428240A - A clock tree synthesizing tool synchronously considering low clock skew and low power consumption - Google Patents

Abstract

The invention brings up a method, which is applied with the skill of insertion, removal, swap and shift buffers to quickly determine the type and location of every buffer type in the clock tree , and pertinent to the combinational design process of designed clock tree to quickly determine the type and location of skew buffer, making the entire design meet the database design specification and the clock skew meet condition limitation respectively. The computation tool of the invention that quickly determines the buffer type and position in the clock tree comprises the inputted clock tree structure to be processed containing the information of each circuit and buffer insertion location, the database for inputting specific component containing the characteristics of input load, power consumption, clock delay, conversion time for output signal, etc., and initial state configuration. Determine if the lock tree structure complies with the feasible solution of design specification; if no, apply the load balancing and buffer balancing methods to get a feasible solution. Quickly determine the buffer type to reduce the power consumption of the clock tree. Apply the optimal technique integrating simulated annealing method to acquire the global optimal solution of the integrated buffer with minimum power consumption.

Description

200428240 IX. Description of the invention: [Technical field to which the invention belongs] The present invention is «Computer-aided for the synthesis of high-speed super large-scale integrated circuit towels and low-power trees and clock-tree circuits. Also," Ten 'is especially relevant to a given buffer || timing and The power database towel is appropriately inserted, removed, replaced, and shifted. The clocks on the clock tree are all related to the technology of the clock tree silk god and the money rate. [Previous technology], high-speed Jingda seam _ Lu Ji Liucai, h a fresh (aGekF-like rate) as an indicator of data processing speed. In the process of transmitting each signal, it is necessary to maintain the signal integrity as much as possible, that is, it must meet the following timing design specifications: reduce as much as possible: clock delay (clockDelay) and clock skew (clockskew), and Specific buffer database, to provide its design specifications. The maximum time it takes for the sender to send the time to the receiver of each synchronization system. Shortening the clock delay can help speed up the transmission of the clock signal. In other words, it is possible to improve the circuit tweet. If the value of the path difference between the clock signal phase tree clock sender and any two receivers in the clock tree is too large, the clock signals received by the receivers will not be synchronized, which may cause signal distortion and logic malfunction. For the special buffer, the input signal fa1 (T position time) and output load have tolerable upper and lower limits. When the input signal conversion time or output load is greater or less than the upper and lower limits, the As a result of the unexpected operation of the buffer, the operation status of the buffer and flip-flop on the clock tree must meet the design specifications. In the case of the ultra-micro integrated circuit deep sub-reading technology, the timing signal is considered in the interconnection line (Interc_e's E far greater than that on each component). 5 200428240 In order to reduce the design of the clock tree synthesis, Line delay. In the conventional technology, the first design method is to shorten the length of the clock tree line as much as possible: the longer the line length, the greater the time delay on the line, and the power consumed by the signal conversion in the line is also At the same time, in general, in the history of large-scale integrated circuit layout design, shortening the length of the line is often the first priority to reduce time delay. W The second design method is to insert a buffer at an appropriate position on the line. Not only can the line be segmented and reduce the secret 'New_Chong !! Ride_Capacity, which can reduce the equivalent load of each hiding path', so that the fast charging of the signal can reduce the rise time, and reduce the delay of the line. In terms of circuit miscellaneous power considerations, the reduction of the input signal conversion time will also reduce the power consumption of the components. Figure-is an expanded view of the clock tree network, and the input pad of the clock signal is the tree root ( Root), the clock signal receiving end of the flip-flop 16 is called the leaf cricket. From the pad Egen) to the flip-flop: the clock signal reception of the 16 (Liao Ye), including buffers and connection lines along the way, constitute -A complete path to ath), the accumulated buffer and line delay are the path delay (touch y) in the figure, the two paths are to the root B1. ^ F13, and the path delay difference is-group clock is positive The curvature is inserted in the appropriate position on the 里 tree network. In addition to reducing the time delay, the time delay can be reduced by selecting different buffers. Clock skew for each path. Figure 1 is the 1C design layout flowchart of Baizhi Technology (US Patent 5,564,022). The traditional layout design rides into the field and places 54 Wei Line 62.彳 _ 集合 ㈣ ^ §㈣her) The tool generates-group description_ compilation leisure and its connected grid wiring list (aged, and then puts standard units of the power grid ,,,, and various types of logic gates ( Standard Cell) is placed on the chip at the selected position of 20042004240. Usually, the distance between the positions is related to the connection relationship of the components in the grid wiring list. The purpose is to reduce the length of the later winding. The 62 windings The actual connection is made according to the result of the placement. In today's designs, clock tree synthesis steps 56, 58 and 60 are added to the layout design. Step%

Optimize the synthesis and winding of the clock tree network, so modify the content of the logic synthesis grid routing table. In addition, step 56 also includes an analysis hardware description processor (Hardware Descriptian Processor), which analyzes and synthesizes the optimized buffer II insertion method in the grid routing table according to the given timing design specifications, and its buffer is added to the power supply. _ The relevant positions of other components in the line table can be used as a reference for the physical material (Physieal Desi㈣) of the bottom n buffer.

Because the original logical synthesis grid wiring list describing the connection relationship of each component has been properly placed in the private step, the "inserted buffer" will affect other components that have been placed. @This step · The position of each component must be readjusted . In addition, because the insertion of the buffer segmented the county's connection from the clock signal sender to each receiver, the steps of the completed clock tree network must be modified to maintain the minimum clock delay. The adjusted buffer position cannot be too far from the originally selected optimal position, so the buffer will have priority over other components. Step 60: Calculate the path delay from the time input terminal to the flip-flop receiver to determine whether the established clock tree network violates the timing design specification. If it meets the timing specifications, you can adjust the placement of each element including the buffer, such as ‘fine_nazhang’, and adjust the physical winding of the circuit. One type of buffer, but does not take into account the actual design, ibrary) has a country-size non-standard photo editor type for 'However, as shown in the clock tree network synthesis process in Figure 2, all the inserted buffers are used only Same buffer timing database (Timing choice, so it can not make the clock tree network 7 200428240 timing control more flexible to meet the timing design specifications, which is its main disadvantage. If you choose the type of each buffer on the clock tree, The delay value of each path will be adjusted to cover the clock T curvature to meet the timing design specifications, and to reduce the dynamic power consumption in the clock tree appropriately. Usually, different types of buffers in the unit design database are found, and their area sizes It may be different, so the ability to drive the next stage circuit is also different. Generally, a buffer with a larger area can drive a larger load than a smaller area, which accelerates the signal rise time of the load. However, the larger buffer itself also With six major delays and large power consumption, how to take a compromise between clock delay and power consumption is one of the key considerations of the algorithm of the present invention. When selecting the buffer type, it is assumed that there are n types of buffers that can be selected, and m buffers need to be inserted on the clock tree network. If a carpet search method is used (Εχ 如 姐 ^

Search), you must judge all! Among the combinations of buffers, which one can obtain the minimum clock delay and meet the clock skew limit? Generally speaking, when considering the issues of buffer insertion and buffer type selection at the same time, the establishment of the clock tree network will repeatedly place and circuit-level simulation (Circuit simulati) based on the results of the timing constraints. Therefore, the ic design process cap in Figure 2 will take a lot of calculation time. Therefore, for a fresh cell type ultra-large integrated circuit design tool, how to quickly find a suitable set of buffer types in a poor material library from a given buffer timing design during the clock tree circuit synthesis stage to reduce The simulation time, which meets the clock skew design specifications and minimum power consumption, occupies a very important position in the clock tree circuit synthesis tool. In the known technology, (by A. Vittal, M. Marek-Sadowska, "Low-Power Buffered

Clock Tree Design ,,, IEEE Tmns · on CAD of Integrated CAS, Vol · 16, No. 9, ρρ · 965-975, 1997 $), should be relying on Renlin_Square construction H flipping area and 200428240 power consumption The best solution; the technique of inserting buffers is proposed in the conventional technology to reduce the clock skew of the clock tree (by J. L. Neves and EG. Friedman, "Design Methodology for Synthesizing Clock Distribution Networks Exploiting Nonzero Localized Clock

Skew, "IEEE Trans. On VLSI Systems, Vol. 4, No. 2, pp. 286-291, proposed in 1996); and the conventional technology proposes the application of the technique of inserting buffers to reduce the difference between buffers and reduce the short-circuit current. To avoid additional current consumption (by S. puiieia, v. Menezes and LT Pillage, "Low Power IC Clock Tree Design ^ Proceedings of the IEEE Custom Integrated

Circuits Conference 1995, pp. 263-266); other conventional technologies (by KM Carrig etc A New Direction in ASIC High-Performance Clock Methodology / 5 Proceedings of the IEEE Custom Integrated Circuits Conference 1998, pp. 593_596) Use insert buffers and reduce unnecessary windings to reduce noise and power consumption. However, in the above algorithm, only the same kind of buffer miscellaneous is used, which is inconsistent with the actual circuit design process. In addition, the return, money, and relocation of the clock tree are not used. It is impossible to achieve the optimal timing and clock connection in the clock tree. Buffer combination for power consumption. Other U.S. patents US66 · 63 application clusters insert buffers to achieve the same clock delay. _〇 Helps the application of hierarchical slow_minute__ tree clock han rate, face-to-even balance clock tree low _ distortion rate, US6367060 application balance All levels of buffers are in compliance with the design specifications. 7 The noodle tree selects the depth of the cypress tree to reduce power consumption. The above patents apply the early-buffer insertion technique or partitioning secret to the clock tree for the power consumption of the clock tree. The goal of a low clock is, however, unable to come up with _kinds_ effective buffering algorithm for multiple buffer types ^ application of removal, replacement and shifting techniques to reduce clock tree clock skew. Alas, since the present inventor has applied for a patent of the Republic of China "to quickly determine the type of buffers on the clock tree and meet the requirements 9 200428240 sequence design rule sharp synthesis tool", the computer-aided design of the high-speed supermarine dragon Wei Weilai circuit is appropriate Each slow-leak axis on the time of selection meets the maximum tree-clock delay and coupled tenderness, but its buffer operation only provides a way to replace the buffer, and there is no optimization analysis for the impact of power consumption. [Summary of the Invention] The purpose of the present invention is to propose a method for inserting, removing, replacing, and shifting buffers on the clock tree, which can quickly synthesize low-energy and high-speed ultra-large integrated circuits. The post of Lai Ling, thief __ Gu Demian, in addition to reducing the consumption of the clock tree, and the clock scales can be simplified to scale design specifications. The clock tree synthesizes miscellaneous wealth, and relieves the ill-fated health of the crane. It is implemented in two steps: the winding of the body and the insertion of the buffer in the traditional chip design θ. The information entered at this time includes the list of machine-connected lines, the parameters of each section of the clock tree towel, and the power rate and timing database of various types of buffers to calculate the line delay, buffer delay, and buffer of the clock tree. Data such as device power consumption. Through the circuit synthesis tool for quickly determining the buffer placement position and various types of circuit synthesis tools provided by the present invention, the minimum output power can be achieved after the update and the clock tree power grid line list that meets the clock distortion design specifications. The reason why the method proposed by this u can achieve the purpose of low-power clock tree synthesis is that it can shout _ the position of each buffer and its divergence _, its characteristics are ... ， Record the relationship between the front stage and the back stage of each buffer. For each optimization, you can calculate the clock delay and power consumption information of each buffer in linear time. Design specifications. The present invention uses empirical methods to optimize the adjustment of buffers for each layer of the clock tree, in order to achieve 10 200428240 to the minimum power consumption and to meet the design specifications of strict clock distortion limit; (3 ) Applying the concept of Heuristic for optimization, instead of using the exhaustive method of carpet search, it can save the time to find the best solution. Because the clock tree has a limited number of buffers, but the placement position is not limited. After the invention uses the above heuristic algorithm to determine the buffer placement position, the simulated annealing algorithm (Simulated Annealing, SA) can be used to obtain the local optimum. Good solution (Local 〇ptimai Solution) 'The global optimal solution (Global Optimal Solution) can be obtained through load balancing technology; (4) Within the range allowed by the equipment, the software tool developed by the present invention can handle High-speed super-large integrated circuit of ten thousand logic gates. In a specific embodiment, the method for quickly determining the position and type of a buffer with low energy consumption according to the present invention includes the following steps: (1) inputting a clock tree grid grid list to be processed, including information of each line and buffer insertion Position, in addition to the buffer database and flip-flop database, to provide a record of the calculation of the process; (2) the initial state slave; (3) whether this age meets the design specifications of the clock distortion rate, and the circuit operation Whether it will violate the limitation of the component database; ⑷ If the specifications are reversed, the buffer insertion, removal, replacement, and shift steps are performed to obtain a feasible solution for clock tree synthesis; (5) Heuristics will be applied to the feasible solution The algorithm is combined with the simulated annealing algorithm, and 2 is the best solution that takes the minimum power consumption and meets the design specifications. [Embodiment] As mentioned above, the object of the present invention is to propose a method for quickly determining all the positions and types of slow and cry in the clock tree. The clock distortion rate is set one by one for timing design specifications. Because the actual buffer power and timing database provide limited choices of buffering, the best optimization of the silk surface is rarely asked. _ Fang cut for the carpet money and the type 11 200428240 Change the type of each clock and compare the type of each buffer. Power consumption and clock skew rate, until the final selection of the best buffer view combination that has the smallest power consumption and meets the clock skew rate timing design specifications. 'The main disadvantage of this method is that: ⑴wave f; (2) There are no steps such as inserting, removing, and shifting the buffer, and the program cannot easily find the best solution.

Based on the above reasons, and to solve this problem, this hair warming exhibition-quickly determine the buffer tree, remove, sickle, lion, side, etc. in the clock tree) will design the original clock tree that does not meet the design specifications. Modify the steps such as punching, removing, replacing, shifting, etc .; (2) Gu Ping_Lai_'s Qifu algorithm, quickly and efficiently determine low energy consumption, minimum clock delay, and clock distortion. Design specifications for optimal buffer locations and

In step 114, it is judged whether the clock tree still meets the design specification. If it is violated, the step is added back to the pre-state. If it is not violated, the algorithm is optimized in step 118 to reduce the discerning cost. To step 120, the present invention The low-energy clock tree synthesis algorithm ends.面 组合。 Face combination. FIG. 3 shows a block diagram of a system according to a specific embodiment of the present invention. Enter the clock tree of the specific embodiment to synthesize the power grid wiring table 电网 2, the hour_curvature design specification upper limit trace, and the power and timing dragon library including buffer II and positive and negative ，, and then check whether it meets the design specifications and the distortion rate through the steps. Assume that the ship is violated. Go to step m. Adjust = the synthesis method of the bell tree makes it a secret design job. Instead, perform step ml2 and replace the buffer J state to quickly reduce the power consumption of the clock tree. However, this step has the risk of violating the design specifications. Therefore, the power analysis of a specific database in the process of low-power bell-tree synthesis scale method can provide different buffers for the power consumption characteristics of individual designed data buffers. N Select the broken wire. Figure 4 shows specific buffers. 200428240 Poor materials storehouse, as if touching the countryside _, _

152, and according to the number of B-level buffers the average load c-level flip-flop said. The power consumption diagram in Figure 4 is the total power consumed by the clock tree, including the operating power consumption of the buffer, the operating power consumption of the flip-flop, and the clutter when the line signal is converted, where the silk power is the taste of the clock tree.建 域 #Material Design Specification 'will not be discussed. If it is slow, the conversion time of the lost money number or the output load cannot be obtained through the database look-up table (T. It is known that a known input will be used. TU Tiger conversion time and load capacitance value to find the power consumption values in the four corners, Then the polynomial linear interpolation method (Polynomial Interpolation) is used to calculate the approximate buffer power consumption by interpolation. The present invention uses the empirical equation A, y: M + melon + to find 4 through the four corners. , C, /) four constants, and then the actual input signal conversion time and output load solution. CL is the youngest person who reads, has the most discerning and most secret wheel power, and has the second smallest input load, the second smallest power consumption and the second smallest driving ability. It is said that the power consumption is more than the power of riding. Consider Figure 5, "T Zhongshu" "A, B, c three levels, where A level is the main driving buffer for mosquito species" Let CLKBUFX8; B ride is Wei buffer [Variable Wei Chong surface and its Figures are the X-axis and γ-axis variables in Figure 4. The c-level is the load flip-flop, and the fixed flip-flop surface is fixed. Qiu Ding's flip-flop is one. Its load can be estimated as the flip-flop input capacitance plus the average Line load. Buffer 152 is the main driving buffer in level A, and buffer 154 is one of the level B buffers. The level B buffers can be fixed at most.

Through the presentation of this power consumption diagram: it can be found that its power consumption is a concave distribution. In the case of a small number of B-level buffers, the input conversion time of the flip-flops is increased due to the increase in load, and it is designed into 13 200428240. Although you can increase the power consumption of the flip-flop part I through the setting of 0, and ... reduce the input signal conversion time, but the face of the larger size i said above for the specific database power consumption W part of the power Consumption increased slightly. Calculate the data scale, _ ^ slightly different characteristics of the fortune, "known as a buffer selection algorithm. The way = = = Considering the specifications of the% order design and the calculation signal from the input to the output Continued on the full path, slow_delayed disks are described in detail. The type of the replacement buffer at this time only affects the buffer delay, and has nothing to do with the line delay; Buffer the parasitic RC circuit connected between them, and its transfer function is Qing Tuzheng ’s RSPF format line electrical parameters, where ρmode compensation, ⑽) is the first three-order Taylor expansion approximation, which can be considered as a slow The equivalent line load of the punch 162, the total line load is C1 + C2. The pin of this line is docked with zero in4〇_pin) The delay can be represented by a simple model, and the line delay is R2 * C3. To simplify the program, The computational complexity is such that the line load = the physical winding length is in a proportional relationship, and the calculation of the buffer delay is related to the load of the buffer, and the effect of line delay is ignored, that is, the buffer loaded under the same buffer, which The input delay time is equal. The buffer delay value and the output signal conversion time can be obtained from the tables of each buffer timing database. As shown in Figure 6, the polynomial interpolation can be used to find the approximate buffer delay value. The method of obtaining the output signal conversion time is the same. (2) Replace the type of the buffer, and relatively change the value of the slow input capacitance (Pin Capacitance). As observed by the output of the previous level of the buffer, it will be changed to 14 j, and the delay of the device will also change. It changes accordingly. For example, the equivalent load of k buffer 162 is changed to the type of k buffer 162 in Figure 7 for the change of buffer_. Therefore, both buffers ⑽ and ⑹ must be re-checked. ^ 1 (3) For the shift of the buffer, The change causes the load of the slow balancer to be cast to t, so the delay of the buffer will also have an impact. For example, in Figure 6, if the relative position of the buffer theory and the buffer pirate I64 in the physical design is changed, the equivalent of the buffer term is changed. Load, ^ one buffer 162 and 164 must re-look up the table to calculate the delay. ⑷ Synchronous system flip-flop is the load of the last stage buffer 'Usually a buffer will connect multiple flip-flops, in other words, the overall flip-flop Quantity ratio The number of back-stage buffer ifs is large. Figure 8 is a flow chart showing the low energy consumption of the present invention to quickly determine the buffer position in the clock tree, the meaning calculation tools, and the original output field secrets to meet the design specifications. The fork, and the pros and cons are located at the clock tree position 204. The clock tree load balancing step and the nucleus team must perform path delay calculation and design specification inspection after the phasing. Steps 2⑽ and 212 are the test positive judgment programs. The detailed process of each module is described in the following. The first is the check-judgment program 206 and m, which contains two observation points: ⑴ in the database. _ Xiao consumption of the buffer and the calculation of the clock extension meaning. Determined by two indicators: input signal conversion gate ^ output load size. Therefore, for the buffer at the previous level of the target buffer, changing the position or surface of the target h buffer will cause the output signal conversion time of the previous level buffer At the same time, the conversion time of the input signals of the components (buffers and flip-flops) in the database has-limited upper and lower bounds. If the input gift is less than the allowable lower bound, or The conversion time of the input signal is greater than the allowable upper bound, which will result in the inability to correct the copper during the operation. 15 200428240 This phenomenon is called a violation of design specifications. The bins are counted w_, for the components connected to the target and the buffer,. Lost above ^ tr material village regulations, lower Wei, if Chao Jian-Fan "will cause a buffer = Gata, in this case Jiao Fan sells digital circuit rights, 8 bell clock is the longest one ... heart, $ After the clock signal is transmitted to the chip via the CLK pin, it is transmitted to the sequential logic through the% clock tree. The logic's delay time is getting closer-fatal is better, ㈣ ㈣ ㈣, the difference between the clock signal's arrival and the short delay time needs to be within -In the fixed range = the longest delay time and the highest standard in the secret design is called the zero clock distortion rate, so this verification step does not determine whether the clock clock distortion rate of the circuit is _ yoke. The steps of this verification judgment program will become the commonly used modules in the present invention. The solution must be improved as much as possible. Wu Chengshao's "The implementation of the coffee, age judgment program is comprehensive, in the process of losing her solution, she flips her edits to the side of the ship and consumes it. For the clock delay of the buffer, the output signal conversion Time has a significant impact. Reasonable load Γ avoids narrative specifications. Ke satisfies Wei Kui ’s "Lost in Money __ Design Rules. In addition, it has strict restrictions on clock distortion, and adjusts the buffers of the same class in the clock tree." The load, the clock delay effect is approaching-due to the overall clock delays. The _step outline is _____, "rate-reliance formula, for strict time-of-day positive curvature limit,-grade slow_ clock delay caused by _ will violate the clock skew limit, so the original clock tree design exists-Na and Other pros and cons on the clock tree are not on the same level, which will cause the clock distortion rate limit to be violated. To avoid this problem, this step will connect 16 200428240 'pounds to the position of the clock guard on the day clock. In addition, in order to consider the load balance of the buffer, when selecting the buffer to reconnect the flip-flop at the same time Consider the load capacity of the previous stage and the large load! In order to buffer the delay effect to meet the strict clock skew limit.

Step 210: 'Zhuang Shu Decoration Positive and Negative Steps _ Measures taken when Man Lin Zhong's Distortion Rate Cannot Be Taken' Flat Scale Bell Shooter's True Gamma Shot Reduces City Green People's Pins to the Buffer and Flip Clock Besides the delay, the power consumption of the buffers and flip-flops can also be reduced. As shown in Figure 9, the two buffers A and A are loaded as 254 buffer B and 256 buffer c, and the input load calculated from the output of buffer A to the subsequent stage is smaller than the maximum buffer type that buffer a belongs to. The load is calculated, and the round signal conversion calculated for the miscellaneous slope of the buffer A and the output of the load is _ 'all satisfying the buffer U and the buffer red which belong to the buffer is difficult to shoot ^ incoming __ 间' At this time, it is said that the buffer modules A, B, and C on the clock tree have feasible solutions. Consider, "... below C, and buffer theft, where buffer B is driven by buffers hd, e, F, and buffer C is driven by buffers G, H, j ,; κ, l, The actual buffer from the current buffer to the secondary buffer is considered to be near the scale, and Wei slowly reads the negative age data, so the output of buffer B is less than buffer _c, which will cause buffer The clock delay on B has a small impact on HC, and the time delay on D, E, F is greater than _g, H, I, J, K, L,

Will meet the anti-strict time slot alcohol design specifications. In this step, in order to avoid the existence of this type of structure, the scale of the clock is too large, so the county's strategy of negative cake balance is in line with the design. If there are two or more buffers on the same level in the clock tree, the two buffers with the largest round load and the smallest output load are selected as the correction target. It is assumed that there is a buffer in the secondary buffer connected to buffer C. The load L0ADGK caused by _ κ, A is slowly touched by the load LOADbk after B is connected to buffer K 17 200428240, then __ newly connected buffer κ and buffer C are connected to buffer B and buffer K. After this operation, it can be ensured that the new output load of the buffer β will be less than the reduced input load of the Lin HC, and the fine load of the two buffers will tend to be balanced. The result of the load balancing is shown in _) . If you change the secondary component of the slow-clog buffer c to a flip-flop, the judgment basis is the same. The application of this load balancing adjustment step is to go through the leaves of the clock tree toward the root of the tree, consider the same level at the same time, and check the step of the cake design specification after the adjustment. If it is still not possible, return to the step to perform load balancing. If the design specifications can be met, the step of adjusting the circuit to a feasible solution ends 214. 2. Right Steps for Best Solution Figure 10 is the detailed steps for quickly finding the best solution for step m. For the clock tree design that meets the design specifications and the clock distortion rate, the method of quickly reducing the power consumption is performed. Enter step by step the clock tree that originally meets the design specifications, or adjust the step to the symbol = 时 _ 'grain material fiber_㈣ side towel, material handling ^ power consumption to reduce unnecessary buffers is — A feasible method, but in order to meet the clock limitation ', only two types of buffers are selected as the target for removal in this step: ⑴ In the clock tree ❼, all buffers are on the common path to the root of the tree. The unbranched buffer is considered as the goal of the buffer removal step. Because the removal of the buffer will cause the failure of all flip-flops, it can avoid the design specification that violates the clock distortion rate. However, removing = The puncher must consider whether the front-stage buffer has the pure ability to drive the lower-level components. It is the design of the library. _ Violation __ If one of the above violations is caused, __ must exist in Dingli. (2) For the buffers of the same level on the clock tree, if the connection status of the former and secondary buffers 18 200428240 is similar, it is regarded as the goal of removing the buffers in this step. However, this operation involves elemental dumping. It can be removed only after the previous level, New Zealand ’s Xu Zhenzai, and the ship ’s ship meet the design specifications of the database. From the time when the clock is fired to the last level, the level is positive and negative. After removing unnecessary buffer steps through step 304, its clock tree architecture is the basic architecture that provides the optimization steps. In step 306, the present invention provides a kind of buffers on the fast clock clock tree. According to the positive illusion of the last-stage buffer riding on the clock tree, the size of the last-stage buffer is changed one by one and applied to All buffers in the clock tree; the final step is to apply check notes to observe whether it meets the database design specifications and the clock distortion limit. If one of them fails to meet the design specifications, the steps are to increase the buffer type by one level. When recalculating, the clock delay, input signal conversion time, and output load of all levels of buffers are all in line with the design specifications of the library and the curvature limit is reached. Step 312 ends the program for quickly determining the clock tree buffer surface. In the main flow chart of the low-energy clock tree design proposed by the present invention in FIG. 3, step 4 is re-verified to quickly determine whether the slow-charging determined by the clock tree buffer test step cap satisfies the design consumption. One of the leaving conditions in step 310 is All the buffers have been adjusted to the maximum and still can't meet the design silk. 'That's why in step 116, the type of buffers is adjusted back to the initial state before entering the step. Library design specifications and clock skew limit. A detailed flowchart of adjusting the buffer type step by step by applying the rule of thumb for step 118. According to the characteristics of the database of the round-robin rolls, through the analysis of the trade-off between power consumption and clock delay, choose the buffer benefit of k to provide buffer insertion and replacement. Steps to use. Steps are optimization calculations. 19 200428240, '° ^ Step 404 is the balancing step of the load flip-flop. It is similar to the operation of step 21G, but only the flip-flop with the maximum clock delay and the flip-flop with the minimum clock delay are considered. Inverters, rather than all flip-flops, are considered at the same time. This strategy can reduce the program operation time and reduce the overall power consumption by overbalancing the buffer load. Steps are carefully judged, in order to avoid the above steps, the remaining axes of the clock tree are shouted and lost, and the successor who violates the rules of the Komaki shell],, and 2 return to the state of the clock tree by step 408 to ensure the optimization process. The clock tree maintains a feasible solution architecture. ^ Based on the application of conventional technology to simulate the optimization process of the annealing method, the temperature _ and the 'A' parameters are introduced. 〇 · 9 The clock tree that reduces the temperature to obtain the best power consumption solution is slowed down = U in this step ^ In order to reduce the type of transformation buffers, the clock distortion in the design specification is ^ I ^ The same-level strategy is adopted for the same level of buffers in the day-to-day clock tree. In addition to solving the above effects, the computational complexity of the optimization process can be reduced. . In step 412, it is judged whether the power miscellaneous of the clock tree of your domain is lower than that of the previous stage through the simulated annealing. If it is true, continue the step-by-step flip-flop balancing operation in order to obtain the best solution to reach the global best solution; if not, step 414 returns to the buffer combination of the previous best solution, and ends the optimization over-step in step 416. Figure 12 is the virtual code of the optimization process that relies on the pseudo-basic method. The steps for synthesizing the low clock distortion rate and low power clock tree proposed by the present invention can be divided into λ 卩 6. First, the circuit that violates the material specification is changed to a clock tree that conforms to the specification; The tree performs the steps of optimizing power consumption and optimizing clock skew. The computational complexity of the algorithm is described below. If J, J is a feasible solution step, it will start from the input pins, calculate the input conversion time on the buffer one by 20, 200428240, and calculate its chastity according to the connection data. Output information such as conversion time and power consumption. Let the number of buffers in the clock tree be m and the number of flip-flops be N, where the number of flip-flops is about tens of times of the buffer record. Let the complexity of the database look-up table calculation be 0 (P), and the Huqi transfer can be converted to the material level (the key step of the threat police in changing the feasible solution part is to balance the tree structure. The buffer and the buffer with the minimum delay time for load balancing operation. Considering a complete binary tree, the number of buffers in the last stage is about half of all buffers, that is, fiber. In the worst case (Worst Case ) Consider and adjust the number of permutations and combinations of 酽. At this time, the computational complexity is 〇 (P * (M + N) m2) 〇 In addition, when performing the optimization method step, the optimization step of the present invention uses The simulated annealing algorithm calculates the power miscellaneous. Because the algorithm also uses the same P luxury layer to change the way of slowing down the charm crane, 'Yes-complete with M buffers: meta tree, the number of levels (tree height) it contains is approximately % 2M. For each replacement step, it is necessary to determine whether it meets the design specifications. The complexity of this operation is ___. In addition, when the size of the buffer is changed, it must be considered whether it will overlap with the existing buffer and flip-flop. And violate the norm, so When the buffers are changed, it can be known that the complexity of the steps is equal to the calculation complexity required by the simulated annealing algorithm. Based on the above analysis, the clock tree synthesis / ¾ different method proposed by the present invention, In the worst case, the computational complexity is ⑽ + state * from 2) + 〇 (P * (M + N) 2 * log2M). Applying the proposed clock tree synthesis algorithm that considers both power consumption and minimum clock skew in the present invention, 'buffer operations of selecting, removing, replacing, and shifting, because the clock tree in the ultra-large integrated circuit 200428240 may contain numbers 10,000 buffers. In order to consider the complexity of the calculation of the program, the step of replacing the buffer is to simultaneously replace the same level of the clock tree to achieve strict clock skew restrictions. Therefore, the goal of reducing the power consumption of the clock tree will reach the approximate maximum. Good solution. Applying the algorithm flow of Figure 3, the table-sort out relevant information provided as a test of the five embodiments of the invention: test case-contains 7 buffers and 123 flip-flops; test case 2 contains 30 buffers And 500 flip-flops; test case 3 contains ΐ3 buffers and 正 flip-flops; test case 4 contains 251 buffers and a flip-flop; test case 5 contains milk buffers and face flip-flops Device. The table lists the power consumption and clock skew of the original clock tree wiring list. Table 2 uses the algorithm proposed by the present invention to analyze each test case 'by limiting the clock distortion rate while observing the change in power consumption. From Table 2, it can be found that the power of the algorithm proposed by the present invention can reduce the power miscellaneousness of the circuit after changing the wiring list. In addition, the right curvature of the π clock is strictly ignored, which will increase the power consumption of the clock tree. However, Still smaller than the original architecture. _ Two towels are revealed, and the new buffer added by the drunk wheel may cause the maximum clock delay from the clock tree root to the leaves (positive and negative) to increase, and the maximum time depends on the minimum time. Next, the material affects the operation of f. In short, 'this miscellaneous axeman, mine, and _ fine skills, a method to quickly determine the type and location of each buffer on the clock tree, can be matched with the set clock tree artificial design process, quick mosquito sewing __ And Jian, so that the hybrid design meets the database design specifications' close time can be used to meet the conditions _. This tool can quickly determine the buffer surface and position calculation tools in the clock tree, including: input and output sequence of each line of the clock tree structure of the sacrifice; Lianyapin, 22 200428240 power consumption, clock delay, output signal conversion time, etc. Characteristics; Initial state setting; When judging, "'Xie Mugou' does not meet the feasible solution of the design specification. If it does not exist, load balancing and buffer-balance methods are used to obtain a feasible solution; quickly determine the type of buffer to reduce the clock Consumption work of the tree: rate; apply the optimization technique combined with simulated annealing method to find the minimum power consumption of the buffer combination and the global best solution. · Only those mentioned above are used only to control the cost of the attack. When the situation cannot be limited, the scope of the present invention is limited. That is to say, the solution and modification of the professional fiber riders who have made a fortune in accordance with this book will still not

Loss of hair loss is detailed in 'Linza Shufu and Lang,' which is the status of further implementation of the present invention. [Schematic description] Figure 1 is an expanded view of the clock tree network. Figure 2 is a basic 1C design layout flowchart. Figure 3 is a block diagram of the output of a computing satellite that implements the present invention. Figure 4 shows the analysis of the power consumption of the connection structure in the specific buffer database. Figure 5 shows the connection structure of the buffer in the clock tree. wπ, a database of six f buffer delay values, output signal conversion signals, and power consumption is not intended to check the database.一 又 口 丁 # (b) ^^ 〇 FIG. 8 is a flowchart of steps for implementing feasible solutions of the present invention. Figure 9 is a schematic diagram of the clock tree load balancing steps. Figure 10 is a flowchart before quickly balancing low-energy clock tree buffer combinations. '<. Figure 12 is a flowchart of a low-energy consumption clock tree optimization algorithm based on the simulated annealing method. Draft code X. Scope of patent application 23

Claims (1)

200428240 Power consumption, clock delay, output signal conversion time, and other characteristics; initial state settings; when judging whether "Xie Mugou" meets the design solution's feasible solution, if it does not exist, load balancing and buffer-balance methods are used to obtain -Feasible solution; quickly determine the type of buffer to reduce the power consumption of the clock tree: rate; apply optimization techniques combined with simulated annealing method to find the minimum power consumption buffer combination and global best solution. · Only those mentioned above are used only to control the cost of the attack. When the situation cannot be limited, the scope of the present invention is limited. That is to say, the solution and modification of the professional fiber riders who have made a fortune in accordance with this book will still not Loss of hair loss is detailed in 'Linza Shufu and Lang,' which is the status of further implementation of the present invention. [Schematic description] Figure 1 is an expanded view of the clock tree network. Figure 2 is a basic 1C design layout flowchart. Figure 3 is a block diagram of the output of a computing satellite that implements the present invention. Figure 4 shows the analysis of the power consumption of the connection structure in the specific buffer database. Figure 5 shows the connection structure of the buffer in the clock tree. wπ, a database of six f buffer delay values, output signal conversion signals, and power consumption is not intended to check the database.一 又 口 丁 # (b) ^^ 〇 FIG. 8 is a flowchart of steps for implementing feasible solutions of the present invention. Figure 9 is a schematic diagram of the clock tree load balancing steps. Figure 10 is a flowchart before quickly balancing low-energy clock tree buffer combinations. '<. Figure 12 is a flowchart of a low-energy consumption clock tree optimization algorithm based on the simulated annealing method. Draft code 10. Application patent range 23 200428240 1 ·-A kind of clock tree combination cylinder that considers clock skew and low energy consumption synchronously, the steps include: ㈣ information including Qianlan petal number and buffer time sequence and power database information (B) Input the upper limit of the timing specification of the clock distortion rate, and A will find I again and use the 'minus sign' to go through the root of the clock tree, and then switch to the buffers and flip-flops of the clock tree. Time, and the output load value of each buffer, determine whether the buffer combination meets the design specifications of a particular database;限制 change the buffer ϋ change the type quickly to find a feasible solution to reduce the power consumption on the clock tree; ⑦ use the rule of thumb for the specific database, apply the optimization based on the simulated annealing method + find Βτ The combination of buffer connection methods on the clock tree to obtain the best global solution for the power consumption on the clock tree. • As described in item 1 of the patent application, a clock-tree synthesis tool that considers low clock skew and low power consumption synchronously 'its design specification checker composition includes: (a) Characteristics, to determine whether the conversion time of the input signal meets the editing specifications; () For, to hide, determine whether the output of the buffer meets the design specifications; and, “4 inch of the buffer” is the conversion time of the input signal And output load, using the internal delay method-ten different buffer clock delay and output signal conversion time. As described in item 1 of Shen Jing's Monograph—step through the time when considering low clock simplification and low energy consumption. Cheng Weiqi's clock tree load balancing step consists of: (a) = break " Lost &Turn; tree duck finance department in the clock tree < P white layer, with the goal of considering buffer load balancing as Rebirth of Kao Dan. (B) The last order of the clock tree, Luli, 9 & rushed $ 11 positive and negative 11 'riding the clock to minimize the clock delay to reduce the clock distortion rate, so balance the last level of the clock tree The load of the buffer turns out; only the clock tree n buffer, its clock delay will seriously affect the overall clock distortion rate, unbalance the charm of the slow "effectively solve the clock distortion rate _, material balance load can improve the output signal conversion Time, thereby reducing the power consumption of the overall clock tree. 4. Please review the first two steps __ Steps to consider low clock skew and low power consumption clock Five, a tool that quickly seeks buffer combinations Include: (a) Select the same type of buffer for the load of the last-hierarchical buffer in the clock tree; ⑼ Change all buffers in the clock tree to silk type buffers to determine whether they meet anti-design specifications; ⑷ Test Cailong Material slow _ meaning, election full The combination of design specifications with a minimum power consumption of 12 is a solution for quickly seeking buffer combination steps. 25 1. As described in step 丨 of the scope of patent application, a clock secret synthesis tool that considers low clock skew and low power consumption, The steps for finding the global best solution include: (a) For a specific database, the buffer characteristics are different. The present invention first analyzes the characteristics of the components in the database as a basis for determining the type of buffer; 2 (b ) Balance the last-level chaos of the time series, which can be used to limit the distortion of the clock, and improve the conversion time of the input signal of the flip-flop, while reducing the power consumption of the overall clock tree 200428240; (C ) Applying the conventional technology simulated annealing method to find the best combination of buffers. In order to consider the strict clock distortion limit and reduce the computational complexity of the algorithm, the change of the buffer combination is based on the hierarchy, and the local maximum of power consumption is sought. Good solution; (d) Improve the load flip-flop balance at the last level of the clock tree again, and re-apply the simulated annealing method to find the combination of clock buffers. Seek global optimal solution the power consumption of the XI drawings: Page summarized as follows