TWI243565B - Network micro controller and the method for transmitting and receiving data through a wireless network system - Google Patents

Abstract

A network micro-controller and the method for transmitting and receiving data through a wireless network system are disclosed. There are a built-in microprocessor and a system bus in the network micro-controller. There is a public memory connected to the system bus. The public memory is equipped with two communication ports. The first communication ports is directly connected to the system bus, and the second communication port is connected to a plurality of package-processing units to let the microprocessor access the processed code of a program and the data stored in the memory through the first communication port, and at the same time, a data package is directly moved among the package process unit through the second communication port without interrupting the built-in microprocessor processing different procedures. The invention can efficiently support and be applied different wireless radio communication standards, and lower the performance requirement of a built-in microprocessor.

Description

1243565 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to wireless network communication, and in particular, to a system and architecture of a network controller to manage access to a wireless communication network and apply various different Remote (remote) device. [Previous Technology] With the advent of portable electronic devices and their widespread use in work, home, and travel, the demand for more flexible and more efficient wireless networks has accelerated. At present, wireless networks have become a means of electronic communication, so these portable devices must be integrated with the communication protocols and interface technologies used with those networks. In a wireless network environment, portable devices with wireless modems, such as personal digital assistants (PDAs), mobile phones, and laptop devices, are physical devices, and the space or media through which they operate are It is managed by a network controller or system. Generally speaking, a medium access control (MAC) protocol configured on a network controller provides the ability to access and share the media in an organized and efficient mode. In essence, the MAC protocol ensures that only one workstation (statin) is allowed to access the media jf one channel at a time; however, in a wireless network, each workstation has a unique perspective on the system, which is workstation Λ The observed quality of Tongyuan ^ cannot be expected to be equivalent to that observed by another workstation B: Guting is obviously different from the traditional wired network. In the traditional wired network, ^^ is based on the channel condition system. Have the same view. In wireless networks, it is because the media is not restricted to any well-defined physical boundary.

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In addition, the standards used in wireless communications, such as IEEE 802 · 11 technology, focus on media access control (MAC) and access point (AP) networks and ad-hoc networks. Physical layer (PHY) protocols; in other words, a communication standard such as IEEE 802.11 defines a "protocol and logical interface" between a media access control (MAC) device and a physical device, rather than defining a MAC device such as "A method for transmitting data packets between a network controller and a physical device such as a mobile phone". However, the transmission of a packet is performed in eight parallel bits at a time regardless of the use of a specific clock cycle ( bits) continuous transmission, or-one bit continuous transmission, the packet transmission method has not been well defined. This leads to the performance of the MAC device such as the network controller architecture for the network environment it supports. There will be a direct impact; more importantly, because these agreements define a state-oriented process, I know that better practices can only configure such information communication procedures in software In order to achieve the miniaturization effect, it is embedded in the hardware and the elements that operate in the controller. W network is a well-known micro-processor network controller as shown in the first figure, its block diagram, its network The physical configuration of the system uses a central structure; network topology is used to control and determine the path of each network worker = data transmission. As shown in the first figure, the conventional network control device such as CSMA / CD controller 11 so that the device can independently exchange data with the host without using the microprocessor 10

To control and determine the routing between these devices (1 ^ 〇11 derivative), the network controller and the controller must have various independent interfaces for the CDMA / CD controller n.

Page 7 1243565 V. Description of the invention (3) transmit first-in first-out queue (TX FIF0) 12, receive first one in-first — out queue (RX FIF0) 14, one A direct memory access (DMA) interface 16 and an auxiliary bus (AUX BUS) interface 18. The disadvantage of using this topology is that if the microprocessor 10 needs to increase the device interface, such as multiple CSMA / CD controllers n, various interfaces must be relatively added, such as transmit first-in first-out queue (τχ FIF) 12. Receive first-in first-out queue (RX FIFO) 14. Direct § direct memory access (DMA) interface 16 and an auxiliary bus (auxiliary bus, AUX BUS) interface 18, which limits the expandability of the network controller 1, or a more powerful but expensive microprocessor must be selected. Therefore, if the network controller 1 is able to serve each workstation in a timely manner, the performance of the network will be maintained. However, 'if the agreement or packet structure between workstations or devices is different or inconsistent' then The network will suffer from many signal collisions or interruptions / and thus performance degradation due to inefficient bandwidth utilization. Another disadvantage is micro-processing. The architecture of 10 is non-scalable, because the f-microprocessor 10 is adapted to the increasing complexity of the communicated devices. Another conventional micro-processor network controller is disclosed in US Patent US 5,636,140 | ^ ^ The block diagram of a network controller is shown in the second figure. 1 A conventional micro-processor is used to move data. ii = r, which is a network controller 2 between several connected devices, including a media access controller 2 〇

Page 8 1243565 V. Description of the invention (4) and a transceiver interface 22, wherein the media access controller 20 includes a microprocessor 202, a static random access memory for storing user data (static random access memory) memory (SRAM) 204 and a flash memory 206 for storing system programs; and the transceiver interface 22 includes a register set 220, a first-in-first-out transmission queue (τχ FIFO) 222, and a first-in-first-out RX FIFO 224, a series FIFO 226, and a transmit / receiver state machine 228 〇 During system initialization, the microprocessor 202 is

The instructions are fetched and executed from the flash memory 206, and the microprocessor 202 initializes the register 220 according to the program instructions, and then transmits the registration bits and receives the registration bits to set the media access control.器 2〇 的 模型。 Device 20 mode. Here, the microprocessor 202 sets the state controller 228 to a special transmission and reception mode by changing the setting of the register 220, so that the state controller 228 controls the transmission rank (TX FIF) 222 and the reception rank (Τχ —fif〇) 224 operation; while the transmission queue (TX FIF〇) 222 and the reception queue (RX — FIF0) 224 are used to provide data buffering between the microprocessor 202 and a physical device 3 and The role of stable data transmission rate.

The disadvantage of this network controller 2 architecture is that when the microprocessor 202kSRAM 2.0 and the data is transferred between the transmission and reception ranks 222 and 224, the microprocessor 202 is completely occupied and blocked to perform any other work. ; The total processing capacity of the configuration is directly affected by the working lamp capacity of the microprocessor 202. In addition, various wireless devices such as PDA phones and laptop systems,

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It usually includes different integrated chipsets or microprocessors, especially in the baseband communication environment to apply different standards. Therefore, different integrated chip sets or microprocessors usually support different communication standards, but cannot support multiple communication standards at the same time, limiting the use of wireless communication. Therefore, the present invention is directed to the above-mentioned problems, and proposes a network micro-controller architecture and a method for transmitting and receiving data to more efficiently support and implement various wireless communication standards. [Summary] The main object of the present invention is to provide a network microcontroller and its

A method for transmitting and receiving data in a wireless network, so that data packets can be efficiently moved between packet processing elements without disturbing the embedded microprocessor to perform other tasks, thereby achieving a very efficient implementation of various wireless communications Standard efficacy to improve conventional signal collisions and low performance issues. Another object of the present invention is to provide a network microcontroller, which has the advantage of reducing the performance requirement of the embedded microprocessor and thereby achieving the advantage of low power consumption. — Another object of the present invention is to achieve the effect of easily reconfigurable (configurable) between different wireless communication standards, so as to apply to various remote devices. Another object of the present invention is to provide a network microcontroller that can adapt to the increasing complexity of the devices to be communicated. According to the present invention, a network microcontroller includes a system bus, f is used as a communication bridge between other components to transmit program instructions and data, and a shared memory system is connected to the system bus. The shared memory is used to store

Page 10 1243565 V. Description of the invention (6) Store plural execution codes and data and configure at least two access cocks. A first access port directly forms an electrical connection relationship with the system bus, and a second access. Then it is provided to connect to a plurality of packet processing elements, so that a data packet is directly moved between the packet processing elements, and one of the packet processing elements is an operator based on a plurality of wireless communication standards, and another micro-point = row ' The microprocessor is used to control the movement of the operating elements; and: access the execution program in the memory via the first access card to control the operation of at least one packet processing element. Data source: Borrow :: The network microcontroller transmits and receives in the wireless network. The devices communicate with each other = end;: = near-end host. The remote wireless transmission transmits the data sent by the device. ;: The law system first receives the conversion data stream through! Stream the data and store it, and then :: send the data; method: =; = send to the host device; transfer the buffering interface to a common set = one of the data is converted by the host control: f yuan:- Unit 2 of the material is recorded by the shared data :: The material packet is transmitted to the wireless = channel Γ and then received by a wireless transmission ... line transmission device. , In the middle of the road, so as to be internalized by the purpose and technology of the remote end. Pingjia explained, when more features and achievements achieved] The present invention is based on the configuration of a memory with a double access ▲ and a system converged to easily understand this id: For example: the attached drawings detailed description effect. 1243565 V. Description of invention (8) 128 kilobytes capacity. The shared data memory unit 46 is a static random access memory (SRAM) with dual access ports (dua; l-ported). The first access port directly forms an interface connection relationship with the system bus 40, and The second access port is shared among a group of packet processing elements. The dual-port RAM (dual-port RAM) can be virtual or physical. The so-called virtual dual-access port memory refers to a memory with only a single access port to achieve dual-access port memory through the memory controller using time di vision mul tipi iex access method Physical function, but the embedded microprocessor 42 has a higher priority to access this memory; and the physical dual-access port memory refers to the physical memory that actually has dual-access ports. Another register 47 is used by the microprocessor 42 through the system bus 40 to store the functional parameters to direct the behavior of the packet processing unit, thereby enabling a data packet to be generated and determining what type As a result, packets are allowed to be transmitted. The packet processing elements include a host control buffer 48, a Bluetooth baseband transmitter 50, a Bluetooth baseband receiver 52 and _iCe) or an audi0 codec 54. The number of packets is ==, and the direct connection relationship is formed with the shell material " self-memory unit 46, so that the two flags can be efficiently moved between these processing elements without interrupting the processor 42. Other work performed. In order to ensure the processing frequency of each packet i: I: 3: data storage unit 46 'the capacity of this second access port or in order to divide two t eight to division multiplex (TDM), si 0 t 1 ΐ Z is a lot of time Slices or time slots (time-slices), and reassign them to any connected processing element;

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V. Description of the invention (9): The controller 4 is provided with a watchdog timer and a time pulse elimination frequency, because the watchdog timer and time pulse elimination frequency (watchd〇g timeF and eiwk, d1Vider) 56 is about 12MHz frequency operation, so every hour slot is equal to 1/6 of the capacity or bandwidth of the second access port. The sixth time slot or slot is not assigned to ensure a time period. The system will not be missed due to re-synchronization or clock f-curves (^ 〇 to skew). Therefore, each packet processing unit can have the same access capability to the shared data storage unit 46 as needed. Among them, the dual-access port configuration of the shared data memory unit 46 is used to connect to the system bus 40 through one of the access ports and to be electrically connected to the embedded microprocessor 40, and at the same time directly through the other access port The connection of multiple packet processing units enables data packets to be efficiently moved between several packet processing units through the shared data memory unit 46 without disturbing the embedded microprocessor 42 to perform other tasks, thereby achieving efficient efficiency. The performance of various wireless communication standards is implemented to improve the problem of low performance caused by the collision of known signals. At the same time, the transmission efficiency and performance are improved. Therefore, the present invention also has the requirement of reducing the performance of the embedded microprocessor. To achieve the advantages of low power consumption ^. / Host control buffer interface 48 supports many industrial standards, such as UART interface 482, USB interface 484 and PCI interface 486, or other standard memory card interfaces, such as Compact Flash (CF), Digital Security (Secured Digital , SD) and Memory Stick. The host control buffer interface 48 interacts with the shared data memory unit 46 through its receiving port or transmission port. This allows the host control buffer interface to directly interact with the shared data.

1243565 5. Description of the invention (10) The memory unit 46 stores or retrieves payload data to reduce any over-processing, so that the embedded microprocessor 42 will only be interrupted after it has received a block of data, and at the same time The network microcontroller 4 can adapt to the increasing complexity of the communicated devices. In addition, the host control buffer interface 48 includes a 512-byte buffer processing unit, which is allocated into two 256-bit One data segment is used as a transmission buffer, and the other data segment is used as a reception buffer to support the interfaces 482, 484, and 486. Among them, the UART, USB, and PCI interfaces 482, 484, and 486 are physical interfaces between a host 6 and a network controller 4. At any given time, only one interface can be selected and activated. In addition, when the microprocessor 42 is allowed to access the host 6, the interfaces 482, 484, and 486 can be directly accessed by the embedded microprocessor 42. At this time, the host control buffer interface 48 is temporarily stopped. . In addition, the audio codec 54 forms an interface connection with the shared data memory unit 46 and provides digital-to-analog (D / A) and analog digital (analog) for full-duplex audio communications. — To digital 'A / D) conversion; whether it is dial-in (in-bund) or dial-out (out-bound), the sound data is a series of data areas through a special buffer in the shared data memory unit The blocks are swapped. Since the audio encoder 54 has only a single access port for transferring the received and transmitted audio data to the shared data memory unit 46, the audio encoder 54 is responsible for mediation between dialing in and out audio data. The Bluetooth baseband transmitter 50 is used to transmit packet data from the shared data memory unit 46 to an RF front end circuit 58, and the Bluetooth baseband receiver 52 is used to transmit from the RF front end circuit 58 Data to shared data

1243565 V. Description of the invention (11) The detailed circuits and functions of the memory unit 46, the Bluetooth baseband transmitter 50 and the Bluetooth baseband receiver 52 will be described in detail below. The data transmission of the present invention uses asynchronous transfer mode (ATM) technology. Before understanding the second transmission and receiver 50 and 52, the structure of this technology must be first. Atm technology will first transfer the data when transmitting data. Voice, data, and video data are cut into multiple fixed-length packets (package / ceii), and then transmitted to destination 2 'after reaching the destination, and then reassembled back to the original data. Because voice, data, and video data are all taken The same processing method, so ATJf Shi Xu on the same network, at the same time pass different forms of data, including language, data and video data. The ATM packet contains two data parts. See Figure 4 for a diagram of a data packet. A data packet 7 contains a header 70 and a payload 72. The payload = ^ info Block, usually 48 bytes, is for carrying real data, ie, data, and video data; while the header is usually 5 bytes, which is address data. Please refer to the fifth and sixth figures, which are detailed circuit blocks of the Bluetooth baseband transmitter and receiver of the network micro ^ = of the present invention, respectively, but are not shown in the figure. 50 is used to transmit the packet data from the common data 58, #, 6 to the RF front end circuit. During the reading process, all the processing of data transfer and control is performed by a tranSmitter state. machine, TSM) 500 order to & false = tune, this transmission state controller (TSM) 500 is also responsible for generating the index and column converter 504, so that the transmission sequence converter 504 according to the 1243565

The instructions act and direct each data packet to a different frequency hopping; among them, a register 47 stores the functional parameters designated by the microprocessor 42 to direct the behavior of the transmission state controller 50 0, thereby using this A data packet $ is generated 'and determines what type of data packet is allowed to be transmitted. When a data is transmitted from the transmission buffer unit in the shared data memory unit 46 to the Bluetooth baseband transmitter 50, the data is received by the transmit serializer 504, and the transmit serial converter 504 The data is received in eight bits byte, and the parallel data is converted into a serial data stream (seriai data strean) or carrying data 72. Once the data has been converted and connected into a string A head M is attached to the carrying data 72 to form an initial data packet 7, $ and then the data packet 7 passes a header error correction (HEC) element 506, and a periodic repeat check (cycHcal) One or all of the functional elements such as redundancy check (CRC) element 508 and an encryption and authorization element 510. The header error correction element 506 is usually 8 bits. Any one of the first four bytes (4 Bytes) of the packet header 70 and a multi-bit error detection; the authorization and encryption element 51 〇 is used to set user permissions and data encryption Yes, and all the transmitted data is through the first two functional elements 506 and 508 to ensure that the header 70 and the carrying data 72 are properly organized together, and the authorization and encryption element 51 is encrypted when the packet 7 is generated. The function defined by the system is executed after the packet 7 has passed one or two other functions. Once the data has been processed for error correction, the header is transmitted before it is transmitted.

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Both 70 and the carrying data 72 are first sent to a data whitening process) 512. The data whitening process is a method of scrambling the header 70 and carrying data 72 in a specific language in order to remove the data from A highly verbose data pattern is broken up, randomized to make it randomly arranged, to avoid continuous " 〇 " or ,,, ", and to minimize any direct current (DC) bias in the packet . Among them, the specific language used in this process is generated by a whitening polynomial g (j)) + + D4 + 1 ', and then an EX OR operation (exclusive or operation) with the header 70 and the carrying data 72; and the transmission The state controller 500 is also another packet processing mechanism. It also controls the selection of the whitening process. After the whitening process is completed, the data packet 7 becomes its final type and is forwarded to the forward error correction (FEC) element, so that the data packet 7 is transmitted to a slot former (i0t formauer) 5i6. Correct any errors first. The time slot former 516 is used to select an input data stream from a synchronous text generator (not shown), whitening processing element 512, and forward error correction (fec) element 51 4; then the data packet 7 is transmitted. To a transmitting module 518 for radio frequency (RF) processing and directly transmitting to a digital-to-analog converter (DAC) in the radio frequency front-end circuit 58; and a Bluetooth baseband receiver 52 The detailed circuit is shown in Figure 6. A Bluetooth baseband receiver 52 is used to transmit data from the RF front-end circuit 58 to the shared data memory unit 46. The function of the Bluetooth baseband receiver 52 is the same as that of the Bluetooth baseband receiver. Conversely, the frequency transmitter 50 receives an input radio frequency data and grabs the data from it, so that the data stream returns to the original state, and then the data stream is aggregated to make it stand-alone.

1243565 V. Description of the invention (15) The above description explains the features of the present invention through the examples. The purpose is that those skilled in the art can understand the content of the present invention and implement it based on the scope of the present invention, rather than limiting the patent scope of the invention Therefore, all other equivalent modifications or modifications that do not depart from the spirit disclosed in the present invention should still be included in the scope of patents described below. Description of figure number: 1 network controller 10 microprocessor 12 FIFO transmission rank 14 FIFO reception rank 1 6 direct § memory access interface 1 8 auxiliary bus interface 2 network controller 20 media access Controller

202 Microprocessor 204 SRAM 2 〇6 Flash memory 2 2 Transceiver interface 22 () Temporary register 222 FIFO transmission rank 224 FIFO reception rank 226 Serial FIFO 2 28 Transmission / reception status controller 3 Physical device 4 Network microcontroller 42 Built-in microprocessor 46 Shared data memory unit 48 Host control buffer interface 484 USB interface 50 Bluetooth baseband transmitter 5 0 4 Transmit sequence converter 5 0 8 Periodic repeat check unit 5 1 2 Whitening processing element 4 0 System bus 4 4 Non-volatile memory 47 Register 482 UART interface 486 PCI interface 500 Transmission status controller 506 Header error correction element 510 Authorization and encryption element 514 Forward error correction element

1243565 V. Description of Invention (16)

516 slot formation 52 Bluetooth baseband receiver 522 synchronization and correction unit 5 2 6 decoding unit 530 header error correction unit 534 receiving deserializer 54 audio codec 58 RF front-end circuit 7 data packet K carrying data 5 1 8 Sending module 5 2 0 Receive status controller 524 Forward error correction element 5 28 De-whitening element 532 Periodic repeat check element 56 Watchdog timing and pulse eliminator 6 Host 70 header

Page 21 1243565 Brief description of the diagram The first diagram is a block diagram of the structure of a conventional microprocessor network controller. The second figure is a block diagram of another conventional microprocessor network controller. The third figure is a block diagram of the network microcontroller of the present invention. The fourth figure is a schematic diagram of a data packet according to the present invention. The fifth figure is a detailed circuit block diagram of the Bluetooth baseband transmitter in the network microcontroller of the present invention. The sixth figure is a detailed circuit block diagram of the Bluetooth baseband receiver in the network microcontroller of the present invention.

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Claims (1)

1243565 6. Scope of patent application 1. A network microcontroller for performing packet processing and data transmission in a wireless communication system. The network microcontroller includes: a system bus which is used for transmission Program instructions and data as a communication bridge between other components; shared memory, which is connected to the system bus, the shared memory is used to store plural execution codes and data, and the shared memory system = set At least two access ports, a first access port is directly connected to the system to form an electrical connection relationship, and a second access port provides connection to a plurality of packet managements, so that a data packet is directly processed in these packets Be moved And one of the packet processing elements is based on a plurality of wireless communication bidders; and a thousand inverse, a microprocessor, which is connected to the system bus, the micro processing = controlling the operation of the operating parts, and through the system bus The execution code in the shared memory and the operation for controlling at least one packet processing element are accessed via the first access unit. 2. The network microcontroller described in item 丨 of the scope of patent application, and other wireless communication standards include IEEE 802 · 11 and Bluetooth standards. , ^ 3 · The network microcontroller according to item 1 of the scope of patent application, which = the shared memory unit includes a system memory unit and a shared data record w-the system memory unit is connected to the system bus, and It is used to store the code and execute the code. The shared data memory unit is used to store coarse particles. The two access ports are configured. Beco 'and its 4. The network microcontroller as described in item 3 of the scope of patent application, its system memory unit is a non-volatile memory. > Ning Page 23 1243565 6. Scope of patent application 1 = Signal input and output relationship with the standard i-communication standard interface. The network micro-controllers described in item U, wherein the subject: discipline is at least one selected from the group consisting of a UART interface, a USB interface, a PCI interface, and a card interface. Mainly the network microcontroller described in item 9 of the patent scope of H, wherein the etch control buffer interface is used to directly access and carry data in the shared memory. &Quot; Already received-block data will only be interrupted. 4. A method for transmitting data in a wireless network, for transmitting data from a host to a wireless communication network, the method includes the following steps: transmitting data from one of the host devices via a connection interface To — shared data memory unit storage; captures the transmitted data with a baseband receiver and converts it into a packet; and J transmits the data packet to a wireless transceiver module, and the wireless transceiver module The data packet is transmitted to a wireless communication network, and the baseband receiver directly captures and processes the transmission data stored in the shared data storage unit, so that the transmission data is efficiently moved. Method 5. The method as described in item 4 of the scope of the patent application, wherein the data packet includes a header and a carrying material, and the carrying material is composed of a series of data streams. iG. The method according to item 14 of the scope of patent application, wherein the wireless transceiver module includes a Bluetooth baseband transmitter, a Bluetooth baseband receiver, and a radio frequency front-end circuit. 25 Page 25, 1243565 6. Scope of patent application-U. Lift the method described in item 14 of the scope of patent application 'wherein' The wireless communication standard used by the helmet line transceiver module is selected from the group consisting of IEE standards At least one of the groups. G2.u and blue labeling are used to transmit this transmission method as described in item 14 of the scope of the patent application, wherein the step of converting the data into the data packet includes ... and appending a standard to convert the transmission data into a The serialized carrying information heads over the carrying information to form an initial packet; the header is subjected to error correction processing; the randomization is performed on the header and the carrying information to whiten the data and arrange randomly; and '= Header and the processing of forward error correction of the carrying data = Λ error, and then a complete data packet is formed. =? At the time of error correction step, it is also included at the same time-week weight = 20 · As described in the 18th scope of the patent application, after the first error correction step, it is included-authorization and encryption are performed in the step 1. · If applied the method of claim 18 patentable scope of the item, an error correction after the step, further comprising a step ,, 'direction to the front - when the groove is formed to select the input data stream: ,, ~ r packet transfer shell · 22 —A method for receiving data in a wireless network. A communication network transmits a wireless transmission device from a wireless machine device. The method includes the following steps: receiving a packet from a host-receiving the data packet from the host 'and the data. The packet contains a header and a carrying page. Page 26 6. Application for patent scope data: The exchange data is composed of-a stream of data; the data for converting the data packet stores the transformed data stream; and 4) it becomes a-transformed data stream ; The conversion data stream is transmitted to the host through a device through the host control buffer interface & host control buffer interface directly 4 claws ® L you · + + data stream and directly to the host The conversion of the stored takes to be moved. The host device 'to make the converted data stream efficiently = · The method described in item 22 of the scope of patent application, in the second step, the wireless communication standard used is selected... And the Bluetooth standard group At least one of them. //// Μ® Item 22 " ^ Method ', wherein the step of converting the resource packet format includes: synchronizing the data packet and error correction processing, wherein the content of the data packet is the same as a The preset threshold value is used for relative comparison; the header and the carrying information are subjected to forward error correction processing; and the header and the carrying information are de-whitened, so that they return to the original state and become orderly and organized information Shaping; and, deserializing and formatting the carrier data to reorganize it into a unified data type. "" 25. The method as described in item 22 of the scope of patent application, wherein before converting the format of the data packet, it further comprises a step of decompressing the data packet. 26. As described in item 24 of the scope of patent application Method, which includes header error correction (HEC) and 1243565 before deserializing the data packet. 6. Steps of applying for a patent repetitive phase 3 repetitive check (CRC). The method described in item 22, wherein the communication standard interface supported by the host control interface == red interface is selected from the group consisting of a · interface, a compiled PCI interface and a standard credit + interface; a group consisting of card interfaces. Group of "'s page 28