1242844 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種深溝渠單邊埋藏導電帶之製作方 法0 【先前技術】 溝渠式動態隨機存取記憶體(Trench-DRAM)結構是先 在半導體基材中蝕刻出複數個深溝渠(deep trench，DT)，再 於各深溝渠中分別製作溝渠電容，然後利用埋入導電帶電 連接溝渠電容與金屬氧化半導體(metal-oxide semiconductor，MOS)電晶體，以大幅降低記憶胞（memory cell)的橫向單位面積，進而增加半導體元件的積集度。而 為了避免相鄰記憶胞(memory cell)之間的相互干擾，埋入 導電帶也逐漸演變成僅具有單邊之埋入導電帶（Single sided buried strap，SSBS)的結構，但由於製程的困難度較 高，往往造成單邊埋入導電帶寬度變異性大，進而使得電 阻值不穩定而影響電性的表現。 請參考第1圖至第3圖，第1圖至第3圖為習知製作一 深溝渠單邊埋藏導電帶之方法示意圖。如第1圖所示，首 1242844 先於一半導體基底10上依序沈積一墊氧化12 與一墊氮化(pad nitride)層14，接著利用黃光暨蝕刻製程於 半導體基底10中形成至少一深溝渠16。 隨後利用沈積、擴散、蝕刻等製程，於深溝渠16中形 成一溝渠電谷（圖未示）以及一多晶砍層17覆蓋於溝渠電容 上。如第2圖所示，接著進行一沈積製程，形成一氮矽化 合物(silicon nitride)層18當作下遮罩層，然後於氮矽化合 物層18表面再沈積一非晶石夕（amorph〇ussiiic〇n，_si)層2〇 當作上遮罩層。之後，進行一斜角離子佈植⑴lted implantation)，將摻雜離子22植入非晶矽層20中，然後利 用被離子轟擊之非晶石夕結構與未受佈植之非晶石夕結構的餘 刻選擇比的差異，來進行一蝕刻製程，用以去除未植入摻 雜離子22之部分的非晶石夕層20並裸露出氮石夕化合物層 18，然後進行一次濕钱刻製程，用以去除裸露出來的氮石夕 化合物層18。最後再利用剩下之非晶矽層2〇以及氮矽化 合物層18當作硬遮罩(hard mask)來姓刻深溝渠内之多 晶石夕層17，以形成單邊埋藏導電帶。 然而，如第3圖所示，在進行氮矽化合物層μ的濕蝕 刻製程時，因為濕蝕刻製程之等向性蝕刻的蝕刻終點及均 1242844 勻度(uniformity)難以控制，因此非常容易造成氮石夕化合物 層18發生底切(undercut)24的現象，嚴重影響非晶石夕層20 及氮石夕化合物層18遮蔽之精確度，進而造成後續製備之單 邊埋入導電帶寬度的高變異性，使得單邊埋入導電帶的電 阻值不穩定而影響整體電性表現。 有鑑於此，申請人乃根據此等缺點及依據多年從事製 造該類產品之相關經驗，悉心觀察且研究之，進而提出本 發明，可以避免上述所提之底切24產生影響。 【發明内容】 本發明之主要目的即在於提供一種防止底切之單邊埋 入導電帶的製作方法。 本發明係揭露一種單邊埋入導電帶之製作方法。首先 提供一形成有至少一深溝渠之基底，且深溝渠内包含一溝 渠電容以及一多晶矽層覆蓋於溝渠電容上。首先依序沈積 一第一、第二遮罩層於多晶矽層上。接著進行一第一離子 佈植製程，將摻雜離子植入於部分之第二遮罩層内，隨後 再進行一蝕刻製程，將未植入摻雜離子之第二遮罩層加以 钱除，並裸露出第一遮罩層。然後再進行一第二離子佈植 1242844 製程與一濕蝕刻製程，蝕除裸露之第一遮罩層，以與剩餘 之第二遮罩層共同形成一硬遮罩覆蓋於部分之多晶^夕層 上。最後進行一蝕刻製程，蝕刻未被硬遮罩遮蔽之部分多 晶矽層，以形成由部分多晶矽層所構成之單邊埋入導電帶。 由於本發明之單邊埋藏導電帶之製作方法，係採用二 遮罩層以及二次離子佈植製程，利用被離子轟擊之遮罩層 與未受佈植之遮罩層的#刻選擇比的差異，來分別進行餘 刻製程，因此可有效且精確地控制二遮罩之遮蔽區域， 提_蝕刻的均勻度並大幅減少了蝕刻時間，避免底切現象 之產生。 【實施方式】 為了使貴審查委員能更近一步了解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用，並非用來對本發明加 以限制者。 請參考第4圖至第8圖，第4圖至第8圖為本發明之 深溝渠單邊埋藏導電帶製作方法之示意圖。如第4圖所 示，首先提供一半導體基底30，例如矽基底，並於半導體 1242844 基底30上依序沈積一墊氧化(pad oxide)層32與一墊氮化 (pad nitride)層34，接著利用黃光暨蝕刻製程於半導體基底 30中形成至少一深溝渠36。隨後再利用沈積、石申石夕玻璃 (arsenic silicate glass，ASG)擴散、蝕刻、沈積等製程，依序 於深溝渠36中形成一溝渠電容（圖未示），以及一多晶石夕層 37專之導電層覆蓋於溝渠電容上，此為習知相關技藝者所 熟知，在此不多加贅述。 接著再進行一沈積製程，例如高密度電漿化學氣相 _ (HDP)沈積法，形成一遮罩層。在本發明之較佳實施例 中，遮罩層係為一包含有第一遮罩層38、第二遮罩層此 之複合結構層，例如第一遮罩層38可為四乙氧基矽烷 (TE0S)沈積層，而第二遮罩層4〇則可為非晶矽化合物。然' 後再進行一斜角離子佈植製程，將摻雜離子42植入第二遮 罩層40内’因此第二遮罩層4〇至此可區分為植入與未受鲁 掺雜離子轟擊之兩部分。 — 之後’如第5圖所示’利用被離子轟擊之非晶石夕結構 與未受佈社非晶♦結構的侧轉比的差異來進行一餘 刻製程’例如氨水濕姓刻製程，將未受摻雜離子義擊之第、 二遮罩層40絲，並且裸露出部分之第_遮單層％。^ 11 1242844 後，如第6圖所示，利用剩下的第二遮罩層40當作遮蔽物 來進行一正向離子佈植製程，使用摻雜離子44植入裸露出 來的部分第一遮罩層38中，進而使得被離子轟擊之第一遮 罩層38與未受佈植之部分第一遮罩層38產生钱刻選擇比 之差異。舉例說明，以氨水濕蝕刻製程為例，當非晶矽結 構受到硼離子(B+)轟擊後，其受氨水蝕刻之速率約為0.1 人/min，而未受硼離子（B+)轟擊之非晶矽結構之蝕刻之速率 約為21人/min ;另一方面，以氫氟酸濕蝕刻製程為例，當 四乙氧基矽烷(TEOS)沈積層受到硼離子(B+)轟擊後，其受 氳氟酸濕钱刻之速率約為35 nm/min，而未受蝴離子(B+)轟 擊之四乙氧基矽烷(TEOS)沈積層之蝕刻之速率約為5 nm/min，另外受硼離子(B+)轟擊之非晶矽層其受氳氟酸濕 餘刻之速率約為4nm/min。 再如第7圖所示，進行一濕蝕刻製程，例如稀釋氫氟 酸（DHF)或緩衝氫氟酸濕蝕刻製程，將裸露出來的部分 第一遮罩層38加以钱除。於一實施例中，由於侧邊第一遮 罩層38之厚度小於底部第一遮罩層38之厚度，即使侧邊 第一遮罩層38未受到正向摻雜離子44佈植，在同樣的蝕 刻時間内侧邊第一遮罩層38同樣會被蝕除。如此，則未被 蝕除之第一遮罩層38與第二遮罩層40即成為部分多晶矽 12 1242844 層37之複合式硬遮罩。 然後，如第8圖所示，進行—乾偏,】製程，將未被硬 遮罩遮敝之部分多㈣層37加錄除，形成由部分多 層所構成之單邊埋人導電帶46。最後再彻淺溝隔離B曰 (shallow trench is〇iati〇n，STI)製程於單 年电▼ 46侧 邊形成絕緣層，此亦為習知相關技藝者所熟知，故不 述。其中，斜角離子佈植製程與正向離子佈植製程所二用 摻雜離子42、44可以是相同之掺雜離子或不同之推雜離 其中，值得注意的是，由於本發明係利用一正向離子 佈植製程之摻雜離子44來破壞裸露出來的部分第一遮罩 層38之結構，並使有受到離子佈植之部分第一遮罩層％ 摻雜有摻質’料可使得本發0魏叫短之關時間來將 裸露出來之部分第-遮罩層38去除，避免f知技術中濕韻 刻製程之等向性#刻祕祕點及均勻度難以控制的問 題’因此能有效避免第-料層38發生如習知技術之氮石夕 化合物層18的底切24現象。 綜上所述，本發明之單邊埋藏導電帶之製作方法，係 13 1242844 採用二遮罩層以及二次離子佈植製程，利用被離子轟擊之 遮罩層與未受佈植之遮罩層的姓刻選擇比的差異，來分別 進行蝕刻製程，因此可有效且精確地控制二遮罩層之遮蔽 區域，提高蝕刻的均勻度並大幅減少了蝕刻時間，避免底 切現象之產生，以增加單邊埋入導電帶之硬遮罩的精確 度，進而能防止硬遮罩影響單邊埋入導電帶之形狀及大 小，以利後續製備單邊埋入導電之寬度的一致性，確保溝 渠電容與金屬氧化半導體(MOS)電晶體電連接的電性表 現。由此可知，本發晛之深溝渠單邊埋藏導電帶之製作方 法能有效提高溝渠式動態隨機存取記憶體(Trench-DRAM) 之生產良率及品質。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖為習知一深溝渠製作方法之示意圖。 第4圖至第8圖為本發明之深溝渠製作方法之示意圖。 14 1242844 【主要元件符號說明】 10半導體基底 12墊氧化層 14墊氮化層 16深溝渠 17多晶矽層 18氮矽化合物層 20非晶矽層 22摻雜離子 24底切 30半導體基底 32墊氧化層 34墊氮化層 36深溝渠 37多晶矽層 38第一遮罩層 40第二遮罩層 42摻雜離子 46單邊埋入導電帶 44摻雜離子 151242844 IX. Description of the invention: [Technical field to which the invention belongs] The present invention provides a method for manufacturing a single-sided buried conductive tape in a deep trench. [Prior technology] The trench-type dynamic random access memory (Trench-DRAM) structure is A plurality of deep trenches (DTs) are etched into the semiconductor substrate, and trench capacitors are made in each of the deep trenches, and then the buried capacitors are used to connect the trench capacitors with metal-oxide semiconductor (MOS) electricity. Crystals to greatly reduce the horizontal unit area of the memory cell, thereby increasing the degree of accumulation of semiconductor elements. In order to avoid mutual interference between adjacent memory cells, the buried conductive tape has gradually evolved into a structure with a single sided buried strap (SSBS), but due to the difficulty of the process A high degree often results in large variability in the width of a single-sided embedded conductive tape, which in turn makes the resistance value unstable and affects electrical performance. Please refer to Figs. 1 to 3, which are schematic diagrams of a conventional method for making a single-sided buried conductive trench in a deep trench. As shown in FIG. 1, the first 1242844 sequentially deposits a pad oxide 12 and a pad nitride layer 14 on a semiconductor substrate 10, and then forms at least one semiconductor substrate 10 using a yellow light and etching process. Deep trenches 16. Subsequently, a trench valley (not shown) and a polycrystalline cutting layer 17 are formed on the trench capacitor to form a trench valley (not shown) in the deep trench 16 by using processes such as deposition, diffusion, and etching. As shown in FIG. 2, a deposition process is then performed to form a silicon nitride compound layer 18 as a lower mask layer, and then an amorphous stone (amorphooussiiic) is deposited on the surface of the nitrogen compound compound layer 18. On, _si) layer 20 is used as the upper mask layer. After that, a beveled ion implantation is performed, the doped ions 22 are implanted into the amorphous silicon layer 20, and then the amorphous stone structure bombarded by the ions and the amorphous stone structure not implanted are used. The difference in the selection ratio at the rest is used to perform an etching process to remove the amorphous stone layer 20 without implanting the doped ions 22 and expose the nitrogen stone compound layer 18, and then perform a wet money engraving process. It is used to remove the exposed azolite compound layer 18. Finally, the remaining amorphous silicon layer 20 and the nitrogen-silicon compound layer 18 are used as hard masks to engrav the polycrystalline silicon layer 17 in the deep trench to form a unilateral buried conductive strip. However, as shown in FIG. 3, during the wet etching process of the nitrogen-silicon compound layer μ, because the etching end point and the uniformity of the 1242844 uniformity of the isotropic etching of the wet etching process are difficult to control, it is very easy to cause nitrogen The phenomenon of undercut 24 occurs in the Shixi compound layer 18, which seriously affects the accuracy of the masking of the amorphous stone layer 20 and the nitrogen stone compound layer 18, which in turn causes a high variation in the width of the unilaterally embedded conductive bands subsequently prepared. This makes the resistance value embedded in the conductive tape on one side unstable and affects the overall electrical performance. In view of this, the applicant has carefully observed and studied based on these shortcomings and years of relevant experience in manufacturing such products, and then proposes the present invention to avoid the impact of the undercut 24 mentioned above. [Summary of the Invention] The main object of the present invention is to provide a manufacturing method for preventing the undercut from being embedded in the conductive tape on one side. The invention discloses a manufacturing method of a unilaterally embedded conductive tape. First, a substrate having at least one deep trench formed is provided, and the deep trench includes a trench capacitor and a polycrystalline silicon layer covering the trench capacitor. First, a first and a second mask layer are sequentially deposited on the polycrystalline silicon layer. Then, a first ion implantation process is performed, the doped ions are implanted in a part of the second mask layer, and then an etching process is performed to remove the second mask layer without implanted dopant ions. The first mask layer is exposed. Then a second ion implantation 1242844 process and a wet etching process are performed to remove the exposed first mask layer to form a hard mask covering the polycrystalline part with the remaining second mask layer. On the floor. Finally, an etching process is performed to etch a portion of the polycrystalline silicon layer that is not masked by the hard mask to form a unilaterally buried conductive strip composed of a portion of the polycrystalline silicon layer. Due to the manufacturing method of the unilaterally buried conductive tape of the present invention, the two mask layers and the secondary ion implantation process are used, and the #etch selection ratio of the mask layer bombarded by ions and the mask layer not implanted is used. The difference is used to separately carry out the remaining process, so the masked area of the two masks can be effectively and accurately controlled, the uniformity of the etching is improved, the etching time is greatly reduced, and the undercut phenomenon is avoided. [Embodiment] In order for your review committee to understand the features and technical contents of the present invention more closely, please refer to the following detailed description and drawings of the present invention. However, the drawings are for reference and auxiliary explanation only, and are not intended to limit the present invention. Please refer to FIGS. 4 to 8, which are schematic diagrams of a method for manufacturing a single-sided buried conductive strip in a deep trench according to the present invention. As shown in FIG. 4, a semiconductor substrate 30 such as a silicon substrate is first provided, and a pad oxide layer 32 and a pad nitride layer 34 are sequentially deposited on the semiconductor 1242844 substrate 30, and then, A yellow light and etching process is used to form at least one deep trench 36 in the semiconductor substrate 30. Subsequently, a process of deposition, arsenic silicate glass (ASG) diffusion, etching, and deposition is used to sequentially form a trench capacitor (not shown) in the deep trench 36 and a polycrystalline layer 37 The conductive layer is specifically used to cover the trench capacitor, which is well known to those skilled in the art and will not be described in detail here. Then, a deposition process is performed, such as a high density plasma chemical vapor phase (HDP) deposition method, to form a mask layer. In a preferred embodiment of the present invention, the mask layer is a composite structure layer including a first mask layer 38 and a second mask layer. For example, the first mask layer 38 may be tetraethoxysilane (TEOS), and the second mask layer 40 may be an amorphous silicon compound. Then, a beveled ion implantation process is performed to implant doped ions 42 into the second mask layer 40. Therefore, the second mask layer 40 can be distinguished as implanted and un-doped by ion bombardment. Two parts. — After 'as shown in FIG. 5', the difference between the side-turn ratio of the amorphous structure and the amorphous structure of the non-clothing company was used to perform a one-step process, such as the ammonia wet process. The 40th wire of the second and second masking layers that were not attacked by the doped ions, and the bare single-layer% of the exposed portion. ^ 11 After 1242844, as shown in FIG. 6, the remaining second mask layer 40 is used as a shield to perform a forward ion implantation process, and the exposed part of the first mask is implanted with doped ions 44. In the mask layer 38, the difference between the first mask layer 38 subjected to ion bombardment and the portion of the first mask layer 38 that is not implanted is different. For example, taking the ammonia wet etching process as an example, when the amorphous silicon structure is bombarded by boron ions (B +), the rate of etching by the ammonia water is about 0.1 person / min, but the amorphous silicon is not bombarded by boron ions (B +). The etching rate of the silicon structure is about 21 people / min; on the other hand, taking the hydrofluoric acid wet etching process as an example, when the tetraethoxysilane (TEOS) deposition layer is bombarded with boron ions (B +), it is affected by radon. The rate of fluoric acid wet engraving is about 35 nm / min, and the rate of etching of the tetraethoxysilane (TEOS) deposited layer not bombarded by butterfly ions (B +) is about 5 nm / min. B +) The amorphous silicon layer bombarded by fluorinated acid is about 4 nm / min. Then, as shown in FIG. 7, a wet etching process is performed, such as a dilute hydrofluoric acid (DHF) or buffered hydrofluoric acid wet etching process, and the exposed first mask layer 38 is removed. In one embodiment, since the thickness of the first mask layer 38 on the side is smaller than the thickness of the first mask layer 38 on the bottom, even if the first mask layer 38 on the side is not implanted with forward doped ions 44, The first mask layer 38 on the inner side of the etching time will also be etched. In this way, the first mask layer 38 and the second mask layer 40 that have not been etched become a composite hard mask of a part of the polycrystalline silicon 12 1242844 layer 37. Then, as shown in FIG. 8, a dry-drying process is performed, and a part of the multi-layered layer 37 not masked by the hard mask is added and recorded to form a unilateral buried conductive tape 46 composed of a plurality of layers. Finally, the shallow trench isolation B (Shallow trench isioation (STI)) process is used to form an insulating layer on the side of a single electrical ▼ 46, which is also well known to those skilled in the art, so it will not be described. Among them, the doped ions 42 and 44 used in the bevel ion implantation process and the forward ion implantation process may be the same dopant ions or different dopants. It is worth noting that since the present invention uses a The doping ions 44 in the forward ion implantation process destroys the structure of the exposed part of the first mask layer 38, and makes the part of the first mask layer exposed to the ion implantation% doped with a dopant material so that This issue calls for a short closing time to remove the exposed part of the first-mask layer 38 to avoid the isotropicity of the wet rhyme engraving process in the known technology. #The secret point and the uniformity are difficult to control. It can effectively prevent the undercut 24 of the first material layer 38 from occurring as in the prior art nitrogen compound layer 18. In summary, the manufacturing method of the unilaterally buried conductive tape of the present invention is 13 1242844. It uses two masking layers and a secondary ion implantation process, using a masking layer bombarded by ions and a masking layer that is not implanted. The difference between the selection ratio of the last name and engraving is used to separately perform the etching process, so the masked area of the two mask layers can be effectively and accurately controlled, the uniformity of the etching is improved, the etching time is greatly reduced, and the occurrence of undercutting is avoided to increase The accuracy of the hard mask embedded in the conductive tape on one side can prevent the hard mask from affecting the shape and size of the conductive tape embedded on one side, so as to facilitate the subsequent preparation of the uniformity of the width of the buried conductive tape and ensure the trench capacitance. Electrical performance of electrical connection with metal oxide semiconductor (MOS) transistors. It can be seen from this that the manufacturing method of the unilaterally buried conductive strip in the deep trench of the present invention can effectively improve the production yield and quality of trench-type dynamic random access memory (Trench-DRAM). The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention. [Schematic description] Figures 1 to 3 are schematic diagrams of a method for manufacturing a deep trench. 4 to 8 are schematic diagrams of a method for manufacturing a deep trench according to the present invention. 14 1242844 [Description of main component symbols] 10 semiconductor substrate 12 pad oxide layer 14 pad nitride layer 16 deep trench 17 polycrystalline silicon layer 18 nitrogen silicon compound layer 20 amorphous silicon layer 22 doped ions 24 undercut 30 semiconductor substrate 32 pad oxide layer 34 pad nitride layer 36 deep trench 37 polycrystalline silicon layer 38 first mask layer 40 second mask layer 42 doped ions 46 unilaterally buried conductive tape 44 doped ions 15