TWI241764B - Differential voltage amplifier circuit - Google Patents
Differential voltage amplifier circuit Download PDFInfo
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- TWI241764B TWI241764B TW092108941A TW92108941A TWI241764B TW I241764 B TWI241764 B TW I241764B TW 092108941 A TW092108941 A TW 092108941A TW 92108941 A TW92108941 A TW 92108941A TW I241764 B TWI241764 B TW I241764B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
- H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
- H03F3/45977—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- General Chemical & Material Sciences (AREA)
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Abstract
Description
1241764 玖、發明說明 之立而子笔壓放大時之差動電壓放大電路之輪出電壓值 加上或減去之前求得之補償電壓值之值用作對應充電電流 或放電電流之值，而以剩餘容量演算電路109演算剩餘容 置。藉此可使補償電壓之二電池101剩餘容量之演算結果 5 誤差縮小。 又’先行技術文獻如下所示。 專利文獻1特開平7· 191110號公報 如上述習知技藝所示，在藉檢測出差動電壓放大電路 之輸入補償電壓值，自輸出電壓值加上或減去該值，以於 10檢測結果進行修正之方法中，為差動電壓放大電路之輸入 電壓值包含輸入補償電壓值之狀態。結果，差動電壓放大 電路原本具有之輸入電壓可能範圍多了輸入補償電壓部份 ，因而扣掉輸人補償電壓所佔範圍之範圍便為習知技藝中 之差動電壓放大電路之輸入電壓可能範圍。因此，為使用 15於測定之輸入電壓可能範圍縮小，乃限定測定範圍，而有 使測定精確度下降之問題。 再者，當輸入補償電壓隨溫度變化時，因測定溫度不 同’而使已修正算出之輸出電壓值與實際之差動電壓間有 誤差產生。由於電池剩餘量係根據累計之輪出電壓值算出 ，故使測定誤差亦隨之累計，而有與實際電池剩餘量大至 無法忽視之程度之問題。為避免此問題，電池剩餘量仍充 裕，但不得不發出剩餘量不足之警告，㈣無法將電池容 量利用至最大限度的問題。每當«時，在測定輸入 補償電壓值之際，亦有產生刪之負擔增加或消耗電流增 20 1241764 坎、發明說明 加等之問題。 又’由於呈差動電壓放大電路之輸入差動電壓包含輸 入補償電壓值之狀態，故每當測定差動電壓時，須進行自 輪入差動電壓去除補償電壓值之影響的修正計算。因此， 5為進行修正須以MPU進行演算處理，而有不但控制繁雜， 且電流托費亦大之問題。 此外，由於將輸入補償電壓記憶於MPU，故須在高精 確度之環境下，進行算出輸入補償電壓，以記憶於Mpu之 測試。因而有測試裝置龐大，且測試昂責之問題。 10 【發明内容】 本發明即是為解決至少一個前述習知技藝之課題而創 作者，其目的在於提供一種差動電壓放大電路，係可防止 輸入電壓可能範圍縮小，而不須以Mpu等進行之修正計瞀 ，且溫度變化造成之影響減少，而可檢測出高精確度之差 15 動電壓者。 發明揭示 為達成前述目的，有關申請專利範圍第丨項之差動電壓放 大電路係係具有第1差動放大器者，其更具有：_第1開 關部，係使第1輸入端子至第！差動放大器之第！輸入路 2〇控及第2輸入端子至第！差動放大器之第2輸入路徑之輸 入路徑間短路者；-電壓保持部，係於輸人特間短路時 ，保持自刖述第1差動放大器輸出之短路輸出電壓者；一 第2開關部，係於保持短路輸出電壓之際，連接前述第1 差動放大裔之輸出端子與前述電壓保持部者；一減法電路 1241764 玖、發明說明 部.，係減去保持於前述電塵保持部之短路輸出電塵與第】 基準電屢者；及一坌 開關。卩，係於輸入路徑間短路時， 將前述第1基準電壓供給 5 10 15 用以ό又疋刖述第〗差動放大器 之輸入電壓之偏壓點的偏壓端子，而於差動電壓放大時， 以前述減法電路部之輸出作為第2基準㈣而將之供給至 前述偏壓端子者。 又’有關申請專利範圍第2項之差動電塵放大電路更 具有：一第1電阻器，係連接於前述第】輸入端子者·一 第2電阻器，係連接於前述第2輸入端子者·一第^電阻 器，係連接於前述偏麼端子者；及一第4電阻器，係連接 於前述第1差動放大器之輸出端子者；而前述第】電阻器 與第3電阻器之連接點係連接至前述第ι差動放大器之正 向輸入端子，前述第2電阻器與前述第4電阻器之連接點 係連接至前述第1差動放大器之倒向輸入端子；且前述第 電：器與前述第2電阻器之電阻值相等，前述第3電阻 器與前述第4電阻器之電阻相等。 再者有關申凊專利範圍第3項之差動電壓放大電路，其 中前述減法電路部具有：一第2差動放大器；一第5電阻 器，係連接於前述第2差動放大器之輸出端子；及一第6 電阻器，係連接於前述電壓保持部者；而前述第5電阻器 與第6電阻器之連接點係連接至前述第2差動放大器之倒 向輸入端子，前述第i基準電歷係連接至前述第2差動放 大器之正向輪入端子；且前述第5電阻器與前述第6電阻 器之電阻值相等。 20 1241764 坎、發明說明 又，有關申請專利範圍第丨項至第3項之差動電壓放 大包路中，在輸入路徑間短路時，第1及第2開關部呈導 通狀％，亚藉第3開關部，將第1基準電壓供給至偏壓端 子β藉此，可將第1差動放大器之輸入補償電壓保持於 I[保持部。又，在差動電壓放大時，第1及第2開關部 則呈非導通狀態，並藉第3開關部，將減法電路部之輸 出作為第2基準電壓而供給至偏壓端子。 藉此，可抵消差動電壓放大電路之輸入補償電壓值 因此，不致因輸入補償電壓之影響而縮小差動電壓放 1〇大電路之輸入電壓可能範圍，而可防止測定精確度之下 降。 又藉此，當差動電壓放大電路之輸入補償電壓隨溫 度變動時，亦可隨該變動，抵消輸入補償電壓值。因此 ，相較於習知藉修正計算進行之電壓值之測定方法，由 15於可進行精確度提南之電壓測定，故可進行更正確之電 池剩餘量之測定。 且藉此，每次測定差動電壓時，不須以Μρυ進行去 除輸入補俏電壓值之景〉響之修正計算。因此，可使控制 簡單化，並可謀求電流耗費之降低。 20 再者藉此，由於不須將輸入補償電壓記憶於MPU， 故不須在兩精確度之測定環境下，算出輸入補償電壓， 並將之記憶於MPU。因此，可使測試裝置簡單化，同時 ，使測試低價化。 又，有關申請專利範圍第4項之差動電壓放大電路 10 1241764 玖、發明說明 ’其中前述第1差動放大器 之週期進行。 之輪入路徑之短路係依規定 5 10 /此，可錢地進行輸人補償電Μ值之更新，且亦 2因溫度等造成之經時變化之補償變動，«輸入補 β 貝屋值。因此，相較於藉習知之修正計算所求得之電 [值可測定精確度更高之電壓值。 又’有时請專利範圍第5項之差動電壓放大電路 ，其中電麼保持部係具有電容器而構成者。藉此，電壓 保持部於輸人路徑間短路時，可保持自第丨差動放大器 輸出之短路輸出電壓。 又’有關申請專利範圍第6項之差動電壓放大電路 ’其中前述第1輸入路徑中前述第1輸入端子至前述第i 開關部之路徑或前述第2輸入路徑中前述第2輸入端子至 前述第1開關部之路徑至少一者具有輸入開關部，前述 15輸入開關部於差動電壓放大時呈連接狀態，而於輸入路 徑短路時則呈非連接狀態。 错此’因輸人開關部呈料通狀態，而可自外部電 路切斷ϋ動電壓放大電路’且可進行輸人路徑間之短路 20又’有關中請專利範圍第7項之差動電壓放大電路，其 中於則述第3開關部至前述第3電阻器之路徑具有第】緩 衝放大器。 藉此，藉不致使將流至第丨電阻器或第3電阻器之電 流提供至偏壓端子之第1或第2基準電壓產生變化，可將 1241764 玖、發明說明 ， 第〗差動放大器之輸入電壓之偏壓點維持一定，因此可 獲得高精確度之差動電壓測定結果。又，令第〗基準電 壓為自電阻分壓之分壓點產生之電路構造，可自由設定 弟1基準電塵之產生方法。 - 5 又，有關申請專利範圍第8項之差動電壓放大電路 ，其中前述第1輸入端子至前述第〗電阻器之路徑具有第 2緩衝放大态，前述第2輸入端子至前述第2電阻器之路 徑具有第3緩衝放大器。 藉此，由於施加於第〗及第2電阻器之電壓值不致因 · 1〇流至第1電阻器及第3電阻器而受到影響，故可獲得高精 確度之差動電壓測定之結果。 · 又，有關申請專利範圍第9項之差動電壓放大電路 ： ’其中電壓保持部至第6電阻器之路徑具有第4緩衝放大 器。 5 藉此，不論電壓保持部之電路結構，施加於第6電 阻杰之電壓皆可保持_定。又，自電壓保持部之電流流 出或電流流入受到控制，而可減低電壓變動。因此，可 · 獲得高精確度之差動電壓測定之結果。且可使電壓保持 部之容量更小。 · 又，有關申凊專利範圍第1〇項之差動電壓放大電路 ’ ，其中於前述第1基準電壓輸入至前述第2差動放大器之 正向輸入端子之路徑具有第4開關部，前述第4開關部於 差動電壓放大時呈連接狀態，而於輸入路徑短路時則呈 非連接狀態。 12 1241764 玖、發明說明 係用以設定前述差動放大器之輸入電厂堅之偏i 點者，而前 述偏壓設定部係於輪入路徑間短路時，設定第！基準電塵 而方、差動電璧放大時，設定保持於前述電㈣持部之短 路輸出電壓與前述第1基準電壓之差分電塵。 5 藉此，可抵消差動電壓放大電路之輸人補償電廢值1241764 玖, the differential voltage amplifying circuit of the differential voltage amplifying circuit when the pen pressure is amplified by the invention description adds or subtracts the value of the compensation voltage value obtained before is used as the value of the corresponding charging current or discharging current, and The remaining capacity is calculated by the remaining capacity calculation circuit 109. This can reduce the error of the calculation result 5 of the remaining capacity of the battery 101 of the compensation voltage. The prior art documents are shown below. Japanese Patent Application Laid-Open No. 7/191110, as shown in the above-mentioned conventional technique, detects the input compensation voltage value of the differential voltage amplifying circuit, adds or subtracts this value from the output voltage value, and performs the detection result at 10 In the correction method, a state in which the input voltage value of the differential voltage amplifier circuit includes the input compensation voltage value. As a result, the differential voltage amplifier circuit originally has a range of input voltage that may have more input compensation voltage, so the range of the input compensation voltage is deducted from the input voltage of the differential voltage amplifier circuit in the conventional art range. Therefore, in order to reduce the possible input voltage range for measurement, the measurement range is limited, and there is a problem that the measurement accuracy is reduced. Furthermore, when the input compensation voltage changes with temperature, an error occurs between the corrected calculated output voltage value and the actual differential voltage due to the difference in the measured temperature. Since the remaining battery is calculated based on the accumulated round-off voltage value, the measurement error is also accumulated, and there is a problem that the actual remaining battery is so large that it cannot be ignored. In order to avoid this problem, the remaining battery capacity is still sufficient, but a warning of insufficient battery capacity has to be issued, and the problem that the battery capacity cannot be used to the maximum can not be avoided. Whenever «, when measuring the input compensation voltage value, there are also problems such as an increase in the burden of deletion or an increase in current consumption. In addition, since the input differential voltage of the differential voltage amplifier circuit includes the input compensation voltage value, whenever the differential voltage is measured, a correction calculation to remove the influence of the compensation voltage value by the wheel-in differential voltage must be performed. Therefore, in order to make corrections, the MPU must be used for calculation processing, which not only has complicated control, but also has large current toll fees. In addition, since the input compensation voltage is memorized in the MPU, it is necessary to calculate the input compensation voltage in a high-accuracy environment to memorize the test in the Mpu. Therefore, there is a problem that the test device is huge and the test has a heavy responsibility. [Summary of the Invention] The present invention was created by the present invention to solve at least one of the problems of the conventional techniques, and its purpose is to provide a differential voltage amplifying circuit, which can prevent the possible range of the input voltage from being reduced, without having to use an Mpu or the like. The correction is calculated, and the influence caused by temperature changes is reduced, and the difference of high dynamic accuracy can be detected. DISCLOSURE OF THE INVENTION In order to achieve the aforementioned object, the differential voltage amplifying circuit related to the scope of application for patent No. 1 has a first differential amplifier, and it further has: a first switch section, which makes the first input terminal to the first! The first of the differential amplifier! Input channel 20 control and the second input terminal to the first! The short-circuit between the input paths of the second input path of the differential amplifier;-the voltage holding section is the one that maintains the short-circuit output voltage from the first differential amplifier output when the input is short-circuited; When the short-circuit output voltage is maintained, the output terminal of the first differential amplifier is connected to the voltage holding section; a subtraction circuit 1241764 发明, the invention description section, is subtracted and held in the aforementioned electric dust holding section. Short-circuit output dust and reference] Repeated reference power; and a switch. That is, when the short circuit between the input paths, the first reference voltage is supplied to 5 10 15 for the bias terminal of the bias point of the input voltage of the differential amplifier, and the differential voltage is amplified. In this case, the output of the subtraction circuit unit is used as the second reference ㈣ and is supplied to the bias terminal. The differential electric dust amplifying circuit related to the second item of the scope of patent application further includes a first resistor connected to the aforementioned input terminal and a second resistor connected to the aforementioned second input terminal. A first resistor is connected to the aforementioned bias terminal; and a fourth resistor is connected to the output terminal of the first differential amplifier; and the aforementioned first] resistor is connected to the third resistor The point is connected to the forward input terminal of the first differential amplifier, and the connection point of the second resistor and the fourth resistor is connected to the backward input terminal of the first differential amplifier; The resistance value of the resistor is equal to that of the second resistor, and the resistance of the third resistor is equal to that of the fourth resistor. Furthermore, regarding the differential voltage amplifying circuit of claim 3 of the patent scope, the aforementioned subtraction circuit section has: a second differential amplifier; and a fifth resistor connected to the output terminal of the aforementioned second differential amplifier; And a sixth resistor, which is connected to the voltage holding section; and the connection point between the fifth resistor and the sixth resistor is connected to the inverted input terminal of the second differential amplifier, and the i-th reference power Connected to the forward wheel-in terminal of the second differential amplifier; and the resistance values of the fifth resistor and the sixth resistor are equal. 20 1241764, the invention description, and in the differential voltage amplification package of the patent application scope items 丨 to 3, when the input path is short-circuited, the first and second switch sections are in a conductive state%. (3) The switch section supplies the first reference voltage to the bias terminal β, thereby maintaining the input compensation voltage of the first differential amplifier at the I [holding section. When the differential voltage is amplified, the first and second switching sections are in a non-conducting state, and the output of the subtraction circuit section is supplied to the bias terminal through the third switching section as a second reference voltage. Therefore, the input compensation voltage value of the differential voltage amplifier circuit can be cancelled. Therefore, the possible range of the input voltage of the large circuit is not reduced due to the influence of the input compensation voltage, and the measurement accuracy can be prevented from lowering. In addition, when the input compensation voltage of the differential voltage amplifier circuit changes with temperature, the input compensation voltage value can also be offset with the change. Therefore, compared with the conventional method for measuring the voltage value by correcting the calculation, the voltage can be accurately measured from 15%, so the more accurate measurement of the battery remaining amount can be performed. And by this, each time the differential voltage is measured, it is not necessary to use Μρυ to perform a correction calculation to remove the scene of the input patch voltage value. Therefore, control can be simplified, and current consumption can be reduced. 20 Furthermore, because it is not necessary to memorize the input compensation voltage in the MPU, it is not necessary to calculate the input compensation voltage under the two-accuracy measurement environment and store it in the MPU. Therefore, the test device can be simplified, and at the same time, the test can be reduced in price. In addition, the differential voltage amplifying circuit 10 in the scope of patent application 10 1241764 发明, description of the invention ′ wherein the cycle of the aforementioned first differential amplifier is performed. The short circuit of the turn-in path is in accordance with the regulations 5 10 / This can be used to update the input compensation value, and also the compensation change over time due to temperature, etc. «Enter the supplementary β shell value. Therefore, the voltage value can be measured with higher accuracy than the value obtained by the conventional correction calculation. In some cases, the differential voltage amplifying circuit of item 5 of the patent is required, in which the capacitor holding section is constituted by a capacitor. Thereby, when the voltage holding section is short-circuited between the input paths, the short-circuit output voltage output from the first differential amplifier can be maintained. "Differential voltage amplifying circuit in the sixth range of the patent application", wherein the path from the first input terminal to the i-th switching section in the first input path or the second input terminal to the foregoing in the second input path At least one of the paths of the first switch section has an input switch section. The aforementioned 15 input switch section is connected when the differential voltage is amplified, and is disconnected when the input path is short-circuited. Wrong this 'Because the input switch part is in a material-passing state, the dynamic voltage amplifier circuit can be cut off from the external circuit' and a short circuit between input paths can be performed. In the amplifier circuit, a path from the third switching section to the third resistor has a first buffer amplifier. Therefore, by not causing a change in the first or second reference voltage that supplies the current flowing to the third resistor or the third resistor to the bias terminal, 1241764, the invention description, and the first differential amplifier The bias point of the input voltage is kept constant, so a highly accurate differential voltage measurement result can be obtained. In addition, let the reference voltage be a circuit structure generated from the voltage-dividing point of the resistance partial voltage, and the method of generating the reference electric dust can be set freely. -5 The differential voltage amplifying circuit of the eighth aspect of the patent application, wherein the path from the first input terminal to the aforementioned resistor has a second buffered amplification state, and the second input terminal to the aforementioned second resistor The path has a third buffer amplifier. As a result, the voltage values applied to the first and second resistors are not affected by the flow of 10 to the first and third resistors, so that a highly accurate differential voltage measurement result can be obtained. · The differential voltage amplifying circuit in the ninth scope of the patent application: ′ The path from the voltage holding section to the sixth resistor has a fourth buffer amplifier. 5 In this way, regardless of the circuit structure of the voltage holding section, the voltage applied to the sixth resistor can be held constant. In addition, the current flow or current flow from the voltage holding section is controlled, and the voltage fluctuation can be reduced. Therefore, a highly accurate differential voltage measurement result can be obtained. In addition, the capacity of the voltage holding section can be made smaller. In addition, regarding the differential voltage amplifier circuit of the patent application No. 10, wherein a path for inputting the first reference voltage to the forward input terminal of the second differential amplifier includes a fourth switching section, the aforementioned first 4 The switch section is connected when the differential voltage is amplified, and it is disconnected when the input path is short-circuited. 12 1241764 发明, description of the invention It is used to set the bias i point of the input power plant of the aforementioned differential amplifier, and the aforementioned bias setting section is set when the short-circuit between wheel paths is set. Reference electric dust When the square or differential electric cymbal is amplified, a differential electric dust having a short circuit output voltage held in the electric holding portion and the first reference voltage is set. 5 This can offset the input power compensation value of the differential voltage amplifier circuit.
。因此，不致因輸人補償電壓之影響而縮小差動電麼放 大電路之可輸人範圍，而可防止敎精確度之下降 。當差動㈣放大電路之輸人補償電壓隨溫度變動時， 亦可隨該變動，抵消輸入補償電壓值。 10 圖式簡單說明 第1圖係第1實施形態之電路圖。 第2圖係第2實施形態之電路圖。 第3圖係第3實施形態之電路圖。 第4圖係第4實施形態之電路圖。 15 第5圖係第5實施形態之電路圖。. Therefore, the input range of the differential circuit cannot be reduced due to the influence of the input compensation voltage, and the decrease in the accuracy can be prevented. When the input compensation voltage of the differential amplifier circuit changes with temperature, the input compensation voltage value can also be offset with the change. 10 Brief Description of Drawings Figure 1 is a circuit diagram of the first embodiment. Fig. 2 is a circuit diagram of the second embodiment. Fig. 3 is a circuit diagram of the third embodiment. Fig. 4 is a circuit diagram of the fourth embodiment. 15 FIG. 5 is a circuit diagram of the fifth embodiment.
第6圖係第6實施形態之電路圖。 第7圖係習知技藝之電路圖。 【實施方式】 20用以實施發明之最佳形態 以下，根據第1圖至第5圖，一面參照圖式，一面詳 細說明就本發明差動電壓放大電路加以具體化之實施形態 利用第1圖之電路圖，說明第丨實施形態。第丨圖係 14 1241764 玖、發明說明Fig. 6 is a circuit diagram of the sixth embodiment. Fig. 7 is a circuit diagram of a conventional technique. [Embodiment] 20 Best Modes for Implementing the Invention Below, referring to Figures 1 to 5, the detailed description of the embodiment of the differential voltage amplifier circuit of the present invention will be described with reference to the drawings using Figure 1. The circuit diagram illustrates the first embodiment. Figure 丨 14 1241764 发明 Description of the invention
SW2及差動電壓放大電路部輸人端子qti。差動電麼放大 又，電阻器R3之一端連接至偏 义4之一端則連接至差動放大器〇p 1 電路部輸出端子0T1係連接至電池剩餘量演算部（圖中未 不），而該電池剩餘量演算部依差動電壓放大電路部〗之測 10定結果，算出電池剩餘量。SW2 and differential voltage amplifying circuit part input terminal qti. The differential electric amplifier is amplified, and one end of the resistor R3 is connected to one end of the bias 4 is connected to the differential amplifier. The output terminal 0T1 of the circuit section is connected to the remaining battery calculation section (not shown in the figure), and the The remaining battery calculation unit calculates the remaining battery quantity based on the measurement result of the differential voltage amplifying circuit unit.
端（節點5)則連接至開關SW2及電阻器R6。減法電路Terminal (node 5) is connected to switch SW2 and resistor R6. Subtraction circuit
子vo以電阻器R7為中介連接至差動放大器〇p2之正向 輸入端子。開關SW3係將減法電路部3之輸出及偏壓輸入 端子VO連接為可切換，並連接至偏壓端子VR。 此外，由減法電路部3及開關SW3構成用以設定差動 2〇放大器OP1之輸入電壓之偏壓點之偏壓設定部。 於輸入端子INI、IN2施加輸入電壓viNl、VIN2，而 於偏壓輸入端子V0施加偏壓v〇1。又，分別將輸入路徑 間短路時之差動放大器〇ρι之輸出定義為輸出電壓 νουτ】，將差動電壓放大時之差動放大器〇ρι之輸出定義 16 1241764 玖、發明說明 為輸出電壓V0UT1A，將差動放大器0P2之輸出定義為輸 出電壓V0UT2，將差動放大器0P1、0P2之輸入補償電壓 分別定義為VOFF1、V0FF2。The sub vo is connected to the positive input terminal of the differential amplifier oop2 through the resistor R7 as an intermediate. The switch SW3 connects the output of the subtraction circuit section 3 and the bias input terminal VO to be switchable and is connected to the bias terminal VR. In addition, the subtraction circuit section 3 and the switch SW3 constitute a bias setting section for setting a bias point of the input voltage of the differential 20 amplifier OP1. Input voltages viNl and VIN2 are applied to the input terminals INI and IN2, and a bias voltage vO1 is applied to the bias input terminal V0. In addition, the output of the differential amplifier 〇ρι when the short-circuit between the input paths is respectively defined as the output voltage νουτ], and the output of the differential amplifier 〇ρι when the differential voltage is amplified are defined as 16 1241764. The invention description is the output voltage V0UT1A, The output of the differential amplifier 0P2 is defined as the output voltage V0UT2, and the input compensation voltages of the differential amplifiers 0P1 and 0P2 are defined as VOFF1 and V0FF2, respectively.
接著，說明輸入路徑間短路時之動作。於進行差動電 5 壓之放大動作前，先進行將差動放大器0P1之輸入補償電 壓V0FF1保持於電壓保持部2之動作。於輸入路徑間短路 時，開關SW1、SW2呈導通狀態，開關SW4、SW5呈非 導通狀態。且，開關SW3將偏壓端子VR及偏壓輸入端子 V0連接。 10 於開關SW1為連接狀態時，將施加於節點Nl、N2之 電壓定義為短路電壓VINR。且，於偏壓端子VR施加偏壓 V01。此時，於節點N3施加電阻器Rl、R3之分壓電壓， 若該電壓值以節點N1為基準時，便以（第1式）表示。 (VOl-VINR) X RR1/ (RR1 + RR3)…（第 1 式） 15 同樣地於節點4施加電阻器R2、R4之分壓電壓，若Next, an operation when a short circuit between input paths is described. Before carrying out the amplification operation of the differential voltage, the operation of maintaining the input compensation voltage V0FF1 of the differential amplifier 0P1 in the voltage holding section 2 is performed. When the input path is short-circuited, switches SW1 and SW2 are turned on, and switches SW4 and SW5 are turned off. The switch SW3 connects the bias terminal VR and the bias input terminal V0. 10 When the switch SW1 is connected, the voltage applied to the nodes N1 and N2 is defined as the short-circuit voltage VINR. A bias voltage V01 is applied to the bias terminal VR. At this time, a divided voltage of the resistors R1 and R3 is applied to the node N3, and if the voltage value is based on the node N1, it is expressed by (1st formula). (VOl-VINR) X RR1 / (RR1 + RR3) ... (Formula 1) 15 Similarly, apply the divided voltage of resistors R2 and R4 to node 4, if
該電壓值以節點N2為基準時，便以（第2式）表示。 (VOUT1 — VINR) X RR2/ (RR2 + RR4)…（第 2 式 由於差動放大器OP1之倒向輸入端子與正向輸入端子 20 為相同電壓，故若考慮輸入補償電壓VOFF1時，（第3式 )便成立。 (VOl-VINR) X RR1/ ( RR1 + RR3 ) +VOFF1-( VOUT1 —VINR) X RR2/ (RR2 + RR4)…（第 3 式） 利用RR1二RR2、RR3 = RR4之關係，整理（第3式） 17 1241764 玖、發明說明 ，便獲得（第4式）。 V0UT1 = V01+ ( 1 + RR4/RR2) X V0FF1··.(第 4 式 ) 在此，定義放大率AV=RR4/RR2，若考慮AV大於1 5 時，輸入路徑間短路時之差動放器0P1之輸出電壓V0U1 便以（第5式）表示。 V0UT1 = V01 + AVx V0FF1··.(第 5 式）When this voltage value is based on the node N2, it is expressed by (Expression 2). (VOUT1 — VINR) X RR2 / (RR2 + RR4) ... (Formula 2 is because the reverse input terminal and differential input terminal 20 of the differential amplifier OP1 have the same voltage. Therefore, if the input compensation voltage VOFF1 is considered, (the third (VOl-VINR) X RR1 / (RR1 + RR3) + VOFF1- (VOUT1 —VINR) X RR2 / (RR2 + RR4) ... (Formula 3) Use the relationship between RR1 and RR2, RR3 = RR4 , Finishing (formula 3) 17 1241764 玖, the description of the invention, we get (formula 4). V0UT1 = V01 + (1 + RR4 / RR2) X V0FF1 ··. (Formula 4) Here, define the magnification AV = For RR4 / RR2, if AV is greater than 15, the output voltage V0U1 of the differential amplifier 0P1 when the input path is short-circuited is represented by (Formula 5). V0UT1 = V01 + AVx V0FF1 ·· .. (Formula 5)
再者，由於開關SW2為導通狀態，故電容器C1充電 至輸出電壓V0UT1之電壓。因而即使開關SW2為非連接 10 狀態，仍可保持其電壓。 其次，說明差動電壓放大時之動作。於差動電壓放大 時，開關SW1、SW2呈非導通狀態，開關SW4、SW5則 呈導通狀態。且開關SW3將偏壓端子VR與減法電路部3 之輸出連接。 15 於節點N5保持有以（第5式）求得之電壓VOUT1。Furthermore, since the switch SW2 is on, the capacitor C1 is charged to the voltage of the output voltage VOUT1. Therefore, even if the switch SW2 is in the non-connected state, its voltage can be maintained. Next, the operation when the differential voltage is amplified will be described. When the differential voltage is amplified, switches SW1 and SW2 are in a non-conducting state, and switches SW4 and SW5 are in a conducting state. The switch SW3 connects the bias terminal VR to the output of the subtraction circuit section 3. 15 A voltage VOUT1 obtained by (Expression 5) is held at the node N5.
此時，於節點6施加電阻器R5、R6之分壓電壓，且該電 壓值以（第6式）表示。 (VOUT2 - VOUT1 ) X RR6/ ( RR5 + RR6 ) + VOUT1·..(第 6 式） 20 由於於差動放大器OP2之正向輸入端子施加偏壓VO 1 ，故若考慮差動放大器OP2之輸入補償電壓VOFF2時，（ 第7式）便成立。 V01 + V0FF2- ( VOUT2-VOUT1 ) x RR6/ ( RR5 + RR6) + VOUT1··.(第 7 式） 18 1241764 玖、發明說明 由於RR5 = RR6，故整理（第7式），便獲得（第8式 )° V0UT2 = 2V01 —V0UTl + 2x V0FF2··.(第 8 式） 將（第5式）代入（第8式）之V0UT1，便獲得（第 5 9式）At this time, a divided voltage of the resistors R5 and R6 is applied to the node 6, and the voltage value is expressed by (Expression 6). (VOUT2-VOUT1) X RR6 / (RR5 + RR6) + VOUT1 · .. (Formula 6) 20 Since the bias input VO 1 is applied to the positive input terminal of the differential amplifier OP2, if the input of the differential amplifier OP2 is considered When the offset voltage VOFF2, (Formula 7) is established. V01 + V0FF2- (VOUT2-VOUT1) x RR6 / (RR5 + RR6) + VOUT1 ··. (Formula 7) 18 1241764 发明, description of the invention Because RR5 = RR6, so finishing (Formula 7), we get (Formula 8) ° V0UT2 = 2V01 —V0UTl + 2x V0FF2 ··. (Formula 8) Substituting (Formula 5) into V0UT1 of (Formula 8), we obtain (Form 5-9)
V0UT2 = V01-AVx V0FF1 + 2X V0FF2··.(第 9 式） 由於開關SW4、SW5為導通狀態，故於節點Nl、N2 分別施加輸入電壓VIN1、VIN2。並於偏壓端子VR施加差 動放大器0P2之輸出電壓V0UT2。因此，差動放大器 10 OP1之差動電壓放大時之輸出電壓VOUT1A係與（第3式 )同樣地求得，如（第10式）。 (VOUT2-VIN1) X RR1/ (RR1 + RR3) +VOFF1 + VIN1 = ( VOUT1A - VIN2 ) x RR2/ ( RR2 + RR4 ) + VIN2…（第10式） 15 利用RR1 = RR2、RR3 = RR4之關係，整理（第3式）V0UT2 = V01-AVx V0FF1 + 2X V0FF2 ··. (Equation 9) Since the switches SW4 and SW5 are on, the input voltages VIN1 and VIN2 are applied to the nodes N1 and N2, respectively. An output voltage VOUT2 of the differential amplifier OP2 is applied to the bias terminal VR. Therefore, the output voltage VOUT1A when the differential voltage of the differential amplifier 10 OP1 is amplified is obtained in the same manner as (Expression 3), such as (Expression 10). (VOUT2-VIN1) X RR1 / (RR1 + RR3) + VOFF1 + VIN1 = (VOUT1A-VIN2) x RR2 / (RR2 + RR4) + VIN2 ... (Formula 10) 15 Use the relationship between RR1 = RR2, RR3 = RR4 , Finishing (style 3)
，且利用放大率AV，便獲得（第11式）。 V0UT1A= VOUT2 +AVx ( VIN1 — VIN2 ) + ( AV + 1 )x VOFF1···(第 11 式） 由於在（第11式）中，放大率AV > 1，故可將（ 20 AV+1 )視為AV。又，將（第9式）代入（第11式）之 VOUT2，便獲得（第12式）。 VOUT1A = VOl + AV X ( VIN1 - VIN2 ) + 2 x VOFF2···(第 12 式）。 因此，自（第12式）可知可排除因放大率AV而增加 19 1241764 玖、發明說明 AV倍之差動放大器0P1之輸入補償電壓v〇FFl之影響。 在此，由於差動放大器0P2之輸入補償電壓v〇FF2並未 乘以放大率AV ( AV使用100等值時），而使輸入補償電壓 VOFF2之項（2x VOFF2)之影響較其他項小，故可將之 5 忽視，因此，便獲得（第13式）。 V0UT1A= VOl + AVx ( VIN1 — VIN2 )…（第 13 式 ) 因此，以（第13式）求得之差動放大器〇P1之差動 電壓放大時之輸出電壓VOUT1A經由差動電壓放大電路部 10輸出端子οτι輸出。即，具有經施加於偏壓輸入端子vo 施加之偏壓V 01調整之偏壓點，而不受輸入補償電壓 VOFF1之影響’而可將依放大率av倍增之輸入電壓viN 1 、VIN2之電壓差之輸出電壓V0UT1A輸出。 藉此，可抵消差動放大器OP1之輸入補償電壓值 15 V〇FF 1。因此，藉輸入補償電壓依av倍增，在差動電壓 放大電路中不致使可差動放大之可輸入電壓範圍縮小，而 可防止測定精確度之下降。 又，藉此，當差動放大器OP1之輸入補償電壓VQFF1 Ik /JDL度變動時’亦可隨該變動抵消輸入補償電壓VOJ7 jq。 20因此，相較於習知之修正計算之電壓值之測定方法，由於 可進行精確度提高之電壓測定，而可進行更正確之電池剩 餘量測定。 且，藉此，相較於習知技藝，每次測定差動電壓時， 便不須以MPU進行去除輸入補償電壓v〇FFl之影響之修 20 1241764 玖、發明說明 正计异。因此，可使控制簡單化，且使伴隨差動電壓測定 之電流粍費降低。再者，由於不須將輸入補償電壓v〇ffi 記憶於MPU，故不須在高精確度之測定環境下算出輸入補 4貝電壓，並將之記憶於MPU。因此，可使測試裝置簡單化 5 ’且使測試低價化。 在此，在差動電壓放大時之動作期間，可以規定之週 期進行輸入路徑間之短路動作。即，可定期地更新保持於 電谷态C1之差動放大器QP1之輸出電壓ν〇υτι。 藉此，可定期地更新輸入補償電壓V0FF1，而可隨溫 10度等造成之經時變化之補償之變動，抵消輸人補償電麼 V0FF1。因此，相較於藉習知修正計算求得之電壓值，可 測定精確度更高之電壓值。 此外，在輸入路徑短路時，藉開關SW4、SW5呈非導 通狀態，不但可自外部電路切斷差動電壓放大電路部！， 15且可進行輸入補償電壓V0FF1之測量。 接著，利用第2目，說明第2實施形態。帛2圖之差 動電壓放大電路部除了具有第1實施形態之差動電壓放大 電路部1外，尚具有緩衝放大器驗，該緩衝放大器bai 係連接於電麼保持部2之電容器ci與減法電路部3之電 2〇 阻哭 a » 之間。在此，由於輸入路徑間之短路時及差動電壓 放大時之動作與第1實施形態相同，故省略詳細說明。 在差動電壓放大時，保持於電容器C1之輸出電壓 V0UT1經由緩衝放大器BA1輸入至減法電路部3。在減法 電路部3中，經由電阻器R5、R6流入之電流係由缓衝放 21 1241764 玖、發明說明 大為BA1所供认，而 θ 因此，電容 叩 口而不疋由電容器Cl供給 器C1之保持電壓可維持一定值。 -方面，當不具有緩衝放大器bai時，差動電星放 動作期間，進仃自電容器C1放電至電阻器R6。此 8、由於電容器C1之保持電壓降低，而於差動放大器And using the magnification AV, it is obtained (Formula 11). V0UT1A = VOUT2 + AVx (VIN1 — VIN2) + (AV + 1) x VOFF1 ··· (Formula 11) Since the magnification ratio AV > 1 in (Formula 11), (20 AV + 1 ) As AV. Also, by substituting (Formula 9) into VOUT2 of (Formula 11), we obtain (Formula 12). VOUT1A = VOl + AV X (VIN1-VIN2) + 2 x VOFF2 ... (Formula 12). Therefore, it can be known from (12th formula) that the increase due to the amplification factor AV can be ruled out. 19 1241764 玖, description of the invention The effect of the input compensation voltage v0FF1 of the differential amplifier OPP1 of AV times. Here, because the input compensation voltage v0FF2 of the differential amplifier 0P2 is not multiplied by the amplification factor AV (when AV is used at an equivalent value of 100), the influence of the term of the input compensation voltage VOFF2 (2x VOFF2) is smaller than other terms. Therefore, 5 can be ignored, and thus obtained (Formula 13). V0UT1A = VOl + AVx (VIN1 — VIN2) ... (Formula 13) Therefore, the output voltage VOUT1A during amplification of the differential voltage of the differential amplifier 〇P1 obtained by (Formula 13) passes through the differential voltage amplifier circuit section 10 Output terminal οτι output. That is, it has a bias point adjusted by the bias voltage V 01 applied to the bias input terminal vo without being affected by the input compensation voltage VOFF1 ', and the voltages of the input voltages viN 1 and VIN2 that are multiplied by the amplification factor av can be increased. Different output voltage V0UT1A output. Thereby, the input compensation voltage value of the differential amplifier OP1 can be canceled to 15 V0FF 1. Therefore, by multiplying the input compensation voltage by av, the input voltage range that can be differentially amplified is not reduced in the differential voltage amplifying circuit, and the measurement accuracy can be prevented from decreasing. In addition, when the input compensation voltage VQFF1 Ik / JDL degree of the differential amplifier OP1 changes, it can also cancel the input compensation voltage VOJ7 jq with the change. 20 Therefore, compared with the conventional method for measuring the calculated voltage value, it is possible to perform a more accurate measurement of the battery voltage because of the improved accuracy of the voltage measurement. Moreover, compared with the conventional art, each time the differential voltage is measured, it is not necessary to use MPU to perform the repair to remove the influence of the input compensation voltage v0FF1. 20 1241764 发明 Description of the invention Therefore, the control can be simplified, and the current cost associated with the measurement of the differential voltage can be reduced. Furthermore, since it is not necessary to memorize the input compensation voltage v0ffi in the MPU, it is not necessary to calculate the input compensation voltage in a high-precision measurement environment and memorize it in the MPU. Therefore, the test device can be simplified 5 'and the test can be made inexpensive. Here, during the operation period when the differential voltage is amplified, a short circuit operation between the input paths can be performed at a predetermined period. That is, the output voltage νουτι of the differential amplifier QP1 held in the electric valley state C1 can be periodically updated. In this way, the input compensation voltage V0FF1 can be updated regularly, and the compensation change V0FF1 can be offset with the change of compensation over time caused by the temperature of 10 degrees. Therefore, the voltage value can be measured with higher accuracy than the voltage value calculated by conventional correction. In addition, when the input path is short-circuited, the switches SW4 and SW5 are in a non-conducting state, and the differential voltage amplifier circuit section can be cut off from an external circuit! , 15 and can measure input compensation voltage V0FF1. Next, the second embodiment will be described using the second item. The differential voltage amplifying circuit section of Fig. 2 has a buffer amplifier test in addition to the differential voltage amplifying circuit section 1 of the first embodiment. The buffer amplifier bai is connected to the capacitor ci and the subtraction circuit of the capacitor holder 2 Part 3 of the electricity 20 阻 resistance cry a »between. Here, the operation during the short circuit between the input paths and during the amplification of the differential voltage is the same as that of the first embodiment, so detailed description is omitted. When the differential voltage is amplified, the output voltage V0UT1 held in the capacitor C1 is input to the subtraction circuit section 3 through the buffer amplifier BA1. In the subtraction circuit section 3, the current flowing through the resistors R5 and R6 is recognized by the buffer amplifier 21 1241764 发明, the invention description is largely recognized by BA1, and θ, therefore, the capacitor is not supplied by the capacitor Cl supply C1. The holding voltage can be maintained at a certain value. -On the other hand, when the buffer amplifier bai is not provided, the capacitor C1 is discharged to the resistor R6 during the operation of the differential electric satellite amplifier. 8. Because the holding voltage of capacitor C1 decreases,
⑽m生誤差’故無法獲得高精確度之輸出電壓 1A且為避免前述問題，當使電容器⑴之容量增大 時，則發生電容器力之電路佔有面積增加等問題。 10 “此藉具有緩衝放大器BA1，不論電壓保持部2之 電㈣C1谷量之大小，皆可將電壓保持部2之保持電壓 保持一定。因&，可獲得更高精確度之輸出電壓V0UT1A 且由於可使電壓保持部2之電容器ci之容量縮小， 故可減少電容器C1之電路佔有面積。生 m produces errors', so high-accuracy output voltage 1A cannot be obtained and in order to avoid the aforementioned problems, when the capacity of the capacitor 增大 is increased, problems such as an increase in the area occupied by the circuit of the capacitor force occur. 10 "With the buffer amplifier BA1, the holding voltage of the voltage holding unit 2 can be kept constant regardless of the amount of the electric voltage C1 valley of the voltage holding unit 2. Because of &, a more accurate output voltage V0UT1A can be obtained Since the capacity of the capacitor ci of the voltage holding section 2 can be reduced, the circuit occupation area of the capacitor C1 can be reduced.
其-人，利用第3圖說明第3實施形態。第3圖之差動 15電壓放大電路部1C除了具有第2實施形態之差動電壓放 大電路部1B外’尚具有緩衝放大器BA2，該緩衝放大器 BA2係連接於開關SW3與偏壓端子VR之間。又，偏壓輸 入端子VO連接有電阻器R8、R9,且供給至偏壓輸入端子 VO之偏壓V01為電阻器R8、R9之分壓。在此，由於差 20動電壓放大電路部1C之動作與第丨實施形態相同，故省 略詳細說明。 於輸入路徑短路時，偏壓V01經由缓衝放大器BA2 及偏壓端子VR施加至電阻器R3。因此，經由電阻器R1 、R3流入之電流係由緩衝放大器BA2所供給。因此，偏 22 1241764 玖、發明說明 壓V01可維持一定值。 另一方 斗 面’若不具有緩衝放大器BA2時，因流至電阻 即R1及R3之電流使為分壓電壓之偏壓Vo!產生變化。 果產生無法獲得南精確度之輸出電壓之問題。 “口此，藉具有緩衝放大器ΒΑ2，流至電阻器R1及R3 之電流不致流至偏壓輸入端子V〇。是故，不致使偏壓 又化藉此’可獲得高精確度之差動電壓測定結果。 可使外β補^電壓Mi為自電阻分壓之分壓點產生之 電路、。構❿可隨意地設定外部補償電壓V⑴之產生方法 10 。 15 20The third embodiment will be described with reference to FIG. 3. The differential 15 voltage amplifier circuit section 1C of FIG. 3 has a buffer amplifier BA2 in addition to the differential voltage amplifier circuit section 1B of the second embodiment. The buffer amplifier BA2 is connected between the switch SW3 and the bias terminal VR. . Further, resistors R8 and R9 are connected to the bias input terminal VO, and the bias V01 supplied to the bias input terminal VO is a divided voltage of the resistors R8 and R9. Here, since the operation of the differential voltage amplifier circuit section 1C is the same as that of the first embodiment, detailed description will be omitted. When the input path is short-circuited, the bias voltage V01 is applied to the resistor R3 via the buffer amplifier BA2 and the bias terminal VR. Therefore, the current flowing through the resistors R1 and R3 is supplied by the buffer amplifier BA2. Therefore, partial 22 1241764 发明, description of the invention V01 can maintain a certain value. On the other hand, if the buffer amplifier BA2 is not provided, the bias voltage Vo !, which is the divided voltage, changes due to the current flowing to the resistors, that is, R1 and R3. As a result, a problem arises in that an output voltage of the South accuracy cannot be obtained. "As a result, by having a buffer amplifier BAA2, the current flowing to the resistors R1 and R3 will not flow to the bias input terminal V0. Therefore, the bias voltage will not be reduced and the high precision differential voltage can be obtained. Measurement results. The circuit that can make the external β offset voltage Mi be generated from the voltage-dividing point of the resistor divider. The method of generating the external compensation voltage V⑴ can be set at will. 15 20
接著，利用第4圖說明第4實施形態。帛4圖之差^ 電壓放大電路部1D &了具有第3實施形態之差動電壓方 大電路。卩1C外，尚具有開關SW6，該開關SW6係連接方 偏壓輸入端子VO與電阻器尺7之間。在此，由於差動制Next, a fourth embodiment will be described with reference to FIG. 4.之 The difference in FIG. 4 ^ The voltage amplifying circuit section 1D & has a differential voltage square circuit having a third embodiment.卩 1C also has a switch SW6, which is connected between the bias input terminal VO and the resistor ruler 7. Here, due to the differential
放大电路邛1D之動作與第i實施形態之差動電壓放大聋 路部相同，故省略詳細說明。 於輸入路徑間短路時，開關SW6呈非導通狀態，而儀 壓νοι經由開關SW3施加至緩衝放大器驗之正向輸入 端子。而於差動電壓放大時，由於開關請6呈導通狀態， 且開關SW3將緩衝放大器BA2之正向輸入端子與減法電 路部3之輸出連接’故偏廢v〇1經由開關綱施加至差 動放大器OP2之正向輸入端子。 士另一方面，若不具有開關SW6時，於輸入路徑間短路 時，偏慶νοι施加至緩衝放A器BA2與差減大器⑽ 23 1241764 玖、發明說明 之動作與第1實施形態相同，故省略詳細說明。 具有二池電池BT1之電池包7以端子PI ' P2為中介 連接於二次電池充電器6。又，端子P3、P4連接AC轉換 器等之電源（圖中未示）。因而，以二次電池充電器6將電 5 池7充電，而可藉差動電壓放大電路部1獲得充電時之差 動電壓測定之結果。 藉此，由於可藉差動電壓放大電路部丨獲得高精確度 之差動電壓測定之結果，故二池電池充電器6可測定高精 確度之充放電電流。是故，可進行更正確之電池剩餘量之 10 測定。 另，本發明並不限於前述實施形態，只要在不超出本 發明曰趣之範圍内可進行各種改良及變形自是無須資言的 。本發明之使用範圍不限於二次電池包、二次電池充電器 ’可用於需測定微小電壓之機器自是無須資言的。 15 產業上可利用性 由以上說明可知，依本發明， 可提供一種差動電壓放 大電路’The operation of the amplifying circuit 邛 1D is the same as that of the differential voltage amplifying deaf circuit section of the i-th embodiment, so detailed description is omitted. When the input path is short-circuited, the switch SW6 is non-conducting, and the instrument voltage νοι is applied to the positive input terminal of the buffer amplifier through the switch SW3. When the differential voltage is amplified, since the switch 6 is turned on, and the switch SW3 connects the positive input terminal of the buffer amplifier BA2 to the output of the subtraction circuit section 3, the partial waste v〇1 is applied to the differential amplifier through the switch platform. OP2 positive input terminal. On the other hand, if the switch SW6 is not provided, when the input path is short-circuited, νοι is applied to the buffer amplifier A2 and the difference amplifier ⑽ 23 1241764 玖. The operation of the invention description is the same as that of the first embodiment. Therefore, detailed description is omitted. A battery pack 7 having a two-cell battery BT1 is connected to a secondary battery charger 6 through a terminal PI 'P2 as an intermediary. The terminals P3 and P4 are connected to a power source (not shown) such as an AC converter. Therefore, the battery 5 is charged by the secondary battery charger 6, and the result of the measurement of the differential voltage during charging can be obtained by the differential voltage amplifying circuit unit 1. Thereby, since the result of the differential voltage measurement with high accuracy can be obtained by the differential voltage amplifier circuit section, the two-cell battery charger 6 can measure the high-accuracy charge and discharge current. Therefore, a more accurate measurement of the remaining amount of battery can be performed. In addition, the present invention is not limited to the aforementioned embodiments, and it is needless to say that various improvements and modifications can be made within the scope of the present invention. The scope of application of the present invention is not limited to secondary battery packs and secondary battery chargers. It is self-explanatory that it can be used in machines that need to measure small voltages. 15 Industrial Applicability As can be seen from the above description, according to the present invention, a differential voltage amplifier circuit can be provided.
可輸入電壓範圍縮小， 少溫度變化造成之影響， 20 者 I：圖式簡單說明】 第1圖係第1實施形態之電路_ 第2圖係第2實施形態之電 第3圖係第3實施形態之電路_ 1241764 玖、發明說明 第4圖係第4實施形態之電路圖。 第5圖係第5實施形態之電路圖。 第6圖係第6實施形態之電路圖。 第7圖係習知技藝之電路圖。 【圖式之主要元件代表符號表】 1.. .差動電壓放大電路部 IB. ..差動電壓放大電路部 IC. ..差動電壓放大電路部 ID. ..差動電壓放大電路部 IE. ..差動電壓放大電路部 2.. .電壓保持部 3…減法電路部 5.. .充電電路 6.. .二次電池充電器 7.. .電池包 101.. .二次電池 102.. .感測電阻 103.. .開關 104…差動電壓放大電路 105.. .微控制器 107.. . A/D轉換器 108.. .電流檢測電路 109.. .剩餘容量演算電路 110.. .開關控制電路 111.. .二池電池端子 112.. .二次電池端子 C1...電容器 IN1·.·輸入端子 IN2…輸入端子 VO...偏壓輸入端子 VR...偏壓端子 OT1...差動電壓放大電路部輸出端 子 OP1...差動放大器 OP2...差動放大器 R1...電阻器 R2...電阻器 27 1241764 玖、發明說明 R3...電阻器 Vss...接地電壓 R4...電阻器 BA1...緩衝放大器 R5...電阻器 BA2…緩衝放大器 R6...電阻器 BA3...緩衝放大器 R7...電阻器 BA4…緩衝放大器 R8...電阻器 P1...端子 R9...電阻器 P2...端子 SW1...開關 P3…端子 SW2...開關 P4...端子 SW3...開關 BT1...二次電池 SW4...開關 SW5…開關 SW6…開關 N1...節點 N2··.節點 N3...節點 N4...節點 N5…節點 N6...節點 28The range of input voltage can be reduced, and the influence caused by temperature changes is small. 20: I: Simple explanation of the diagram.] Figure 1 shows the circuit of the first embodiment _ Figure 2 shows the electricity of the second embodiment Figure 3 shows the third implementation Circuit of the form _ 1241764 发明 Description of the invention Fig. 4 is a circuit diagram of the fourth embodiment. Fig. 5 is a circuit diagram of the fifth embodiment. Fig. 6 is a circuit diagram of the sixth embodiment. Fig. 7 is a circuit diagram of a conventional technique. [Representative symbol table of main components of the figure] 1... Differential voltage amplifier circuit section IB... Differential voltage amplifier circuit section IC... Differential voltage amplifier circuit section ID... Differential voltage amplifier circuit section IE .. Differential voltage amplifier circuit section 2 .. Voltage holding section 3 ... Subtraction circuit section 5 .. Charging circuit 6 .. Secondary battery charger 7. Battery pack 101 .. Secondary battery 102 ... Sensing resistor 103 ... Switch 104 ... Differential voltage amplifier circuit 105 ... Microcontroller 107 ... A / D converter 108 ... Current detection circuit 109 ... Remaining capacity calculation circuit 110 .. switch control circuit 111 .. two battery terminal 112 .. secondary battery terminal C1 ... capacitor IN1 ... input terminal IN2 ... input terminal VO ... bias input terminal VR ... Bias terminal OT1 ... differential voltage amplifier circuit output terminal OP1 ... differential amplifier OP2 ... differential amplifier R1 ... resistor R2 ... resistor 27 1241764 发明, invention description R3 .. .Resistor Vss ... ground voltage R4 ... resistor BA1 ... buffer amplifier R5 ... resistor BA2 ... buffer amplifier R6 ... resistor BA3 ... buffer amplifier R7 ... resistor BA4 …slow Amplifier R8 ... Resistor P1 ... Terminal R9 ... Resistor P2 ... Terminal SW1 ... Switch P3 ... Terminal SW2 ... Switch P4 ... Terminal SW3 ... Switch BT1 ... Secondary battery SW4 ... switch SW5 ... switch SW6 ... switch N1 ... node N2 ... node N3 ... node N4 ... node N5 ... node N6 ... node 28
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/JP2003/004929 WO2004093311A1 (en) | 2003-04-17 | 2003-04-17 | Differential voltage amplifier circuit |
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| TW200423534A TW200423534A (en) | 2004-11-01 |
| TWI241764B true TWI241764B (en) | 2005-10-11 |
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| US9614094B2 (en) * | 2011-04-29 | 2017-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including oxide semiconductor layer and method for driving the same |
| US9245650B2 (en) | 2013-03-15 | 2016-01-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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| JP3102020B2 (en) * | 1990-08-15 | 2000-10-23 | 日本電気株式会社 | Operational amplifier circuit |
| JPH0818353A (en) * | 1994-07-05 | 1996-01-19 | Fuji Electric Co Ltd | Operational amplifier circuit |
| JP2000004129A (en) * | 1998-06-17 | 2000-01-07 | Toshiba Ave Co Ltd | Cmos analog circuit |
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| JPWO2004093311A1 (en) | 2006-07-06 |
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