TWI241593B - Structure and fabricating method of an anti-fuse memory device - Google Patents

Abstract

A method of fabricating an anti-fuse memory device. A substrate is provided with a metal film formed thereon. A silicon layer is formed on the metal film, reacting with part of the silicon layer to form a silicide layer. The unreacted silicon layer is used as a first type conductive layer, and an anti-fuse layer is formed thereon. Then, the first type conductive layer, the silicide layer and the anti-fuse layer are patterned to form word lines and a second type conductive layer is formed on the anti-fuse layer. Thus poly silicon layer formation is shortened, the silicide process is simplified and process time, cost and resistance of the conductive layer are all reduced.

Description

1241593

TECHNICAL FIELD The present invention relates to an improved anti-glare type memory structure and method. This kind of semiconductor process improvement, especially the prior art anti-fuse type memory element for polycrystalline silicon and metal silicide process is a two-memory cell system application one is located in two: memory element 'its Take control. When the anti-solubilizing layer is finished = pole: the anti-dazzle silk layer between the negative electrode, but when the anti-fuse layer is destroyed; = negative electrode: disconnected from each other: and the wiring is designed as the material of the positive and negative electrodes The two-S element is smaller than the traditional two-microstructure memory, and therefore, the type-type memory element provides better protection from the core product = the two-product two-holding property. ， 在 多 说 ； ::: 1 Mod t: Ξ ′ It shows a cross-sectional schematic diagram of the metal silicide process of the conventional anti-refining type memory element. Metal wire and the dielectric layer between wires | y θ ^ No, on, solid-Fan Cheng on semiconductor substrate 1⑽ Electricity: omitted, apply to the metal wire and its wire. The polycrystalline silicon layer is accepted as the polycrystalline silicon layer at the bottom. The polycrystalline silicon layer 111 is on the polycrystalline silicon layer 110 at the bottom. The contact layer 119 and the subsequent titanium nitride layer 12 are made of undoped polycrystalline silicon or amorphous:

1241593 V. Description of the invention (2) On layer 1 11. Next, as shown in Fig. 1B, Putian / 5 Shi Xiyue A "Common-rapid tempering process, so that the reaction of the day and night stone layer and titanium metal layer 119 and Qiu-titanium stone compound Layer 13〇. The formation of it: the titanium argon layer 120 reacts to form Squeen's slave, "*, & ^ 's convergence of the Xixi compound layer 1 30 has a low V coefficient and good thermal stability. A layer of resistance is deposited on the compound. Of type conductive layer 135. The polycrystalline stone layer is used as the first-following step, as shown in Fig. 1C. In the first step, a thermal oxidation process is performed in the first type—the anti-fuse layer 136 1 is formed. The anti-material layer 136 is used as the main element for controlling the anti-fuse memory cell. After the bean, define the anti-dazzle silk layer 136 'titanium compound layer 13 formed before, the first type conductive layer 35 and the polycrystalline silicon layer 110 to form word lines, which include lithography, and etch 2V Filling the dielectric material between the wires after the wire and the subsequent chemical mechanical polishing process 'It is a conventional technique' will not be described in detail here. Finally, as shown in FIG. 1D, an N-doped polycrystalline silicon layer is deposited as the second-type conductive layer 140, and the second-type conductive layer 14 is defined to form bit lines.凊 芩 See Figure 3, which is a perspective view showing the metal silicide process of the conventional antifuse memory element polycrystalline silicon. The bottom polycrystalline silicon layer 丨 i 〇 is formed on the semiconductor substrate 100 in order. The bottom polycrystalline silicon layer 110, the titanium-silicon compound layer 130, the titanium nitride layer 1220, and the first-type conductive layer 135. The bottom polycrystalline silicon layer 110, the titanium silicon compound layer 130, and the first type conductive layer 135 are used as word lines (WL). The second type conductive layer 14 is used as a bit line (BL) and an antifuse layer 136 is sandwiched between the second type conductive layer and the first type conductive layer 135. When this process is used to form a titanium metal oxide, a p + polycrystal must be deposited first.

0503-9867TWF (Nl); TSMC2002-1345; wayne.ptd

1241593

Silicon layer and subsequent undoped polycrystalline or amorphous silicon layer. The deposited titanium metal layer is heated so that the titanium metal layer and the undoped polycrystalline or amorphous silicon layer underneath react to form a titanium metal silicide layer. Thereafter, a polycrystalline silicon layer doped with P + is deposited. The steps for forming the first-type conductive layer are quite tedious, and the multilayer polycrystalline stone deposition must continuously take out the entire batch of wafers from the previous reactor and then put them into the pre-reaction reactor. Not only are the steps complicated, but also the Waiting for a long time to evacuate to reach the standard reaction chamber pressure is quite time consuming. In the United States, when the anti-fuse layer is turned on, the anti-fuse layer is turned on to cause its bipolar current, which is non-volatile. The anti-dazzle wire layer is also based on the storage of the electrode and the negative electrode. The type-memory patent is applied for, and its fuse layer is also covered by anti-fuse material because of its external appearance. However, the components are all under polycrystalline silicon.

No. 0 9/5 6 0 6 2 6 reveals a kind of low leakage current where a reverse solution is placed between the positive and negative diodes ^ When intact 'the positive and negative electrodes are disconnected from each other, when a is broken, The positive and negative electrodes of a small area form a diode for this purpose, and because of the small area of the melting area, it also has a relatively small >: Patent Patent 6 5 2 5 9 5 3 reveals a three-dimensional, programmable memory cell, which is composed of a positive and negative element of a self-aligned columnar polar body, and a white cell formed by the columnar body. Transport; | The original β layer is intact and damaged or not, forming a circuit, and the order is determined by the conventional method described above, using a doped polycrystalline stone on the formation of a diode, compared to the cited case The formation of the metal silicide layer only needs to increase the overall resistance of the system and the silicide layer, and thereby increase the overdrive driving current.

1241593 V. Description of the invention (4) There are several aspects of the invention. In order to solve the above problems, one object of the present invention is the structure and manufacturing method of a stiff, interspecialized anti-refined memory element, which: Fewer polycrystalline silicon deposition steps are used to simplify the fabrication of metal silicides, reduce process time, and reduce manufacturing costs. Another object of the present invention is to provide an antifuse memory device and a manufacturing method thereof. By reducing the polycrystalline silicon layer, the total resistance of the crystalline silicon and silicide layer can be reduced, and thereby Increase the drive current of the anti-fuse type memory element. According to the above-mentioned object, the present invention provides a simplified anti-fuse-type memory: 2 structure and manufacturing method, including the following steps: first & providing-forming a f layer on the substrate. Thereafter, the% -Si layer is formed on the compound and the Ϊ 5 ° metametallic layer reacts with a part of the Si layer to form a -metal oxide layer to form a second anti-silicon layer as the first-type conductive layer. . Next, φ is spread on the ^ -type conductive layer. Graphical first guide

The electrical layer, the metal silicide layer, and the anti-IV-conducting lightning are identified as the μ long-term filament layer to form a character line and form a first V-electric layer on the anti-fuse layer. . Finally, the second type conductive layer is patterned with a silicide structure, which includes a polycrystalline electrical layer of an anti-fuse memory element on the metal silicide layer, a metal silicide layer, and a first type. ; And a second-type conductive reed anti-fuse layer is on the first-type conductive structure, because it reduces the ^ j ^ fuse layer compared with the conventional technology. According to the invention, the polycrystalline spar and the polycrystalline spar

1241593

It can increase the overall resistance of the driver layer of the anti-dazzle type memory device and lower the current. In order to make the above and other objects of the present invention obvious and comprehensible in conjunction with the accompanying drawings, a preferred embodiment is described below in detail as follows: Embodiments Examples-Ming ^ f2A to 2D diagrams showing process cross-sections of a simplified antifuse type = ... embodiment of the present invention. In this embodiment L :, ': The word "inverse" refers to the components formed on the semiconductor wafer. First, as shown in Figure 2A, a semiconductor substrate 200 is provided, and the metal wires and the dielectric layer between the wires are provided. Already formed on the semiconductor substrate 200, its Mons wire can be copper metal or tungsten metal, and the dielectric layer between the wires can be a non-titanium shixi glass' tetraethoxy shixi sintered as shixi Source of silicon dioxide or hafnium other dielectric materials. Thereafter, a titanium nitride layer 20 and a subsequent metal layer 2 1 2 ′ titanium can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Titanium The metal system is deposited by physical vapor deposition (PVD). The thickness of titanium nitride is 25 ~ 250 angstroms. The 4 series is used as the bonding layer of the titanium silicon compound and the underlying metal wires. The thickness of the titanium metal is 2 0 0 ~ 80 0 Angstroms, which provides the source for the formation of titanium silicon compounds after the formation of 0. Then, an undoped polycrystalline silicon layer or an amorphous silicon layer is deposited as

0503-9867T ^ rF (Nl). TSMC2002-1345; wayne .ptd Page 9 1241593 V. Description of the invention (6) '_ " ~-The polycrystalline silicon layer 2 2 0 should be on the titanium metal layer 2 1 2 and its system A chemical vapor deposition (CVD) method was used at a reaction temperature of 45 °. c ~ 800. c. The reaction pressure is deposited under the conditions of 0 ITorr to 10 Torr, and the thickness of the reactive polycrystalline silicon layer 22 is 200 to 1 500 Angstroms, which is used as the titanium metal layer 2 and a part thereof. The titanium nitride layer 210 reacts to form a subsequent titanium silicon compound layer. Next, a first-type conductive layer 23 is deposited on the reactive polycrystalline silicon layer, which can be a polycrystalline silicon layer doped with p +, or formed using a chemical vapor deposition (CVD) method. However, the polycrystalline silicon layer is used as a conductive and conductive layer. To form a diode, it needs to have a lower resistivity. Therefore, its doping can be reduced by doping. The doped impurities are shed or other trivalent elements. In addition, after its polycrystalline fragmented chemical vapor deposition (CVD) reaction, thorium is introduced into the impurity by a high-temperature diffusion method, or ion implantation is performed after the deposition to implant the impurity in an ionic form. Into the polycrystalline silicon, or during the deposition reaction of the polycrystalline silicon, impurities are simultaneously infiltrated into the polycrystalline silicon, and the thickness of the first-type conductive layer 230 formed therein is 300 to 2000 angstroms. As shown in FIG. 2B, the post-production process is a thermal process, which can be a rapid heating process or a furnace control process, at a temperature of 400. c ~ 12〇〇. c. Permeate the gas so that the previously formed titanium / titanium nitride layer 2 and 0 react with the polycrystalline silicon wafer 220 to form a titanium metal silicide layer 24. The titanium gold layer 240 formed thereon has a low resistance. And thermal stability. Thereafter, as shown in the figure, a thermal process is performed, which may be a fast heating process or a furnace control process, at a temperature of 400. c ~ 12〇〇. c. Oxygen isolation is used to generate a dioxide layer on the surface of the first type conductive layer. The second silicon layer has a thickness of 5200 Angstroms.

1241593 V. Description of the invention (7) The anti-fuse layer 2 3 5, so the control of the quality and uniformity of the anti-fuse layer 2 3 5 is quite important. Next, the previously formed anti-fuse layer 235, the titanium silicon compound layer = 0 > and the first type conductive layer μ 0 are formed to form word lines, which include conventional techniques such as lithography and surname engraving, which will not be described in detail here. After the wires are formed, a dielectric material is filled between the wires, which can be silicon dioxide formed by a high-density plasma (HDP) chemical vapor deposition method. The ion concentration in the plasma is higher than that of ordinary electricity = ' The rolling phase / child product method is thickened, so the method of deposition / money engraving / deposition can be used. The better trench filling ability can fill the gap after forming the wire. Second, chemical mechanical polishing (CMP) is used to remove the excess dielectric layer and planarize it. The fuse m 'is shown in the figure' and the second type conductive layer 250 is deposited in the opposite direction. ≪: 曰 目 &##; 乂 is a polycrystalline silicon layer doped with 1 ^, which is applied—the reaction pressure is 0 1Torr 1n τ Under the conditions of anti-It C ~ 800.c, • 1 〇rr ~ 1 〇τ 〇rr, Shen Ji, Gan Gan life reached 1000 ~ 6500 Angstroms. The second criminal road + gy under the product of one product t t ¥ The electrical layer is used for conduction and: 口:? Yu Yi 4, the formation of the first type of conductive layer-H seeks the formation of 夂 and 刖 f ^ a ^ polar body effect 'so it also needs a $ 4's thunder The P-day method is also available *: Shellfish is arsenic or other pentavalent elements. The method of implantation of the sub-implantation: required; the diffusion method brings impurities into the 'or the first electricity formed before the ionization and the The type of layer 250 of the polycrystalline silicon layer to be deposited can also be reversed, in other words, the type at this step. Κρ + type, and the previously deposited polycrystalline silicon is N + and then the 'definition first'; #, # —V electrical layer 2 5 0 to form a bit line, which includes 1241593 V. Description of the invention (8) Photomask 'development and etching. After forming the wires, fill the dielectric material between the wires' It is also a high density The silicon dioxide formed by the chemical vapor deposition method of the HDP is filled into the gap after the wires are formed. Thereafter, the excess dielectric layer is removed by chemical mechanical polishing (CMP) and planarized. Please refer to FIG. 4 for reference. It is a perspective view showing the metal silicide process of the anti-dazzling silk type slow-body element polysilicon of the present invention. A titanium silicide layer 240 is formed on the semiconductor substrate 200. The first type conductive layer 23 is used as a word line (WL) and the second type conductive layer 250 is used as a bit 9 line (BL). The titanium silicide layer 240 and the semiconductor substrate 2 There is a titanium carbide layer 210 between 〇 for adhesion, and an anti-dazzling silk layer 2 3 5 between the first type conductive layer 23 and the second type conductive layer 250. Features and advantages of the present invention Features In the process of the anti-fuse memory element, a metal layer is deposited on the metal wire, and then a reaction layer is deposited, and the metal layer is reacted upward to form a metal silicide by the heating process, which can reduce ^ Polysilicon deposition steps to simplify metal silicide formation The process can reduce the process time and reduce the manufacturing cost. Χ The present invention can also reduce the overall resistance of polycrystalline sand and silicide layer by reducing a polycrystalline silicon layer, and thereby increase the anti-fiber memory device, ❶ Driving current.% Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit or limit the present invention. Anyone skilled in this art will not depart from the essence of the present invention.

1241593

0503-9867TWF (Nl); TSMC2002-1345; wayne.ptd Page 13 1241593 Schematic description

Figures 1A to 1D show cross-sectional schematic diagrams of the polycrystalline stone polysilicon and metal silicide manufacturing processes of conventional anti-solvent silk memory elements. Figures 2A to 2D show schematic cross-sectional views of the polysilicon and metal silicide process of the anti-fuse type memory device according to the embodiment of the present invention. FIG. 3 is a perspective view showing a metal silicide process of a polycrystalline stone of a conventional anti-dissolved silk memory element. Fig. 4 is a perspective view showing a metal silicide process for the antifuse memory element polysilicon of the present invention. Explanation of symbols Conventional technology 100 ~ semiconductor substrate; 111 ~ reactive polycrystalline silicon layer; 120 ~ titanium nitride layer; 135 ~ first type conductive layer; 140 ~ second type conductive layer. The technology of the present invention is 200 to semiconductor substrate; 212, titanium metal layer; 230 to first type conductive layer; 2 3 5 to antifuse layer; 110 to bottom polycrystalline second layer; 11 9 to titanium metal layer; 1 3 0 ~ Titanium silicon compound layer; 136 ~ antifuse layer; 2 1 0 ~ titanium nitride layer; 2 2 0 ~ reactive polycrystalline silicon layer; 2 0 0 ~ titanium metal silicide layer 250 ~ second type conductive layer.

0503-9867TWF (Nl) TSMC2002-1345; wayne.ptd p. 14

Claims (1)

1241593 VI. Patent application method for manufacturing anti-fuse memory device, including the following steps: Provide ~ form a * form a form-siliconize the metal-form a pattern-form word lines-form a pattern 2 · Rushen's manufacturing method 3 · Rushen's manufacturing method 4 · Rushen's manufacturing method Nitride 5 · Rushen's manufacturing method substrate; Adhesive layer metal layer Silicon layer belongs to the physical layer and the physical layer and antifuse§ The first and second types are patented, of which the patents are claimed, of which the patents are patented, among which the patents are more mixed. If patent-type ions are doped on the substrate; on the adhesive layer; the metal On the layer; part of the adhesive layer reacts with part of the silicon layer to form an unreacted silicon layer system as a first type conductive layer; layer on the first type conductive layer; type conductive layer, metal silicide layer, The fuse layer is a conductive layer on the antifuse layer; and a conductive layer is formed to form a bit line. The anti-fuse type memory element described in item 1 of the scope The substrate is a semiconductor substrate. The anti-fuse type memory element described in item 1 of 巳 巳 巳 is composed of Qin 'diamond or recording. : ^: The anti-fuse type memory element described in item 1 is composed of titanium nitride, cobalt nitride, or hum: The anti-fuse type memory element described in the first two pages of silicon I is in order — Un-doped polycrystalline silicon and a stack of first-day sun and evening eves constitute the anti-fuse type memory element described in item 1 0503-9867TWF (Nl): TSMC2002-1345; wayne.ptd Page 15 1241593 6. Manufacturing method in the scope of patent application, wherein the formation of the metal silicide layer is a metal layer and an undoped polycrystalline silicon layer of the silicon layer The reaction formed. 7. The method of manufacturing an anti-fuse type memory element according to item 1 of the scope of the patent application, wherein the first-type conductive layer is a P-type and the second-type conductive layer is an N-type. 8. The manufacturing method of the anti-fuse type memory element according to item 1 of the scope of the patent application, wherein the first type conductive layer is an N type and the second type conductive layer is a P type. 9. The method for manufacturing an anti-fuse type memory device according to item 1 of the scope of the patent application, wherein the metal silicide layer is composed of a titanium silicon compound, a cobalt silicide compound, or a nickel compound. 10. The method for manufacturing an anti-fuse type memory element according to item 1 of the scope of the patent application, wherein the method of forming an anti-fuse layer is to heat the first-type conductive layer. 1 1. The method for manufacturing an anti-fuse type memory device according to item 1 of the scope of the patent application, wherein the anti-fuse layer is silicon dioxide or silicon nitride. 1 2. A structure of an anti-fuse type memory element, comprising: a metal oxide layer; a first type conductive layer on the metal silicide layer; an anti-fuse layer on the first type conductive Layer; and, a second type conductive layer on the antifuse layer. 1 3. The structure of the anti-fuse type memory element according to item 12 of the scope of the patent application, wherein the first type conductive layer is a P type and the second type conductive layer is N 〇 0503-9867TWF (Nl); TSMC2002-1345; wayne.ptd page 16 1241593 VI. Scope of patent application / 1 4 · The structure of the anti-fuse type memory as described in Item 12 of the scope of patent application = item, where the first type conductive layer is N type and the second type conductive layer is P type. 15 · According to the structure of the anti-dazzle silk-type self-thinking body element described in item 12 of the scope of patent application, wherein the metal silicide layer is a titanium silicon compound, a starting stone compound, or a nickel compound Composed of. 16 · The structure of the anti-fuse memory device described in item 12 of the patent application scope, wherein the anti-fuse layer is silicon dioxide or silicon nitride. 1 7 · —The structure of an anti-hyun silk memory element, which includes: A first wire; an adhesive layer on the first wire; a metal silicide layer on the adhesive layer; a first type conductive layer on the first wire; an anti-refining layer on the first type conductive Layer; and a second type conductive layer is located under a second conductive line, the first conductive line and the second conductive line are perpendicular to each other, and the anti-wire layer between the first conductive layer and the second conductive layer is a moment Region, and the first type conductive layer and the second type conductive layer will form a diode only when the anti-glare wire layer is broken. 1 8 The structure of a one-piece anti-fuse memory as described in item 7 of the scope of the patent application, wherein the first and second wires are made of tungsten, ~ & 70 copper. 19, or 19 · The structure of the anti-fuse type wind-remembering device as described in item 7 of the patent application scope, wherein the metal silicide layer is a titanium silicon compound, the surface is also a element, or is a recording stone. Evening compounds. Xihuahe II 0503-9867TWF (Nl): TSMC2002-1345; wayne.ptd Page 17 1241593 6. Application for patent scope 20 • The structure of the anti-fuse type memory element described in item 17 of the scope of patent application, where the first The first-type conductive layer and the second-type conductive layer are P-type or N-type. 2 1 · The structure of the anti-fuse type memory element as described in item 17 of the scope of patent application, wherein the first type conductive layer and the second type conductive layer are different from each other in shape. 2 2 · The structure of the anti-fuse type memory element as described in item 17 of the scope of the patent application, wherein the anti-solvent layer is a dioxide or a nitride. 2 3 · The structure of the anti-fuse type memory device according to item 7 of the patent application scope, wherein the adhesive layer is a nitride of titanium, a nitride of cobalt, or a nitride of nickel. ⑩ 2 4 · —A method for manufacturing an anti-fuse memory device, including the following steps: providing a substrate; forming a metal layer on the substrate; forming a silicon layer on the metal layer; and making the metal layer and a part The stone layer reacts to form a metal silicide layer and the unreacted silicon layer is used as the first variable conductive layer; forming an antifuse layer on the first split conductive layer; and patterning the first type The conductive layer, metal silicide layer, and anti-fuse layer form word lines with _. 2 5 · The method for manufacturing an anti-hyun silk type memory device as described in item 24 of the patent application, wherein the substrate is two semiconductor substrates. 2 6 · Anti-fuse type memory cell as described in item 24 of patent application 0503-9867TWF (Nl): TSMC2002-1345; wayne.ptd Page 18 1241593 VI. Scope of patent application-Large-scale manufacturing of 27 pieces, where the metal layer is made of thorium, cobalt, or nickel. The anti-dazzle silk memory element layer described in item 24 of the patent application scope. Method 'wherein the metal layer and the substrate still include the manufacture of an adhesive member ^ The anti-dazzle silk-type memory cell or nickel as described in item 27 of the patent application scope, wherein the adhesive layer is nitrogen Compound, starting nitride rat compound. The first method of anti-fuse type memory cell described in item 24 of the patent application of 29 items, wherein the silicon layer is an undoped polycrystalline silicon and a 30-doped polycrystalline silicon in order. Stacked composition. The silicon layer of the anti-fuse memory cell described in item 24 of the scope of patent application: the silicon layer: method, wherein the metal silicide layer is formed by a metal layer and an undoped polycrystalline silicon layer. form. "A piece &" ^ The anti-fuse type recording method described in item 24 of the scope of application for patents_ The manufacturing method, wherein the metal stone material layer is a titanium stone material: an ordinary compound, or a nickel stone Composed of compounds. The anti-fuse method of fabricating as described in item 24 of the scope of patent application, wherein the method of forming an anti-fuse layer is an ordinary conductive layer. To heat the first 33. The method of manufacturing an anti-fuse device as described in item 24 of the scope of the patent application, wherein the anti-fuse layer is titanium dioxide silicon nitride. 0503-9867TWF (Nl): TSMC2002-1345; wayne.ptd Page 19