I2404Q1 87twf.d〇c/c 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝基板，且特別是 種封裝單元外圍具有擬線路，用以對封裝單元=一關於一 試的封裝基板。 I 仃電性測 【先前技術】 暴板型承載器（substrate type carrier)由於具古 =、組裝緊凑以及性能良好等優點，是半導體製程= ‘人裝70件。一般而言，基板型承載器可分為堆疊 積層式（b痛，）等兩大類型之 其主要是由多個圖案化之線路層及多声 =曰登合所構成，且任兩線路層係藉由形成於介二 %通孔相互電性連接’以達成訊號傳遞的目的。 在高度情報化社㈣今日，為符合電抒 功能化、積集化及小型輕量化等多方_要求I2404Q1 87twf.d〇c / c IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a package substrate, and in particular, a package unit has a pseudo-line on the periphery for packaging unit = one for one test Package substrate. I Electrical performance test [Prior technology] Due to its advantages such as compact structure, compact assembly, and good performance, the substrate type carrier is a semiconductor process = ‘70 pieces of equipment. Generally speaking, the substrate type carrier can be divided into two types: stacked and laminated (b pain,), etc.It is mainly composed of multiple patterned circuit layers and multi-sound = Yue Denghe, and any two circuit layers The purpose is to achieve the purpose of signal transmission through the electrical connection formed between the two percent vias. In today's high-information agency, today, in order to meet various requirements such as functionalization, accumulation, and miniaturization of electronics,
縮小封型化及高密度化發展。為了 Chip Fi ^ ^功能性，諸如覆晶（FliP ^：«T/：；~r：(Ba,IGridA^ 騎術皆廣為產業界=:^161>〜’挪）等封 發展i 基板之線路設計也隨著3功能之 對於整趙ΐ裝因此封裝基㈣電縣現 封震基板上，部分之特徵ϋ甚矩。舉例而5，在尚逾、度 付做線路的阻抗往往會對整體線路之 I2404QI 8 7twf. doc/c 電性表現造成關鍵性的影響，因此線路間需要藉 (impedance etching) 傳遞的品質。然而，由於封裝基板之線路的密萝 ^ =在基板製程中或縣前後，往往無法對“線路$ 性進仃準確且快速的量測。目前常見的方法通常壯： 凡外圍設置較大之接墊，並藉由打線的方式將料= ^則接點電性連接至外圍之接塾，以透過接墊間接= 基板内之特徵線路進行阻抗的量測。 丁衣 封丄而，：知之阻抗量測的方式必須犧牲進行測試的 h早兀’因此會在無形中造成製作成本上的 進行—道打線製程，使制試日㈣加長。此外 产=以f連接之導線皆會影響所測得之阻抗值的準確 度。因此，如何提供—種快速、 測機制，實為提昇伊Μ ί衣基板的阻抗置 【發明内容】 讀封倾術之品質的重要關鍵。 J1,本么明的目的就是在提供一種封裝基板條， 用以對基板單元進行準杳 ” 行準f是在提供一種封裝基板，其適於進 線路阻抗測試’以提高封裝產品之品質與 有提出—料裝基板條，其具 徵線路以及—擬驗。:基ί條包括多個基板單元、-特 。土板單元係與基板邊框一體成型， I2404QL 8 7twf. doc/c mr係配置於基板單元之其一内，且擬線路係配置 ^'反邊㈣’其中擬線路储應於魏線路，以藉由擬 線路模擬特徵線路之電性。 依照本發明之—較佳實 中擬線路例如是與特徵線路同時形成。 ㈣之—較佳實施顺述之魏基板條，其 中擬線路例如與特徵線路具有相同之截面。 明之—較佳實施例所述之封裝基板條，其 7夕a、、°構，且擬線路與特徵線路例如是位於封裝 基板條之同一層中。 依照本發明之一較佳實施例所述之 中擬線路與特徵線路例如是位於封裝基板條之^ ㈣m發明之—較佳實施綱述之縣基板條，其 有多個表層接點。此外’封裝基板條例如 :且，罩層暴μ表層接點。另外’縣基板條例如ί υ括-抗德層，其係配置絲層接點 化層例如是鎳/金層。 田几乳 川明之一較佳實施例所述之封裝基板條，其 ==縫i這些狹長縫係將基板單元與基板 刀二而彳k板單元僅^部份連結於基板邊框。 中封n本r明之一較佳實施例所述之封農基板條，其 中封衣基板條例如是塑膠基板。 依照本發明之-較佳實施例所述之封裝基板條，其 I2404Q1 1 87twf. do。/。 例如是一球格陣列基板。 非封=明更提出一種封裝基板，其具有m盥 非封衣區。此封裝基板包衣&與- 徵線路係配置於封擬線路，其中 褒區分2，而使得封裝封 依照本發明之一較佳實施例所述之封% 擬線路與紐線關如是同時形成。 土才反/、中 依照本發明之一較佳實施例所述之封 擬線路與特徵線路例如具有相同之截面。 /、 所述之封裝基板，其例 如疋-夕層結構，且擬鱗與紐線路係錄封裝基板之 同一層中。 土 依照本發明之-較佳實_所述之封裝基板，其中 擬線路與特徵線路例如是位於封裴基板之表層。/、 依照本發明之一較佳實施例所述之封裝基板，其中 擬線路例如具有多個表層接點。此外，封裝基板例如更包 括-辑罩層，其減蓋於封親與非封裝區之表面，且焊 罩層暴露出表層接點。另外，封裝基板例如更包括一抗氧 化層，且此抗氧化層係配置於表層接點之表面，其中抗氧 化層例如是鎳/金層。 I2404Q1, 87twf.d〇c/c 依照本發明之一較佳實施例所述之封裝基 如是塑膠基板。 其例 依照本發明之一較佳實施例所述之封裝基板， 如是-球格_基板。 奴其例 基=上述’本發明之封裝基板條或封裝基板係 板早兀（或封裝基板之封裝區）以外的基板邊框（或 ς 封裝區)上形成擬線路’其係對應於基板單元的ί ::，因此只需對基板邊框上之擬線路進行檢測，便可 板擬基板單it内之特徵線路的電性。藉由本發明之 =與封裝基板可達醇確且快速·基板單元之線ςς 几的目的，進而有效控制產品品質與製程良率。 為讓本發明之上述和其他目的、特徵和優點能更明 ”、、頁易It下文特舉較佳實施例，並配合所附圖式，作 說明如下。 十、、、田 【實施方式】 明芩考圖1，其繪示本發明之較佳實施例之一種封妒 基板條的示意圖。如圖！所示，封裝基板條1〇〇例如是—、 多層板’其例如包括多個基板單元1G2以及圍繞基板單元 1—02配置的-基板邊框1()4。其中，每—基板料ι〇2係 定義為封裝區，其例如可經由封裝製程與一晶片（未繪示) 接σ、而形成一封装結構(未繪示）。相對地，基板邊框⑺4 係定義為非封裝區’且基板單元1()2與基板邊框剛之間 例如具有多個狹長縫1〇6，以將基板單元1〇2與基板邊框 1〇4刀開，而使得基板單元1〇2财部份連結於基板邊框 I2404QL 87twf.doc/c ^04 S封裝製程完成後，可進行—分離程序，使得基板 =102與基板邊框1〇4分離，而形成多個相互獨立的封Reduced sealing and high-density development. For Chip Fi ^ ^ functionality, such as flip-chip (FliP ^: «T / :; ~ r: (Ba, IGridA ^ riding are widely used in the industry =: ^ 161 > ~ ')) The circuit design also follows the 3 functions of the entire package. Therefore, some of the features on the current sealed seismic substrate of the package base are extremely inaccurate. For example, 5, the impedance of the circuit that is over and over is often a problem for the whole. I2404QI 8 7twf. Doc / c The electrical performance of the circuit has a critical impact, so the quality of transmission by impedance etching is needed between the circuits. However, because of the multitude of the circuit of the package substrate ^ = in the substrate manufacturing process or around the county It is often impossible to make accurate and fast measurement of the "line" property. At present, common methods are generally strong: Where large pads are set on the periphery, and the material is connected by means of a wire = ^, the contact is electrically connected to The connection of the periphery is to measure the impedance through the pad indirectly = the characteristic line in the substrate. Ding Yifeng: The method of measuring the impedance must be sacrificed. Therefore, it will be invisible. Production cost progress-wire-to-line process The length of the sundial is longer. In addition, the wires connected with f will affect the accuracy of the measured impedance value. Therefore, how to provide a fast and measuring mechanism to improve the impedance setting of the substrate 】 The key to the quality of the reading package. J1, the purpose of this Meming is to provide a package substrate strip, used to standardize the substrate unit. "Line standard f is to provide a package substrate, which is suitable for wiring Impedance test 'in order to improve the quality of packaged products and put forward-material board strips, which have characteristic lines and-test .: The base strip includes multiple substrate units,-special. The soil plate unit is integrated with the substrate frame, I2404QL 8 7twf. Doc / c mr is arranged in one of the base units, and the pseudo-line is arranged ^ 'inside edge', where the pseudo-line is stored in the Wei line to simulate the electrical characteristics of the characteristic line by the pseudo-line. According to the present invention, the preferred circuit is formed at the same time as the characteristic circuit, for example. ㈣ — The preferred embodiment of the Wei substrate strip is described, in which the proposed circuit has the same cross-section as the characteristic circuit, for example. In the package substrate strip described in the example, the structure of the circuit board and the characteristic circuit are, for example, located in the same layer of the package substrate strip. According to a preferred embodiment of the present invention, the proposed circuit and the characteristic circuit are in the same layer. The characteristic circuit is, for example, the ^ ㈣m invention of the package substrate strip—the county substrate strip of the preferred implementation outline, which has multiple surface layer contacts. In addition, the package substrate strip is, for example, and the cover layer exposes μ surface layer contacts. The county board strip is, for example, a layer of anti-German, which is configured with a silk layer contact layer, such as a nickel / gold layer. The package substrate strip described by one of the preferred embodiments of Takiru Rukawa, which == slit These slits connect the substrate unit and the substrate knife, and the 板 k plate unit is only partially connected to the substrate frame. The sealing substrate strip according to a preferred embodiment of the present invention, wherein the sealing substrate strip is, for example, a plastic substrate. According to the package substrate strip of the preferred embodiment of the present invention, I2404Q1 1 87twf. Do. /. For example, it is a ball grid array substrate. Non-encapsulated = Ming Gen proposes a package substrate having an m-encapsulated area. This package substrate coating & and -signal circuit is arranged on the sealed circuit, of which the division is 2 so that the package seal is formed according to the seal of a preferred embodiment of the present invention. . Tucai /, Zhong The sealed circuit and the characteristic circuit according to a preferred embodiment of the present invention have, for example, the same cross section. The package substrate mentioned above has a structure of, for example, a 疋 -Xi layer structure, and the pseudo scale and the button line are recorded in the same layer of the package substrate. The package substrate according to the preferred embodiment of the present invention, wherein the pseudo wiring and the characteristic wiring are, for example, located on the surface layer of the sealing substrate. /. The package substrate according to a preferred embodiment of the present invention, wherein the proposed circuit has, for example, a plurality of surface layer contacts. In addition, the package substrate further includes, for example, a mask layer, which is covered on the surface of the sealing and non-packaged areas, and the solder mask layer exposes surface layer contacts. In addition, the package substrate further includes, for example, an anti-oxidation layer, and the anti-oxidation layer is disposed on the surface of the surface contact, wherein the anti-oxidation layer is, for example, a nickel / gold layer. I2404Q1, 87twf.doc / c The packaging base according to a preferred embodiment of the present invention is a plastic substrate. Example A package substrate according to a preferred embodiment of the present invention is a ball grid substrate. No matter the base = the above-mentioned 'the package circuit strip or package substrate of the present invention is formed on a substrate frame (or package area) other than the early board (or package area of the package substrate) of a pseudo-circuit', which corresponds to the substrate unit ί ::, so you only need to test the pseudo-circuits on the substrate frame to board the electrical characteristics of the characteristic circuits in the substrate single it. With the purpose of the present invention, it is possible to achieve an accurate and fast connection with the package substrate, and thus effectively control the product quality and the process yield. In order to make the above and other objects, features, and advantages of the present invention clearer, page and it will be described below with preferred embodiments, and in conjunction with the accompanying drawings, the description is as follows. Fig. 1 shows a schematic diagram of a sealing substrate strip according to a preferred embodiment of the present invention. As shown in the figure, the packaging substrate strip 100 is, for example, a multilayer board, which includes, for example, a plurality of substrates. The unit 1G2 and the substrate frame 1 () 4 arranged around the substrate unit 1-02. Among them, each substrate material 2 is defined as a packaging area, which can be connected to a chip (not shown) through a packaging process, for example. To form a packaging structure (not shown). In contrast, the substrate frame ⑺4 is defined as an unencapsulated area 'and the substrate unit 1 () 2 and the substrate frame have, for example, a plurality of slits 106 between the substrate frame and the substrate. The unit 102 and the substrate frame 104 are cut apart, so that the substrate unit 102 is connected to the substrate frame I2404QL 87twf.doc / c ^ 04 After the S packaging process is completed, a separation process can be performed so that the substrate = 102 is separated from the substrate frame 104, and forms a plurality of mutually independent Seal
SiL树T在二實施例中’封裝基板條100例如是 ，土 而基板單元102例如是一球格陣列基板。 =再參考圖i，本發明係在封裝基 框卿卩非封裝區)上配置—擬線路12G，其中擬線 列如係與基板單元1G2同時形成，並對應於In the second embodiment, the SiL tree T is a package substrate strip 100, for example, and the substrate unit 102 is, for example, a ball grid array substrate. = Refer to Figure i again, the present invention is configured on the package base frame (unpackaged area)-pseudo-line 12G, where the pseudo-line is formed at the same time as the substrate unit 1G2, and corresponds to
102(即封裝區）内戶斤欲 恭旦 ’心；土反早7G 圖2A)，且;^,电里測的特徵線路（繪示於 口^^，且擬線路12〇與特徵 其比如有相對應的線寬、線長、相 的佈線形狀。如此一來，擬線路 基板早X 102内之特徵線路（緣示於將了丰確拉擬 即只須對擬線路120進行量測，便Γ )的電性’亦 任何位置之特徵線路（綠示於圖仔=板單元102内 發明之擬線路120的型態會對。當然’本 2Α)而有所不同，舉例而言，壯“泉路（緣示於圖 為-多層結構時，擬線路120二：：板條100例如係 例如可位於封裝基板條100之^屌二、〃路（繪示於圖2Α) 内的同一層内。 & 9或位於封裝基板條100 為詳細說明本發明之特徵， 態之擬線路，並搭配其欲量 。寺舉出多種不同型 行說明。 、基板早元内的特徵線路進 請同時參考圖2Α與2Β，其中題一 線的剖面圖，而圖 —示為圖丨：為圖1之“， Β線的剖面圖。在 〇c/c I24_Utwfd 序C ’封裝基板條100例如是—四芦 !134、1=二:ΤΓ42、-第二導電 介電層U6以及—第四導電層138;:電層136、一第三 132與第四導 構成，且第一導電層 與154。¥“138之表_口分別配置有—鮮罩 士圖2A所示，第一導電声 係分別構成基板單元102之一曰第=第四導電層⑶ 及—第四圖案化線路_，且第%圖牵案路仙、以 具有欲進行電性量測的-特徵線路^化f路咖例如 層⑼及第-道千故 33°此外’第二導電 層。 电層136例如分別為一接地層與-電源 如圖2B所示，於—實施例中， 成上述之第== 形成-擬===圖。的第—導電層132 兩端，以作πΓ 係減出擬線路120之 發明之特行’㈣々接點122與—第二接點124。依照本 -參= 匕 與第一圖案化線路132“系由同 如且1 且擬線路120與第一圖案化線路132a例 ^相^目對應的線寬、線長以及佈線形狀，換言之，即罝 ^目问之截面。因此擬線路12〇與特徵線路133可具有極 盥物理特性。如此一來’便可直接透過第-接點122 特徵線路則阻抗值。值得一提的是，為;; I2404QJ,87twf doc/c 122與第二接點124之過度氧化，第—接點122與第二接 點124上例如可形成有一抗氧化層16〇，其例如是一錄/ 金層。田然’於本發明之其他實施例中，封裝基板條更例 如可為-多層結構，其中擬線路與特徵線路例如是位於封 裝基板條之同-線路助，且擬線路可藉由位於封裝基板 絲層之接軸餘外界，以供作電錄測之用。 除了上述位於基板表層的擬線路之外，本發明之擬 ^更^^位於封裝幻反條内之任—層中，用以模擬基 板早兀内之同一層線路的電性。 請參考圖3A與3B’其中圖3a給 城基板之騎魏的剖關，而圖_林發明之 -種封裝基板之擬線路的剖面圖。如圖3Α幻 =裝ίΓ〇ΓΗ°是一六層板，且其例如是-球格陣列 ；ΪΐΓ3〇2 Γϊ! 310 300 一段:路且 路310的電性，係於封二了迪此封裝區内之特徵線 ^ 320，^ 且擬。例如具有_=中， 之内層，因此题====糾裝基板删 孔330，使得擬線路32〇藉由導通孔=別形成一導通 基板300表層的第—9 連接至位於封裝 過第-接點30技第接Γ Μ二接點娜。其中，透 ”弟―接點306可對擬線路32〇進行阻抗 40丨1 l87tWf.d〇C/c =上 與第二接點3'06，且^層340 ’其係暴露出第一接點304 例如同樣可形成有^接點3〇4與第二接點306之表面 第—接點304斑第化層3〇8(如鎳/金層），以避免 值得注意的t^3!6過度氧化。 例之用，本發明之油^㈣崎不之擬線路僅為舉 線路的不同而有所變化。=型態f可隨基板單元内之特徵 裝基板之非封褒區的=列而言’擬線路例如可位於封 之封=任意位置二：性用以模擬封裝基板 板之非封裝區條的基板邊框(或封裝基 單元(或封裝基板之封擬線路可對應與基板 徵線路）同時形成 Y0内之任思部分的線路結構（特 線路。並且，由於擬線路i 來形成此擬 (或封裳基板之非封穿⑸:配置於封叙基板條之基板邊框 基板邊框(或封Μ x )内，因此可視量測需求充分利用 在基板單可佈線空間，例如可 態的多個擬線路區)之周圍同時形成不同型 内不=之特徵線路的電=基板單元(或封裝基板之封裝區） 優點：r上所述’本發明之封裝基板至少具有下列特徵與 裝基 )使付封裳基板條(或封袭基板)上之 I2404Q1 87tyyf.d〇c/c 本。 有助於降低測試成 區)内路路反單元(或封裝基板之封裝 進而有效㈣〗產品品倾製=特料路之阻抗值， 内之部分線路二:應 擬線路，因此可節省製作成本與製之製程來形成 之擬S 條内上可同時配置多個不同類型 此可提供爭夕if反早7"内之不同線路結構的阻抗，因 此j徒供更多兀且具彈性之量測方式。 口 雖然本發明已以較佳實施例揭露如 以限定本發明’任何熟習此技藝者，在不脫離;;^非用 二範，内，當可作些許之更動與潤倚，因此本^明= 4軏圍當視後附之申請專利範圍所界定者為準。 /、 【圖式簡單說明】 〜圖1繪示為本發明之較佳實_之—_裝基板的 不思圖。 圖2A繪示為圖1之A_A，線的剖面圖。 圖2B繪示為圖1之B_B，線的剖面圖。 圖3A繪示為本發明之一種封裝基板之特徵線路的 面圖。 叫 圖3B繪示為本發明之一種封裝基板之擬線路的剖面 I2404Ql87t wf. doc/c 圖。 【主要元件符號說明】 100 :封裝基板條 102 :基板單元 104 :基板邊框 106 :狹長縫 120 :擬線路 122 :第一接點 124 :第二接點 132 :第一導電層 132a :第一圖案化線路 133 :特徵線路 134 :第二導電層 134a :第二圖案化線路 136 :第三導電層 136a :第三圖案化線路 138 :第四導電層 138a ··第四圖案化線路 142 :第一介電層 144 :第二介電層 146 :第三介電層 152、154 :銲罩層 160 ·•抗氧化層 300 :封裝基板 15 1240401 13 1 87twf.doc/c 302 :第三導電層 304 :第一接點 306 :第二接點 308 ··抗氧化層 310 :特徵線路 320 :擬線路 330 :導通孔 340 :銲罩層102 (that is, the package area), the households are willing to respectfully; the heart is anti-early 7G Figure 2A), and; ^, the characteristic line measured in the electric circuit (shown in the mouth ^^, and the proposed line 12〇 and characteristics such as Corresponding line width, line length, and phase wiring shape. In this way, the characteristic circuit in the pseudo-circuit board X 102 (shown in the case of Fengchao drawing, only the pseudo-line 120 needs to be measured, The electrical characteristics of Γ) are also characteristic lines of any position (green is shown in Figure T = the invented type of circuit 120 in the board unit 102. Of course, 'this 2A) is different, for example, Zhuang "Quanlu (the edge is shown in the figure-the multilayer structure, the proposed line 1202 :: the slat 100 can be located, for example, on the same layer within the package substrate strip 100, 〃2 (〃 shown in Figure 2A) &Amp; 9 or located on the package substrate strip 100. In order to explain the characteristics of the present invention in detail, the proposed circuit is matched with the desired amount. The temple gives a variety of different types of line descriptions. Please enter the characteristic circuits in the substrate early. Referring to FIGS. 2A and 2B, a cross-sectional view of the first line is shown, and the diagram—shown as FIG. 丨: is a cross-section of line “B” of FIG. In the oc / c I24_Utwfd sequence C ', the package substrate strip 100 is, for example,-four lu! 134, 1 = two: T42,-the second conductive dielectric layer U6, and-the fourth conductive layer 138 ;: the electrical layer 136, A third 132 and a fourth guide are formed, and the first conductive layer and 154 are arranged respectively. The table of 138 is arranged separately—as shown in FIG. 2A, the first conductive acoustic system constitutes one of the substrate units 102, respectively. The fourth = fourth conductive layer ⑶ and-the fourth patterned circuit _, and the% chart shows the case of Lu Xian, with a characteristic line to be measured electrically, such as layer ⑼ and the first-Dao Qian Therefore, 33 ° is also the second conductive layer. The electrical layer 136 is, for example, a ground layer and a power source, as shown in FIG. 2B. In the embodiment, the above-mentioned first == formation-pseudo === diagram. —The two ends of the conductive layer 132 are used as the πΓ system to reduce the special feature of the invention of the pseudo-line 120, the second contact point 122 and the second contact point 124. According to this reference, the first patterned line 132 The line width, line length, and wiring shape corresponding to the same example 1 and the pseudo-pattern 120 and the first patterned circuit 132a are equivalent, in other words, the cross-section of the mesh. The circuit 12 and the characteristic circuit 133 can have extremely physical characteristics. In this way, the impedance value of the characteristic circuit can be directly passed through the-contact 122. It is worth mentioning that; is; I2404QJ, 87twf doc / c 122 and Excessive oxidation of the second contact 124, for example, an anti-oxidation layer 16 can be formed on the first contact 122 and the second contact 124, which is, for example, a recording / gold layer. Tian Ran 'is described in other embodiments of the present invention. In the package substrate strip, for example, a multi-layer structure can be used, in which the pseudo-circuit and the characteristic circuit are, for example, located on the same side of the package substrate strip, and the pseudo-circuit can be provided by the connector outside the wire layer of the package substrate for external use. Used for recording test. In addition to the above-mentioned pseudo-lines on the substrate surface layer, the pseudo-lines of the present invention are located in any layer of the package magic stripe to simulate the electrical properties of the same layer of wires in the substrate. Please refer to FIGS. 3A and 3B ′, where FIG. 3a is a cross-section view of the riding substrate of the city substrate, and FIG. As shown in FIG. 3Α magic = equipment ΓΓ〇ΓΗ ° is a six-layer board, and it is, for example, a ball grid array; ΪΐΓ3〇2 Γϊ! 310 300 A section: The electrical properties of Lu Qilu 310 are based on the sealing of this package. The characteristic lines in the area ^ 320, ^ are intended. For example, it has an inner layer of _ = medium, so the problem ==== correction of the substrate deletion hole 330, so that the pseudo-line 32 ° is connected to the ninth through the via layer, which forms the surface layer of the conductive substrate 300. The 30th contact is connected to the second contact point. Among them, the "brother" contact 306 can perform impedance 40 on the pseudo-line 32o, 1 l87tWf.d0C / c = upper and second contact 3'06, and the layer 340 'exposes the first contact For example, the point 304 can also be formed with the first contact 304 and the second contact 306 on the surface of the second contact 304—a spot-forming layer 308 (such as a nickel / gold layer) to avoid noteworthy t ^ 3! 6 Excessive oxidation. For example, the oil of the present invention is not intended to change the circuit. For example, the type f can be changed in accordance with the characteristics of the substrate unit. In terms of the column, 'the pseudo-line can be located at, for example, the seal of the seal = any position 2: it is used to simulate the substrate frame of the non-encapsulation area of the package substrate board (or the package base unit (or the package circuit of the package substrate can correspond to the substrate characteristics). The circuit) simultaneously forms the circuit structure (special circuit) of the Rensi part in Y0. Moreover, this pseudo (or unsealed through substrate) is formed by the pseudo circuit i: the substrate frame (the substrate frame ( Or sealed M x), so according to the needs of measurement, make full use of the single wiring space on the substrate, such as multiple pseudo-circuit areas that can be in a state. ) Around the same time to form different types of characteristic lines of electric = substrate unit (or packaging area of the packaging substrate) advantages: the above mentioned 'the packaging substrate of the present invention has at least the following characteristics and mounting base) I2404Q1 87tyyf.d0c / c on the substrate strip (or hermetically sealed substrate). It helps to reduce the test area. The internal circuit reversal unit (or the packaging of the packaging substrate is effective). The impedance value of the road, part of the line 2: the line should be planned, so it can save production costs and the manufacturing process to form a quasi-S line. Multiple different types can be configured at the same time. This can provide contention if anti-early 7 " The impedance of different line structures, so J provides more flexible and flexible measurement methods. Although the present invention has been disclosed in a preferred embodiment, such as to limit the invention 'anyone skilled in this art, without leaving; ^ Instead of using the second model, some changes and reliance can be made, so this ^ Ming = 4 軏 Wai Dang will be determined by the scope of the attached patent application. /, [Simplified description of the drawing] ~ Figure 1 shows the better practice of the present invention Fig. 2A is a cross-sectional view taken along the line A_A of Fig. 1. Fig. 2B is a cross-sectional view taken along the line B_B of Fig. 1. Fig. 3A is a plan view of a characteristic circuit of a package substrate of the present invention. FIG. 3B shows a cross section I2404Ql87t wf. Doc / c of a pseudo-circuit of a package substrate of the present invention. [Description of main component symbols] 100: package substrate strip 102: substrate unit 104: substrate frame 106: slot 120: Virtual line 122: first contact 124: second contact 132: first conductive layer 132a: first patterned line 133: characteristic line 134: second conductive layer 134a: second patterned line 136: third conductive layer 136a: third patterned circuit 138: fourth conductive layer 138a · fourth patterned circuit 142: first dielectric layer 144: second dielectric layer 146: third dielectric layer 152, 154: solder mask layer 160 Antioxidant layer 300: package substrate 15 1240401 13 1 87twf.doc / c 302: third conductive layer 304: first contact 306: second contact 308 330: vias 340: solder mask layer
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