1239631 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種積體電容（integratedcapacitor)，尤指一種垂直式 積體電容結構，特別適合應用於類比/數位轉換器（A/D converter)或數位/ 類比轉換器（D/A converter)或切換電路(switch cap circuit)領域。 【先前技術】 直以來’電谷等被動元件已廣泛地被使用在無線電波 frequency，RF)及混合訊號(mixed-signal)電路中，應用在諸如過濾器 (filter)、共振電路(resonant circuit)、及導流電路(bypass)等電路設 計上。而為了降低生絲造成本，IC製造或設計#者莫不戮力朝提高積體 電路積集度之方向努力。 、 立睛參閱圖-及圖二，其中圖一為習知積體電容結構3〇〇之電極側視示 意圖，圖二為圖-中之習知積體電容結構3〇〇沿著切線聊—谓之叫面圖 Λ 316 ^ 326，^ 不，父又排列之相鄰兩電極指部（finger)係接以不同極性者。田-斤 電連Γ該it===於層與叙間係以插絲〇及_ 層中形成介相(via)，顯容結構之作法乃先在介電 最後侧該紹金屬層，形成後:再於插塞上沈積銘金屬層， 於插塞之規格，而無法進—士吉二/、。上述習知之積體電容結構受限 5 1239631 【發明内容】 據此，本發明之主要目的在於提供一種高積集度積體電容，可以應用 於類比/數位轉換器（A/D converter)或數位/類比轉換器（D/A converter) 或切換電路(switch cap circuit)設計中。 本發明之另一目的在於提供一種高積集度雙鑲嵌式積體電容，以雙鑲 欲銅製程構成垂直式電容板或電容柱，可不受限於習知技藝中之插塞規 格’僅需控制電容板或電容柱之間的距離即可有效提昇電容值。 在本發明之最佳實施例中，揭露了一種垂直式積體電容，包含有一半 導體基底；一第一垂直電容電極板設於該半導體基底上，該第一垂直電容 電極板係由複數個並列之第一鑲嵌(damascene )導電條上下經由複數個第 一鑲肷；丨層插塞互相電連接所構成；以及一第二垂直電容電極板，其與該 第一垂直電容電極板平行設置於該半導體基底上，該第二垂直板係由複數 個並列第二導電條上下經由複數個第二鑲嵌介層插塞互相電連接所構成。 根據本發明之另一實施例，揭露一種垂直式積體電容，包含有一半導 體基底；一第一垂直電容柱設於該半導體基底上，該第一垂直電容柱係由 複數個第一鑲嵌導電塊上下經由複數個第一鑲嵌介層插塞互相電連接所構 成，以及一苐一垂直電容柱，其與該第一垂直電容柱平行設置於該半導體 基底上，該第二垂直電容柱係由複數個第二鑲嵌導電塊上下經由複數個第 二鑲嵌介層插塞互相電連接所構成。 根據本發明之另一實施例，揭露一種垂直式積體電容，包含有一半導 體基底ϋ直電容電極板設於該轉縣紅，該垂直電容電極板係由 複數個並列之鑲礙導電條上下經由複數個第一鑲嵌介雜塞互相電連接所 構成；以及ϋ電雜設於該半導縣紅，職直電雜係由複數個 6 1239631 鑲肷$電塊Jl下ϋ由複數個第二鑲嵌介層減互相電連接所構成。 為讓本發明之上述目的、特徵、和優點能更_紐，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 清參閱圖二，圖二為本發明第一較佳實施例之高積集度垂直式積體電 谷500的部份結構放大侧視圖。如圖三所示，依據本發明之第一較佳實施 例，本發明高積集度積體電容_設於_轉體基底（圖未示)上，係由複 數個平行垂直金屬板501及5G2構成，其中垂直金屬板·與垂直金屬板 502係分別電連接不同電極，例如，垂直金屬板5〇1係為負極㈠，而垂直 金屬板502係接正極⑴。為方便說明，介於垂直金屬板5〇1及·之間的 介電層並未顯示。 如圖三所示，依據本發.第—健實施例，高積集度垂直式積體電 容500具有指型交叉排列之電極結構。垂直金屬板5〇1包含有複數層镶嵌 金屬線510、514、518，其並以鑲喪介層插塞512及516形成内連結。形成 本發明具心型X叉制電極結構之高積集度垂直式频電容删的作法， 首先以鑲嵌銅(copper damascene)製程在第-介電層中（圖未示)形成第一 層交叉指型鑲敌銅導線圖案510及520,接著於第一介電層以及第一層交又 指型鑲嵌銅導線圖案510及520上覆蓋第二介電層（圖未示），然後進^于雙 鑲嵌(dual damascene)製程，以於第二介電層内形成第二 銅導線圖案514、524及鑲嵌介層插塞512、522。接著，重複上述雙镶嵌製 程步驟’形成第三層交又指型鑲嵌銅導線圖案518、卿及鑲&介層插塞 516、526，如此堆疊出本發明高積集度垂直式積體電容5〇〇，且有^型^叉 排列之電極結構。上述之鑲喪製程或雙鑲嵌製程係指先在介電層中侧出 導線介層洞溝渠，接著填入銅金屬，最後加以研磨平坦化之製程，其詳細 製程乃該行業者所熟知，因此不再贅述。 /' 、 1239631 本發明藉由鑲嵌製程構成垂直式電容電極板係由不同層之鑲嵌銅導線 圖案以及鑲嵌介層插塞所堆疊而成，因此可以最小線寬製作，將電容電極 板之間距縮至最小，藉此獲得最大之電容值。此外，本發明結合銅鑲欲製 程以製作積體電容乃習知未有之作法。 〜請參閱圖四，圖四為本發明第二較佳實施例之高積集度垂直式積體電 容600的部份結構放大側視圖。如圖四所示，依據本發明之第二較佳實施 例，本發明南積集度積體電容6〇〇係由複數個垂直電容電極柱⑼1以及複 數個垂直電容電極柱602所構成，其中垂直電容電極柱6〇1與垂直電容電 極柱602係分別電連接不同電極，例如，垂直電容電極柱6〇1 /係接正極(+)， 垂直電容電極柱602接負極(-）。為方便說明，介於垂直電容電極柱與 垂直電谷電極柱602之間的介電層並未顯示。 如圖四所示，依據本發明之第二較佳實施例，垂直電容電極柱6〇1包 3有複數層鑲嵌金屬區塊610、614、618，其並以鑲嵌介層插塞612及616 形成内連結。形成本發明之高積集㈣直式柱狀積體電容刪的作法，首 先以鑲嵌銅(copper damascene)製程在第一介電層中（圖未示）形成第一層 鑲後銅導線區麵案61〇及62()，接著於第—介電層以及第—層職銅導線 ，塊圖案610及620上覆蓋第二介電層（圖未示），然後進行雙鑲欲(㈣ amascene)製程’以於第二介電層内形成第二層鑲嵌銅導線區塊圖案⑽、 624及鑲篏介層插塞612、622。接著，重複上述雙鑲後製程步驟，形成第 二層鑲，銅導線區塊圖案618、628及镶嵌介層插塞616、626，如此堆疊出 本發明高積集度垂直式柱狀積體電容600。 ，參閱圖五，圖五為本發明第三較佳實施例之高積集度垂直式積體電 二0的射〃結槪大舰圖。如圖五所示，依據本發明之第三較佳實施 2本發明高積集度積體電容·係由垂直電容電極板7〇1以及複數個垂 直電容電極柱702所構成，其中垂直電容電極柱顺由垂直電容電極板7〇1 1239631 圍繞。垂直電容電極板701與垂直電容電極柱702係分別電連接不同電極， 例如，垂直電容電極板7〇1係接負極(―），垂直電容電極柱702接正極(+)， 反之亦可。為方便說明，介於垂直電容電極板701與垂直電容電極柱7〇2 之間的金屬層間介電（inter-metal dielectric)層並未顯示。 如圖五所示，依據本發明之第三較佳實施例，垂直電容電極板7〇1包 含有複數層鑲嵌金屬線710、714、718，其並以鑲嵌介層插塞712及716形 成内連結。垂直電容電極柱702包含有複數層鑲嵌金屬區塊72〇、724、728^ 其並以鑲嵌介層插塞722及726形成内連結。形成本發明之高積集度垂直 式柱狀積體電容700的作法，首先以鑲嵌銅(copper damascene)製程在第 一介電層中（圖未示)形成第一層鑲嵌銅導線圖案71〇以及第一層鑲嵌銅導 線區塊圖案720，接著於第一介電層、第一層鑲嵌銅導線圖案71〇以及第一 層鑲嵌銅導線區塊圖案720上覆蓋第二介電層（圖未示），然後進行雙鑲嵌 (dual damascene)製程，以於第二介電層内形成第二層鑲嵌銅導線圖案人 714、鑲嵌介層插塞712以及第二層鑲嵌銅導線區塊圖案724與鑲嵌介層插 塞722。接著’重複上述雙鑲後製程步驟，如此堆疊出本發明高产 式積體電容700。 m 請參閱圖六，圖六為本發明第四較佳實施例之高積集度垂直式積體電 容細的部份結構放大側棚。如圖六所示，依據本發明之第四較佳實施 例，本發明高帛集度積體電容_係由立體樑柱電極結構8〇1以及立體 irrf802所構成，其中立贿㈣極結構8〇1以及立體樑柱電極結 1錯醜。立體雛電極結構则以及塊_極結構 糸刀別電連接不ISJ電極’例如，立體雛電極結構8Q1係接正極⑴，立 接負極㈠，反之亦可。同樣地，介於立體樑柱電極結構 801 U及立體樑柱電極、结構8〇2之間的金屬層間介電層並未顯示。 在其它本發明之實關巾，亦可以相麵三至. 電谷500、600、700、800之上，另外形成有一金屬^ I屬盤（圖未不），該金屬盤 9 1239631 以獲得更大之電容值。 透過—介層金屬與下方的電容正極或負極電連接 【圖式簡單說明】 圖式之簡單說明 圖一為習知積體電容結構之電極側視示意圖 圖一為圖一中之習知積體電容結構沿著切線XIV-XIV之剖面圖。 圖二為本發明第—較佳實關高積紐垂直式傾電容的部份結構放大 侧視圖。 ^ 圖四為本發明第二較佳實細高積紐垂直式積體電容的部份結構放大 側視圖。 ° 圖五為本發明第三較佳實施例高積集度垂直式積體電容的部份結構放大 側視圖。 ° 圖 六為本發明第四較佳實施例之高積集度垂直式積體電容 大侧視圖。 的部份結構放 圖式之符號說明 300 積體電容 310、312、314、316 電容電極 320、322、324、326 電容電極 330、340 插塞 500 積體電容 501、502 垂直金屬板 1239631 510、514、518 鑲嵌金屬線 520、524、528 鑲嵌金屬線 512、516 鑲嵌介層插塞 522、526 鑲嵌介層插塞 600 積體電容 601、602 垂直電容電極柱 610、614、618 鑲後金屬區塊 620、624、628 鑲嵌金屬區塊 612、616 鑲嵌介層插塞 622、626 镶後介層插塞 700 積體電容 701 垂直金屬板 702 垂直電容電極柱 710、714、718 镶欲金屬線 720、724、728 鑲欲金屬區塊 712、716 鑲嵌介層插塞 722、726 鑲嵌介層插塞 800 積體電容 801 ^ 802 立體樑柱電極結構 111239631 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to an integrated capacitor, especially a vertical integrated capacitor structure, and is particularly suitable for use in analog / digital converters. Or digital / analog converter (D / A converter) or switch cap circuit field. [Previous technology] Passive components such as 'electric valleys' have been widely used in radio frequency (RF) and mixed-signal circuits, and have been used in filters, resonance circuits, etc. , And circuit design (bypass). And in order to reduce the cost of raw silk, IC manufacturers or designers must make efforts to improve the integration of integrated circuits. See Figure-and Figure 2, where Figure 1 is a schematic side view of the electrode of the conventional integrated capacitor structure 300, Figure 2 is a diagram of the conventional integrated capacitor structure 300 in Figure-chat along the tangent line- This is called a surface map Λ 316 ^ 326, ^ No, the two adjacent electrode fingers arranged by the parent are connected with different polarities. Tian-Jin Electric Co., Ltd. It === forms a via in the layer and the intersegmental system with a wire 0 and _ layer. The method of explicit capacitance structure is to form the metal layer on the last side of the dielectric to form After: deposit a metal layer on the plug to fit the specifications of the plug, but it cannot enter-Shiji II / ,. The conventional integrated capacitor structure is limited 5 1239631 [Summary] Accordingly, the main object of the present invention is to provide a high integration density integrated capacitor, which can be applied to analog / digital converter (A / D converter) or digital / D / A converter or switch cap circuit design. Another object of the present invention is to provide a dual-mosaic integrated capacitor with a high accumulation degree. A vertical capacitor plate or a capacitor column is formed by a dual-inlay copper process, which is not limited to the plug specifications in the conventional art. Controlling the distance between the capacitor plate or capacitor column can effectively increase the capacitance value. In a preferred embodiment of the present invention, a vertical integrated capacitor is disclosed, which includes a semiconductor substrate; a first vertical capacitor electrode plate is disposed on the semiconductor substrate, and the first vertical capacitor electrode plate is formed by a plurality of side by side A first damascene conductive strip is formed by a plurality of first inlays up and down; 丨 layer plugs are electrically connected to each other; and a second vertical capacitor electrode plate is disposed parallel to the first vertical capacitor electrode plate On the semiconductor substrate, the second vertical plate is composed of a plurality of parallel second conductive strips which are electrically connected to each other via a plurality of second damascene vias. According to another embodiment of the present invention, a vertical integrated capacitor is disclosed, including a semiconductor substrate; a first vertical capacitor pillar is disposed on the semiconductor substrate, and the first vertical capacitor pillar is composed of a plurality of first mosaic conductive blocks. The upper and lower layers are electrically connected to each other through a plurality of first mosaic via plugs, and a vertical capacitor column is arranged on the semiconductor substrate in parallel with the first vertical capacitor column. The second vertical capacitor column is composed of a plurality of The second inlaid conductive blocks are electrically connected to each other via a plurality of second inlaid interlayer plugs. According to another embodiment of the present invention, a vertical integrated capacitor is disclosed, which includes a semiconductor substrate, a straight capacitor electrode plate provided in the Zhuanxian Red, and the vertical capacitor electrode plate is passed up and down by a plurality of side-by-side blocking conductive strips. A plurality of first mosaic insert plugs are electrically connected to each other; and an electric hybrid is located in the semi-conductive county of Hong, and a direct electric hybrid system is composed of a plurality of 6 1239631 inlaid $ electric blocks Jl. The lower insert is composed of a plurality of second mosaics The dielectric layer is formed by reducing electrical connection with each other. In order to make the above-mentioned objects, features, and advantages of the present invention even better, a preferred embodiment is given below and described in detail with the accompanying drawings. [Embodiment] Please refer to FIG. 2. FIG. 2 is an enlarged side view of a part of the structure of the high-integration vertical integrated valley 500 according to the first preferred embodiment of the present invention. As shown in FIG. 3, according to the first preferred embodiment of the present invention, the high-integration integrated capacitor of the present invention is provided on a swivel substrate (not shown), and is composed of a plurality of parallel vertical metal plates 501 and 5G2 structure, wherein the vertical metal plate and the vertical metal plate 502 are electrically connected to different electrodes, for example, the vertical metal plate 501 is a negative electrode ㈠, and the vertical metal plate 502 is connected to a positive electrode ⑴. For the convenience of explanation, the dielectric layer between the vertical metal plates 501 and · is not shown. As shown in FIG. 3, according to the first embodiment of the present invention, the high-integration-degree vertical integrated capacitor 500 has an electrode structure in which fingers are arranged crosswise. The vertical metal plate 501 includes a plurality of layers of inlaid metal wires 510, 514, and 518, and an inner connection is formed by inserting interposer plugs 512 and 516. To form a high-integration vertical frequency capacitor with a heart-shaped X-fork electrode structure according to the present invention, firstly, a first layer of cross-layers is formed in a copper dielectric (copper damascene) process in a first dielectric layer (not shown). Finger-type inlay copper wire patterns 510 and 520, and then cover the second dielectric layer (not shown) on the first dielectric layer and the first interdigitated copper-wire pattern 510 and 520, and then enter the A dual damascene process is used to form second copper wire patterns 514 and 524 and damascene via plugs 512 and 522 in the second dielectric layer. Next, repeat the above dual-damascene process steps to form a third-layer cross-finger-type inlaid copper wire pattern 518, green and inlay & interposer plugs 516, 526, so as to stack the highly integrated vertical integrated capacitor of the present invention. 500, and has a ^ type ^ cross electrode arrangement. The above-mentioned inlaying process or double inlaying process refers to a process in which a wire interlayer trench is firstly flared in a dielectric layer, then filled with copper metal, and finally polished and flattened. The detailed process is well known to those in the industry, so it is not More details. / ', 1239631 In the present invention, a vertical capacitor electrode plate is formed by a damascene process, which is formed by stacking inlaid copper wire patterns and inlay interposer plugs of different layers, so it can be produced with the smallest line width and reduce the distance between capacitor electrode plates To the minimum, to obtain the maximum capacitance value. In addition, the present invention combines a copper inlay process to make a bulk capacitor, which is a conventional method. Please refer to FIG. 4. FIG. 4 is an enlarged side view of a part of the structure of the high-integration vertical integrated capacitor 600 according to the second preferred embodiment of the present invention. As shown in FIG. 4, according to a second preferred embodiment of the present invention, the integrated product capacitor 600 of the present invention is composed of a plurality of vertical capacitor electrode posts ⑼1 and a plurality of vertical capacitor electrode posts 602, wherein The vertical capacitor electrode column 601 and the vertical capacitor electrode column 602 are respectively electrically connected to different electrodes. For example, the vertical capacitor electrode column 601 / is connected to a positive electrode (+), and the vertical capacitor electrode column 602 is connected to a negative electrode (-). For convenience, the dielectric layer between the vertical capacitor electrode column and the vertical valley electrode column 602 is not shown. As shown in FIG. 4, according to the second preferred embodiment of the present invention, the vertical capacitor electrode column 601 package 3 has a plurality of layers of inlaid metal blocks 610, 614, and 618, which are inlaid with interlayer plugs 612 and 616. Formation of internal links. The method of forming the high-concentration, straight-type columnar bulk capacitor of the present invention is to first form a first layer of copper-inlaid copper wire area in a first dielectric layer (not shown) by a copper damascene process. Cases 61 and 62 (), followed by the first dielectric layer and the first layer copper conductors, covered with a second dielectric layer (not shown) on the block patterns 610 and 620, and then performed a double inlay (mas amascene) The process is to form a second layer of inlaid copper wire block patterns ⑽, 624 and 篏 inlay dielectric layer plugs 612, 622 in the second dielectric layer. Next, repeat the above-mentioned dual-mounting process steps to form a second layer of inserts, copper wire block patterns 618, 628, and inlay via plugs 616, 626, so as to stack the highly integrated vertical columnar integrated capacitors of the present invention. 600. Please refer to FIG. 5. FIG. 5 is a diagram of a high-concentration vertical vertical integrated power generator 20 that is a high-integration degree integrated electric generator 20. FIG. As shown in FIG. 5, according to the third preferred embodiment 2 of the present invention, the high-capacity integrated capacitor is composed of a vertical capacitor electrode plate 701 and a plurality of vertical capacitor electrode columns 702, of which the vertical capacitor electrode The post is surrounded by a vertical capacitor electrode plate 701 1239631. The vertical capacitor electrode plate 701 and the vertical capacitor electrode column 702 are respectively electrically connected to different electrodes. For example, the vertical capacitor electrode plate 701 is connected to the negative electrode (-), and the vertical capacitor electrode column 702 is connected to the positive electrode (+), and vice versa. For convenience of explanation, an inter-metal dielectric layer between the vertical capacitor electrode plate 701 and the vertical capacitor electrode pillar 702 is not shown. As shown in FIG. 5, according to a third preferred embodiment of the present invention, the vertical capacitor electrode plate 701 includes a plurality of layers of inlaid metal wires 710, 714, and 718, and is formed by inlaying vias 712 and 716. link. The vertical capacitor electrode post 702 includes a plurality of layers of inlaid metal blocks 72, 724, and 728, and internal interconnections are formed by the inlay via plugs 722 and 726. To form the highly integrated vertical columnar bulk capacitor 700 of the present invention, first, a first damascene copper wire pattern 71 is formed in a first dielectric layer (not shown) by a copper damascene process. And a first layer of copper wire block pattern 720, and then a second dielectric layer is overlaid on the first dielectric layer, the first layer of copper wire block pattern 71, and the first layer of copper wire block pattern 720 (not shown) (Shown), and then a dual damascene process is performed to form a second layer of inlaid copper conductor pattern 714, a mosaic of interlayer plug 712, and a second layer of copper conductor block pattern 724 in the second dielectric layer. Mosaic via plug 722. Then, the above-mentioned double post-mounting process steps are repeated to stack the high-capacity integrated capacitor 700 according to the present invention. Please refer to FIG. 6. FIG. 6 is an enlarged side shed of a partial structure of a high-integrity vertical integrated capacitor with a small height according to a fourth preferred embodiment of the present invention. As shown in FIG. 6, according to a fourth preferred embodiment of the present invention, the high-density integrated capacitor according to the present invention is composed of a three-dimensional beam-column electrode structure 801 and a three-dimensional irrf802 structure, in which a bridging pole structure 8 〇1 and three-dimensional beam-column electrode junction 1 are ugly. The three-dimensional chick electrode structure and the block-pole structure are not electrically connected to the ISJ electrode. For example, the three-dimensional chick electrode structure 8Q1 is connected to the positive electrode ⑴ and the negative electrode 立, and vice versa. Similarly, the interlayer dielectric layer between the three-dimensional beam-column electrode structure 801 U, the three-dimensional beam-column electrode structure, and the structure 802 is not shown. In other practical towels of the present invention, they can also face each other. Power valleys 500, 600, 700, 800, and a metal ^ I metal plate (not shown), the metal plate 9 1239631 to get more Large capacitance value. Through-the interlayer metal is electrically connected to the positive or negative capacitor of the capacitor [simple description of the diagram] Figure 1 is a schematic side view of the electrode of the conventional capacitor structure. Figure 1 is the conventional capacitor in Figure 1. A cross-sectional view of the capacitor structure along a tangent line XIV-XIV. FIG. 2 is an enlarged side view of a part of the structure of the first-preferred high-capacity vertical tilt capacitor of the present invention. ^ Figure 4 is an enlarged side view of a part of the structure of the second preferred solid high-capacity vertical integrated capacitor of the present invention. ° Figure 5 is an enlarged side view of a part of the structure of a high-integration vertical integrated capacitor in a third preferred embodiment of the present invention. ° Fig. 6 is a large side view of a high-integration vertical vertical integrated capacitor in a fourth preferred embodiment of the present invention. Part of the structure is shown graphically. 300 integrated capacitors 310, 312, 314, 316 capacitor electrodes 320, 322, 324, 326 capacitor electrodes 330, 340 plugs 500 integrated capacitors 501, 502 vertical metal plates 1239631 510, 514, 518 Inlaid metal wire 520, 524, 528 Inlaid metal wire 512, 516 Inlaid interposer plug 522, 526 Inlaid interposer plug 600 Integrated capacitor 601, 602 Vertical capacitor electrode post 610, 614, 618 Inlaid metal area Blocks 620, 624, 628 Inlaid metal blocks 612, 616 Inlaid interposer plugs 622, 626 Inlaid back interposer plugs 700 Integrated capacitors 701 Vertical metal plates 702 Vertical capacitor electrode posts 710, 714, 718 Inlaid metal wires 720 , 724, 728 Inlaid metal block 712, 716 Inlaid interposer plug 722, 726 Inlaid interposer plug 800 Integrated capacitor 801 ^ 802 Three-dimensional beam-column electrode structure 11