TWI239622B - Integral structure of chip and multi-layer plate - Google Patents

Integral structure of chip and multi-layer plate Download PDF

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Publication number
TWI239622B
TWI239622B TW093136510A TW93136510A TWI239622B TW I239622 B TWI239622 B TW I239622B TW 093136510 A TW093136510 A TW 093136510A TW 93136510 A TW93136510 A TW 93136510A TW I239622 B TWI239622 B TW I239622B
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TW
Taiwan
Prior art keywords
conductive
item
layer
scope
patent application
Prior art date
Application number
TW093136510A
Other languages
Chinese (zh)
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TW200618239A (en
Inventor
Chi-Chao Tseng
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093136510A priority Critical patent/TWI239622B/en
Application granted granted Critical
Publication of TWI239622B publication Critical patent/TWI239622B/en
Publication of TW200618239A publication Critical patent/TW200618239A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

A complex structure integrates one or more chips in or on a multi-layer plate. The connecting structures in or on the multi-layer plate are employed to electrically connect the chips directly or indirectly. Thus the size reduction of a package can be achieved.

Description

C39622 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種晶片結合至多層板中製作 的結構，特別是提供一種可整合晶片與多層板的 複合式結構。 【先前技術】 現7 ，半導體元件封裝朝向縮小尺寸與低成 的方面努力，因此各式各樣的封裝結構因蘊而 一_般所謂的封裝結構，不外乎將一或多個晶 h沾$基板’例如一傳統印刷電路板，完成電性 的連接，之後再覆以保護或散熱的結構。 哎封;制^述傳統結構於進行傳統電路板製作 Π製冗長…性所需的電 息息相關，的上I作大多與連接結構的性質與效能 上’ 上述於現今欲降低製作時間與成本 欲縮小：：：：因*。再者’既定的封裝結構於 【發明内容】面能改善的幅度亦有限。 以達有二於〗、上體:背1中’有關整合晶片與多層板 層板製作a#古f，此提供一複合式結構，於多 封敦結構：直接將晶片包覆於其中，彳縮小整個 5 1239622 再者’鐘於整合多層杯盤^ η ^ ^ λλ 夕層扳裟作與封裝製作以達 Μ P ^ ^ m r, 於此獒供〜種以多層板作為 封裝的結構，應用於多層板内 來電性連接晶Μ，並放置曰片：有的内連f、·，。構 乂七h壯， 置曰日片於其中，可省略製 作封裝的步驟，並且達到、 J日乃封装的目的0 ，提供 第一連 板包含 導電層 導電結 層板内 層。第 接觸導 Ί上述之目的，本發明之例 一種複合式結構’包含一多層板、a 接結構、導電結構與第二連接結構:曰多層 複數個導電層與複數個絕緣層，其中任一 與任二絕緣層緊鄰，晶片位於多層板内， 構則位於多層板上。第一連接結^位於多 並接觸晶片，且電性連接晶片與任一導電 二連接結構位於多層板上，且電性連接並 電結構與任一導電層。 【實施方式】 本發明之實施例用示意圖詳細描述如下，在詳述本 發明之實施例時，表示複合式結構的部份會放大顯示並 說明’然不應以此作為有限定的認知。此外，在實於的 複合式結構與方法中，應包含此結構中其他必要^ 分。 ϋ 其次’當本發明之實施例圖式中的各元件或結構以 單一元件或結構描述說明時’不應以此作為有限^的認 知，即如下之說明未特別強調數目上的限制時，本發= 之精神與應用範圍可推及多數個元件或結構並存的結構 與方法上。 第一圖所示為本發明之一第一實施例說明晶片與載 板之複合式結構的剖面示意圖。參照第一圖，複合式 結構10主要包含一多層板與一晶片12於多層板内。 複合式結構10亦可包含一導電結構18位於表面上。 多層板包含一或多層導電層17與絕緣層13、15，其 中相鄰兩層導電層17之間利用絕緣層13或15來絕 緣，且經由導通結構19而導通。晶片i 2可位於絕緣 層13中’其利用絕緣層13與導電層17絕緣，並利 用連接結構14與導電層17導電地連接。導電結構18 位於絕緣層15上，其利用連接結構16與導電層17 導電地連接。 —- 們斯網泊層驭鍍銅層， 包含-般的内層線路I、外層線路層（圖案化導電層）卑 接地層，其厚度可相同或相異’但不限於此。於此實摊 例中’導電層17為兩外層線路層。其:欠，導通結構19， ，如-電㈣孔’包含導電側壁層與其所包圍之絕緣層 5^此實施例中，導通結構19為—導電塞孔，利用 :銅：性連接_ 17 ’但不限於此。於另一實施例 :緣ΠΠ 為以一般方式形成之-中空導通孔。 或介於導電層17之=/面 之-部分’用以提供絕緣與保護之用。於此實施例中， 絕緣層13可為一般印刷多層板中的内層絕緣層，而絕 緣層15則可為表面綠漆保護層，但不限於此。 再者，晶片12為一般用途之單一晶片，其表面具 有已配置之導電接墊（connecting pad)作為連接結構 14或連接結構14之一部分。於此實施例中，晶片12 上之導電接墊，例如一鋁接墊或包含黏著（adhesi〇n) 與阻障（barrier)作用之接塾，構成連接結構14以提供 晶片12電性連接至導電層17。於另一實施例中，連 接結構14則可包含製作多層板時形成的導電盲孔。其 -人，連接結構16係可包含黏著與阻障作用之接墊，但 不限於此。導電結構18，例如-錫球（solder ball)、 無錯凸塊（lead-free bump)或金凸塊（g〇ld stud)，提 供複合式結構10外部電性連接之用，亦可對内藉由導 電層17及導通結構19而與晶片12電 第二圖所示為本發明之一第二實施例說明晶片與載 複合式結構的剖面示意圖。基本結構與形成方式係 和苐-實施例相同’但與第—實施例料狀處在於連 接結構14包含導電接塾14b與導電盲孔14& 塾刚係直接製料晶片12。另-方面，導電盲孔= 則於製作多層板時形成，可包含孔鋼與底銅及底塾 不限於此。 ~ ~ 第三圖所示為本發明之一第三實施例說明晶片與載 结:冓的剖面示意圖。基本結構與形成方式係 和第二實施例相同’但與第二實施 合式結構10更包含一散熱結構20位於絕緣層15 ΐ 並且一電絕緣層21介於散熱結構20與導電層17之 間。由於電絕緣層21很薄，晶片12操作時所產生的 熱可透過連接結構14及導電層17傳遞至 姓 公，由散熱結構20將晶片12所產生的熱快速傳』 :面。於一實施例中，散熱結構2〇為-平板狀金屬結 構，厚度可依設計與所需而定，但不限於此。 第四圖所示為本發明之一第四實施例說明晶片與載 板之複合式結構的剖面示意圖。相較於第二實施例，、第 二實施例中的晶片12係為—覆晶晶片，經由連接結構 再導，層17與連接結構16後連接至導電結構18。 #摄，晶片12可藉由連接結構14、導電層17與連接 :16電性連接至導電結構18，可藉此與外界電性 第五圖所示為本發明之—第五實施例說明晶片 板：複合式結構的剖面示意圖。相較於第四實施例，第 熱結構2。與—電U ;二包含第三實施例中的散 :f之間。由於電絕緣層21报薄，此時晶片12操 作時所產生的熱透過導電声子月 操 2〇。 守罨層17直接傳遞至散熱結構 板為本發明之—第六實施例說明晶片與載 板：複口式、，，。構的剖面示意圖。相較於第一實施例，第 六實施例的複合式結構10更包二實：： 上’並藉由連接結構24連接至導電層17上之連= 構26’且更進一步藉由導通結構19、導電層17與連 接結構16電性連接至導電結構18。於此實施例中， 連接結構24包含接墊24a與導線24b，其中導線24b 可利用打線（wiring)的方式形成。連接結構26與連接 結構16類似，可提供黏著、潤濕或阻障之用。可選擇 的，本實施例中更可包含散熱結構（圖上未示）於複合式 結構10中。 第七圖所示為本發明之一第七實施例說明晶片與載 板之複合式結構的剖面示意圖。相較於第四實施例，第 七實施例的複合式結構1〇更包含第六實施例中的晶片 22、連接結構24與連接結構26。可選擇的，本實施 例中更可包含散熱結構（圖上未示）於複合式結構1 〇 中〇 第八圖所示為本發明之1人實施例說明晶片與載 板之複合式結構的剖面示意圖。相較於第一實施例，第 八實施例的複合式結構10係包含較多層的導電層17, 除了導通結構19外，内部導電層17更可藉由導電盲 孔14a進行電性連接。此外，對於晶片12而言 過多層板之間的導電層17與導電盲孔⑷電性連接至 二再者，相較於第七實施例，第八實施例 的曰曰片2所利用的連接結構24可為-導電球以植球 2开:二二於第七實施例的打線方式形成。可選擇的， 1〇 ^ 可包含散熱結構（圖上未示）於複合式結構 1239622 第九圖所示為本發明之一第九實施例說明晶片與載 板之複合式結構的剖面示意圖。相較於第八實施例，第 九實施例中的晶片12係為一覆晶晶片，與第四實施例 相似。可選擇的，本實施例中更可包含散熱結構（圖上 未示）於複合式結構1 〇中。 第十圖所示為本發明之一第十實施例說明晶片與載 板之複合式結構的剖面示·意圖。相較於第八實施例，第 十實施例中的複合式結構10包含一堆疊晶片結構於其 上’其中晶片22的連接方式與第八實施例中的晶片22 相同，晶片32的連接方式則與第六實施例中的晶片22 相同，晶片22與晶片32則可以一黏著結構34相互 固定。可選擇的，本實施例中更可包含散熱結構（圖上 未示）於複合式結構10中。 第十一圖所示為本發明之一第十一實施例說明晶片 與載板之複合式結構的剖面示意圖。相較於第十實施 例，第十一實施例中的晶片12係為一覆晶晶片，與第 四實施例相似。可選擇的，本實施例中更可包含散熱結 構（圖上未示）於複合式結構10中。 根據上述，一種複合式結構，整合一或多晶 片與多層板，可使封裝結構更形縮小，其包含一 多層板、一第一晶片位於多層板内、一第一連接 結構、一導電結構位於多層板上、一第二連接結 構、至少一第二晶片與一第三連接結構位於多層 板上。多層板包含複數個導電層與複數個絕緣 層，其中任一導電層與任二絕緣層緊鄰。第一連 11 1239622 j結構位於多層板内，且電性連接第一晶片與任 一導電層。第二連接結構位於多層板上，且電性 連接導電結構與任一導電層。第三連接結構電性 連接第二晶片及最接近多層板表面的導電層。 以上所述之實施例僅係為說明本發明之技術思想及 少點，其目的在使熟習此項技藝之人士能夠瞭解本發明 内容並據以實施，當不能以之限定本發明之專利範 ，即大凡依本發明所揭示之精神所作之均等變化或修 ’仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 一實施例說明晶片與載 第一圖所示為本發明之一第 板之複合式結構的剖面示意圖。 二實施例說明晶片與載 三實施例說明晶片與載 四實施例說明晶片與載 五實施例說明晶片與載 第二圖所示為本發明之一第 板之複合式結構的剖面示意圖。 第三圖所示為本發明之一第 板之複合式結構的剖面示意圖。 第四圖所示為本發明之一第 板之複合式結構的剖面示意圖。 第五圖所示為本發明之一第 板之複合式結構的剖面示意圖。 12 1239622 第六圖所示為本發明之一第六實施例說明晶片與載 板之複合式結構的剖面示意圖。 第七圖所示為本發明之一第七實施例說明晶片與載 板之複合式結構的剖面示意圖。 第八圖所示為本發明之一第八實施例說明晶片與載 板之複合式結構的剖面示意圖。 ^ 第九圖所示為本發明之一第九實施例說明晶片與載 板之複合式結構的剖面示意圖。 第十圖所示為本發明之一第十實施例說明晶片與載 板之複合式結構的剖面示意圖。 第十一圖所示為本發明之一第十一實施例說明晶片 與載板之複合式結構的剖面示意圖。 【主要元件符號說明】 10 複合式結構 12 晶片 13 絕緣層 14 連接結構 14a 導電盲孔 14b 導電接墊 15 絕緣層 16 連接結構 13 1239622 17 導電層 18 導電結構 19 導通結構 20散熱結構 2 1 電絕緣層 22 晶片 24 連接結構 24a 接墊 24b 導線 26 連接結構 3 0 晶粒 32 晶片 34 黏著結構C39622 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a structure in which a wafer is incorporated into a multilayer board, and in particular, it provides a composite structure capable of integrating a wafer and a multilayer board. [Previous technology] Now, semiconductor device packages are working towards reducing the size and cost. Therefore, a variety of package structures are generally called package structures because of the connotation, except that one or more crystals are attached. The "substrate" is, for example, a conventional printed circuit board, which is electrically connected and then covered with a structure for protection or heat dissipation. Hey, the production of traditional structures is related to the lengthy electrical requirements of traditional circuit board production. Most of the previous work is related to the nature and performance of the connection structure. The above is to reduce the production time and cost. ::::because*. Furthermore, the established package structure is limited in terms of [Summary of the Invention]. There are two parts in the upper body: back 1 in the "relating to the integration of wafers and multi-layer board production a # ancient f", this provides a composite structure, in a multiple seal structure: the wafer is directly wrapped in it, shrink The entire 5 1239622 and 'Zhong Yu integrated multi-layer cups and plates ^ η ^ ^ λλ The layer operation and packaging production to achieve MP P ^ ^ mr, here are provided ~ a kind of multi-layer board as a package structure, applied to multiple layers The board is electrically connected to the crystal M and placed on it: some internal connections f, · ,. The structure can be built for seven hours, and the Japanese film can be placed therein. The step of making the package can be omitted, and the purpose of packaging can be achieved. The first connection board includes a conductive layer and an inner layer of a conductive junction board. The first contact guide aims at the above purpose, and an example of the present invention is a composite structure including a multilayer board, an a-joint structure, a conductive structure, and a second connection structure: a plurality of conductive layers and a plurality of insulating layers, any of which Close to any two insulating layers, the wafer is located in the multilayer board, and the structure is located in the multilayer board. The first connection junction is located on the multiple and contacts the chip, and the electrical connection chip is connected to any conductive layer. The second connection structure is located on the multilayer board, and the parallel connection structure is electrically connected to any conductive layer. [Embodiment] The embodiment of the present invention is described in detail with a schematic diagram as follows. When the embodiment of the present invention is described in detail, the part showing the composite structure will be enlarged and explained, but it should not be used as a limited recognition. In addition, the actual composite structure and method should include other necessary points in this structure. ϋ Secondly, when each element or structure in the embodiment of the present invention is described by a single element or structure, it should not be used as a limited recognition, that is, when the following description does not particularly emphasize the number limitation, the present The spirit and scope of development = can be extended to structures and methods where many components or structures coexist. The first figure is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier according to a first embodiment of the present invention. Referring to the first figure, the composite structure 10 mainly includes a multilayer board and a wafer 12 in the multilayer board. The composite structure 10 may also include a conductive structure 18 on the surface. The multilayer board includes one or more conductive layers 17 and insulating layers 13 and 15. Insulating layers 13 and 15 are used to isolate between two adjacent conductive layers 17 and are conducted through a conductive structure 19. The wafer i 2 may be located in the insulating layer 13 ′, which is insulated from the conductive layer 17 by the insulating layer 13 and is conductively connected to the conductive layer 17 by the connection structure 14. The conductive structure 18 is located on the insulating layer 15 and is connected to the conductive layer 17 in a conductive manner by using the connection structure 16. —- The Mens mooring layer is a copper-plated layer, which includes a general ground layer I and an outer layer (patterned conductive layer) ground layer. The thickness may be the same or different ’but is not limited thereto. In this example, the 'conductive layer 17 is two outer circuit layers. Its: the under-conducting structure 19, such as-the electrical counter-via 'includes a conductive sidewall layer and the surrounding insulating layer 5 ^ In this embodiment, the conducting structure 19 is a conductive plug hole, using: copper: sexual connection _ 17' But it is not limited to this. In another embodiment, the edge ΠΠ is a hollow via formed in a general manner. Alternatively, it can be used to provide insulation and protection. In this embodiment, the insulating layer 13 may be an inner insulating layer in a general printed multilayer board, and the insulating layer 15 may be a surface green paint protective layer, but is not limited thereto. Furthermore, the chip 12 is a single chip for general use, and the surface of the chip 12 has a configured conductive pad as the connection structure 14 or a part of the connection structure 14. In this embodiment, a conductive pad on the chip 12, such as an aluminum pad or a connector including adhesion and barrier effects, forms a connection structure 14 to provide the chip 12 to be electrically connected to Conductive layer 17. In another embodiment, the connection structure 14 may include a conductive blind hole formed when a multilayer board is manufactured. Among other things, the connection structure 16 may include adhesive pads and barriers, but is not limited thereto. The conductive structure 18, such as a solder ball, a lead-free bump, or a gold bump, provides a composite structure 10 for external electrical connection, and can also be used for internal The second layer is electrically connected to the chip 12 through the conductive layer 17 and the conductive structure 19. The second figure is a schematic cross-sectional view illustrating a wafer and a carrier-type composite structure according to a second embodiment of the present invention. The basic structure is the same as that of the first embodiment, but the material of the first embodiment lies in that the connection structure 14 includes a conductive connection 14b and a conductive blind hole 14 & On the other hand, the conductive blind hole = is formed during the manufacture of the multilayer board, and can include hole steel, bottom copper and bottom cymbal. ~ ~ The third figure is a schematic cross-sectional view illustrating a wafer and a carrier: 冓 according to a third embodiment of the present invention. The basic structure and the formation method are the same as those of the second embodiment, but the combined structure 10 further includes a heat dissipation structure 20 located at the insulating layer 15 ΐ and an electrically insulating layer 21 interposed between the heat dissipation structure 20 and the conductive layer 17. Since the electrically insulating layer 21 is very thin, the heat generated during the operation of the wafer 12 can be transferred to the surname through the connection structure 14 and the conductive layer 17, and the heat generated by the wafer 12 can be quickly transferred by the heat dissipation structure 20. In one embodiment, the heat dissipation structure 20 is a flat metal structure, and the thickness may be determined according to design and requirements, but is not limited thereto. The fourth figure is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier according to a fourth embodiment of the present invention. Compared with the second embodiment, the wafer 12 in the second embodiment is a flip-chip wafer, which is re-conducted through the connection structure, and the layer 17 and the connection structure 16 are connected to the conductive structure 18. #Photo, the chip 12 can be electrically connected to the conductive structure 18 through the connection structure 14, the conductive layer 17, and the connection: 16, which can be electrically connected to the outside. The fifth figure shows the wafer of the fifth embodiment of the present invention. Plate: A schematic cross-sectional view of a composite structure. Compared with the fourth embodiment, the second thermal structure 2. And-the electric U; the second includes the scattered f in the third embodiment. Since the electrical insulating layer 21 is thin, the heat generated during the operation of the wafer 12 at this time is transmitted through the conductive phonon. The guard layer 17 is directly transferred to the heat dissipation structure board, which is the sixth embodiment of the present invention. The wafer and the carrier board are described as follows: a complex type and a double-sided type. Schematic sectional view. Compared with the first embodiment, the composite structure 10 of the sixth embodiment is more intensive: "upper" and connected to the conductive layer 17 by the connection structure 24 = structure 26 'and further by the conductive structure 19. The conductive layer 17 and the connection structure 16 are electrically connected to the conductive structure 18. In this embodiment, the connection structure 24 includes a pad 24a and a lead 24b, wherein the lead 24b can be formed by a wiring method. The connection structure 26 is similar to the connection structure 16 and can provide adhesion, wetting, or barrier. Alternatively, a heat dissipation structure (not shown in the figure) may be included in the composite structure 10 in this embodiment. The seventh figure is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier board according to a seventh embodiment of the present invention. Compared with the fourth embodiment, the composite structure 10 of the seventh embodiment further includes the chip 22, the connection structure 24, and the connection structure 26 in the sixth embodiment. Alternatively, this embodiment may further include a heat dissipation structure (not shown in the figure) in the composite structure 100. The eighth figure is a one-person embodiment of the present invention illustrating a composite structure of a wafer and a carrier board. Schematic cross-section. Compared with the first embodiment, the composite structure 10 of the eighth embodiment includes a plurality of conductive layers 17, and in addition to the conductive structure 19, the internal conductive layer 17 can be electrically connected through the conductive blind hole 14a. In addition, for the wafer 12, the conductive layer 17 and the conductive blind hole between the multilayer boards are electrically connected to the second and the second. Compared with the seventh embodiment, the connection used in the chip 2 of the eighth embodiment is used. The structure 24 may be-the conductive ball is formed by using the ball planting method 2: 22 in the wire bonding manner of the seventh embodiment. Alternatively, 10 ^ may include a heat dissipation structure (not shown in the figure) in the composite structure 1239622. The ninth figure is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier according to a ninth embodiment of the present invention. Compared with the eighth embodiment, the wafer 12 in the ninth embodiment is a flip-chip wafer, which is similar to the fourth embodiment. Alternatively, the heat dissipation structure (not shown in the figure) may be included in the composite structure 10 in this embodiment. The tenth figure is a cross-sectional view and a schematic view illustrating a composite structure of a wafer and a carrier board according to a tenth embodiment of the present invention. Compared with the eighth embodiment, the composite structure 10 in the tenth embodiment includes a stacked wafer structure thereon, wherein the connection method of the wafer 22 is the same as that of the eighth embodiment, and the connection method of the wafer 32 is Similar to the wafer 22 in the sixth embodiment, the wafer 22 and the wafer 32 can be fixed to each other by an adhesive structure 34. Alternatively, the heat dissipation structure (not shown in the figure) may be included in the composite structure 10 in this embodiment. Fig. 11 is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier plate according to an eleventh embodiment of the present invention. Compared with the tenth embodiment, the wafer 12 in the eleventh embodiment is a flip-chip wafer, which is similar to the fourth embodiment. Alternatively, the heat dissipation structure (not shown in the figure) may be included in the composite structure 10 in this embodiment. According to the above, a composite structure that integrates one or more chips and multi-layer boards can make the packaging structure more compact. It includes a multi-layer board, a first chip is located in the multi-layer board, a first connection structure, and a conductive structure. The second connection structure, at least one second chip and a third connection structure are located on the multi-layer board. The multilayer board includes a plurality of conductive layers and a plurality of insulating layers, and any one of the conductive layers is adjacent to any two of the insulating layers. The first connection 11 1239622 j structure is located in the multilayer board, and is electrically connected to the first chip and any conductive layer. The second connection structure is located on the multilayer board, and is electrically connected to the conductive structure and any conductive layer. The third connection structure electrically connects the second chip and the conductive layer closest to the surface of the multilayer board. The above-mentioned embodiments are only for explaining the technical ideas and a few points of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. When the patent scope of the present invention cannot be limited, That is, any equivalent changes or modifications made in accordance with the spirit disclosed by the present invention should still be covered by the patent scope of the present invention. [Brief description of the drawings] An embodiment illustrates a wafer and a first embodiment. The first figure shows a schematic cross-sectional view of a composite structure of a first plate of the present invention. The second embodiment illustrates the wafer and the carrier. The third embodiment illustrates the wafer and the carrier. The fourth embodiment illustrates the wafer and the carrier. The fifth embodiment illustrates the wafer and the carrier. The second figure is a schematic cross-sectional view of the composite structure of the first board of the present invention. The third figure is a schematic cross-sectional view of the composite structure of the first plate of the present invention. The fourth figure is a schematic cross-sectional view of the composite structure of the first plate of the present invention. The fifth figure is a schematic cross-sectional view of a composite structure of a first plate of the present invention. 12 1239622 The sixth diagram is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier board according to a sixth embodiment of the present invention. The seventh figure is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier board according to a seventh embodiment of the present invention. FIG. 8 is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier board according to an eighth embodiment of the present invention. ^ Figure 9 is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier board according to a ninth embodiment of the present invention. The tenth figure is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier board according to a tenth embodiment of the present invention. Fig. 11 is a schematic cross-sectional view illustrating a composite structure of a wafer and a carrier plate according to an eleventh embodiment of the present invention. [Description of main component symbols] 10 Composite structure 12 Wafer 13 Insulating layer 14 Connection structure 14a Conductive blind hole 14b Conductive pad 15 Insulating layer 16 Connection structure 13 1239622 17 Conductive layer 18 Conductive structure 19 Conducting structure 20 Heat dissipation structure 2 1 Electrical insulation Layer 22 Chip 24 Connection structure 24a Pad 24b Wire 26 Connection structure 3 0 Die 32 Chip 34 Adhesive structure

Claims (1)

12396221239622 、申請專利範圍： 層 片 該導電層 種複合式結構，包含· 一多層板’包含複數個 其中任-該導電層與與稷數個絕轉 一曰Η # ^ Γ 该絕緣層緊鄰； 日日片位於该多層板内； 弟連接結構位於該多層相 苴Ψ^ Χ夕禮板内並接觸該晶 八中a亥弟一連接結構電性 雷展· 丈伐巧日日片與任一 一導電結構位於該多層板上，·及 一第二連接結構位於該多層板上，其 ;J J、结#電性連接ϋ接觸料電結•與任二該 2 ·如申請專利範圍第1 中該多層板更包含至少 導電層與至少一絕緣層 與任一該導電層。 項所述之複合式結構，其 一導通結構穿過該複數個 ，並連接該第二連接結構 3 ·如申請專利範圍第2項所述之複合式結構，其 中該晶片更包含藉由該導通結構電性連接至該導 電結構。 4 ·如申請專利範圍第1頊所述之複合式結構，其 中該晶片更包含藉由該第一連接結構及任一該^ 電層電性連接至該導電結構。 15 1239622 5. 如申請專利範圍第1項所述之複合式結構，更 包含一散熱結構位於該多層板中及一電絕緣層介 於該散熱結構與任一該導電層之間，且藉由任一 該導電層傳遞該晶片所產生的熱。 6. 如申請專利範圍第1項所述之複合式結構，其 中該第一連接結構包含至少一接墊位於該晶片之 一表面上。 7. 如申請專利範圍第6項所述之複合式結構，其 中該第一連接結構更包含至少一導電盲孔位於該 接墊上並穿過至少任一該絕緣層而與任一該導電 層連接。 8. 如申請專利範圍第1項所述之複合式結構，其 中該導電結構係為一導電凸塊。 9. 如申請專利範圍第8項所述之複合式結構，其 中該導電凸塊係為一錫球。 1 0 .如申請專利範圍第 8項所述之複合式結構， 其中該導電凸塊係為一金凸塊。 1 1. 一種複合式結構，包含： 一多層板，包含複數個導電層與複數個絕緣 層，其中任一該導電層與任二該絕緣層緊鄰； 一第一晶片位於該多層板内； 16 1239622 一連接 層； 二連接 層； 至 三連接； 板表面ί 12·如申 其中該： 盲孔係$ 及其他>1 該絕緣J 1 3 ·如申 其中該] 該第一 ί 14如申 其中該： 該多層； 上並穿〗 接。 之複合式結構， 接墊位於並接觸 至少任一該絕緣層而與任一該導電層連 接結構位於該多層板内，其中該第 、’。^、性連接該第一晶片與任一該導電 導電結構位於該多層板上； =連Λ結構位於該多層板上，其中該第 -構電性連接該導電結構與任—該導電 结一 …,网双丄，及 往：iT!構位於該多層板上，其中該第 的該導電層。 乃及取接近该多層 $ ％ <後合式結構， ^一連接結構更包含一導電盲孔，該導電 ®性連J最接近該多層板表面的該導電層 :一該導電層，並穿過該兩導電層 請專利範圍第1 1項所述 ’連接結構包含至少一 ;片之一表面上。 請專利範圍第13項所述之複合式結構， 客一連接結構更包含複數個導電盲孔位於 文中’其中至少一該導電盲孔位於該接墊 17 1239622 15·如申請專利範圍第14項所述之複合式結構， 其中部分該導電盲孔電性連接最接近該多層板 面的該導電層及其他任一該導雷爲 導電層之間的該絕緣層。導電層’…該兩 16.如申請專利範圍第“項所述之複合式結構， 其中該第一連接結構更包含一導電通孔 (through h〇le)穿過該複數個導電層與該複數個 1 7 ·如申請專利範圍第 其中第一晶片更包含藉 該導電結構。 1 6項所述之複合式結構， 由該導電通孔電性連接至 •如申請專利範圍第11項所述之複合式結 中該第三連接結構包含複數個接墊與複數個 凸塊介於該第二晶片與該多層板之間 19·如申請專利範圍第項所述之複合式結構， 其中該第三連接結構包含複數個接墊與複數個導 電線’其中該複數個接墊位於該多層板上，— 該導電線一端連接每一該接墊，另一端 == 二晶片之一表面。 嗎S亥第 20·如申請專利範圍第項所述之複合式結 更包含複數個第二晶片相互堆疊。 18 1239622 2 1 .如申請專利範圍第11項 更包含一散熱結構位於該多 介於該散熱結構與任一該導 構用以傳遞該第一晶片所產」 所述之複合式結構， 層板中及一電絕緣層 電層之間，該散熱結 t的熱。 19Scope of patent application: Plywood This conductive layer has a composite structure, including a multi-layer board 'including a plurality of any of this-the conductive layer is in close contact with a few of them, and the insulation layer is close to the insulation layer; The Japanese film is located in the multilayer board; the connection structure is located in the multi-layered phase plate ^ XX evening gift plate and contacts the crystal eight middle school ai-connection structure electrical thunder show · Zhang Qiao Japanese film and any one The conductive structure is located on the multilayer board, and a second connection structure is located on the multilayer board, which is JJ 、 结 #Electrically connectedϋContact material electric junction • and any two of them The multilayer board further includes at least a conductive layer and at least one insulating layer and any one of the conductive layers. In the composite structure described in item 1, a conductive structure passes through the plurality and is connected to the second connection structure. 3 · The composite structure described in item 2 of the patent application scope, wherein the chip further includes the conductive structure. The structure is electrically connected to the conductive structure. 4. The composite structure as described in claim 1 of the patent application scope, wherein the chip further includes being electrically connected to the conductive structure through the first connection structure and any of the electrical layers. 15 1239622 5. The composite structure described in item 1 of the scope of patent application, further comprising a heat dissipation structure located in the multilayer board and an electrically insulating layer interposed between the heat dissipation structure and any of the conductive layers, and by Any of the conductive layers transfers heat generated by the wafer. 6. The composite structure according to item 1 of the patent application scope, wherein the first connection structure includes at least one pad on a surface of the wafer. 7. The composite structure according to item 6 of the patent application scope, wherein the first connection structure further comprises at least one conductive blind hole located on the pad and passing through at least any of the insulating layers to be connected to any of the conductive layers. . 8. The composite structure described in item 1 of the scope of patent application, wherein the conductive structure is a conductive bump. 9. The composite structure described in item 8 of the scope of patent application, wherein the conductive bump is a solder ball. 10. The composite structure according to item 8 of the scope of the patent application, wherein the conductive bump is a gold bump. 1 1. A composite structure comprising: a multilayer board including a plurality of conductive layers and a plurality of insulating layers, wherein any one of the conductive layers is adjacent to any two of the insulating layers; a first wafer is located in the multilayer board; 16 1239622 One connection layer; Two connection layers; Three connection; Surface of the board ί 12 · As claimed in which: Blind hole system $ and other > 1 The insulation J 1 3 · As claimed in which] The first 14 as Apply it in: The multiple layers; In the composite structure, the pad is located in contact with at least any of the insulating layers and the connection structure with any of the conductive layers is located in the multilayer board, wherein the first and the first. ^, The first chip and any of the conductive conductive structures are located on the multilayer board; = the Λ structure is located on the multilayer board, wherein the first structure electrically connects the conductive structure with any of the conductive junctions ... , Net double 丄, and to: iT! Structure is located on the multilayer board, wherein the first conductive layer. And even close to the multilayer $% < back-closed structure, a connection structure further includes a conductive blind hole, the conductive® J is closest to the conductive layer on the surface of the multilayer board: a conductive layer, and passes through The two conductive layers are described in item 11 of the patent scope, and the 'connection structure includes at least one sheet on one surface. Please refer to the composite structure described in item 13 of the patent scope, and the passenger-connecting structure further includes a plurality of conductive blind holes located in the text 'at least one of the conductive blind holes is located in the pad 17 1239622 15 In the composite structure described above, some of the conductive blind holes are electrically connected to the conductive layer closest to the multilayer board surface and any other lightning conducting layer is the insulating layer between the conductive layers. Conductive layer '... The two 16. The composite structure described in item "Scope of the patent application", wherein the first connection structure further includes a conductive through hole passing through the plurality of conductive layers and the plurality of 1 7 · If the first chip in the scope of the patent application includes the conductive structure. The composite structure described in item 16 is electrically connected by the conductive vias. • As described in item 11 of the scope of patent application. The third connection structure in the composite junction includes a plurality of pads and a plurality of bumps between the second wafer and the multilayer board. 19. The composite structure described in the item of the scope of patent application, wherein the third The connection structure includes a plurality of pads and a plurality of conductive wires. Wherein the plurality of pads are located on the multilayer board, one end of the conductive wire is connected to each of the pads, and the other end == one surface of two chips. Article 20: The composite junction as described in the item of the scope of the patent application further includes a plurality of second chips stacked on each other. 18 1239622 2 1. As the item 11 of the scope of the patent application, it further includes a heat dissipation structure located in the heat dissipation structure. versus The configuration for transmitting a pilot of the first wafer of the composite structure "is produced between the laminate and the electrically insulating layer is a dielectric layer, the heat dissipation of the junction t. 19
TW093136510A 2004-11-26 2004-11-26 Integral structure of chip and multi-layer plate TWI239622B (en)

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