TWI239146B - Phase lock loop circuit having rapid lock frequency - Google Patents

Abstract

The present invention relates to a phase lock loop circuit having rapid lock frequency and its control method. A power-on-reset signal typically used in the general digital system circuit is used to conduct the presetting function onto the phase lock loop circuit so as to make the phase lock loop circuit capable of pre-generating a signal with middle-frequency internally at the initial state to greatly accelerate the required frequency lock action of the phase lock loop circuit. In order to match the reset signal operation of the power-on-reset circuit, an extra 2x1 multiplexer is added in the phase frequency detector (PFD circuit). When the operation is started, an extra logical circuit can be added in the phase frequency detector (PFD circuit) to determine whether the present phase lock loop circuit needs to control the increment signal (UP) or decrement signal (DN). Thus, the required hardware cost can be reduced, and the circuit can be easily assembled by the standard cells without affecting the operation of the entire phase lock loop circuit and changing the sensitivity of the entire phase lock loop circuit.

Description

1239146 发明 Description of the invention: [Technical field to which the invention belongs] The phase-locked loop circuit with fast frequency-locking provided by the present invention and the method for restraining the same are mainly used to generate digital power) or in the field of communication In particular, said that changing the M phase-locked loop circuit can generate a preset signal to the phase-locked loop circuit through a power-on-reset circuit when the power supply voltage has not reached stability. The phase-locked loop circuit can generate an intermediate frequency fixed output frequency by itself in advance, which can greatly reduce the waiting time required for the overall digital circuit system, make the phase-locked loop circuit reach the frequency-locked operation faster, and thus enable the digital system. The circuit enters the normal working mode faster. The present invention can also use a simple digital circuit to judge the phase difference value of the frequency phase detector (pj? D circuit), and control the upward (UP) and downward (DN) signals. The charge and discharge time of the charge pump (CP circuit) to the capacitance of the low-pass filter (lpf circuit) can be lengthened or shortened. [Prior art] Please refer to the first figure: it is a general phase-locked loop circuit architecture diagram. The architecture of a general phase-locked loop circuit can be roughly divided into six parts: Phase Frequency Detector (referred to as PFD circuit), Charge Pump (referred to as CP circuit), and voltage controlled oscillator (v oltage- Controlled Oscillator (abbreviated as VC0 circuit), Low-Pass Filter (abbreviated as LPF circuit), Divide by 2 (1/2) and Divider-by-N. After comparing the phase difference between the external reference input signal (Reference Input) and Divide-by-1239146 N signal through the frequency phase detector (PFD circuit), the relationship between the two is converted into up (up) and down ()) ) The two letters were sent to the charge pump (cp circuit). The charge pump (CP circuit) is mainly used to replace the digital signal of the control circuit (H0 > FD circuit) with a voltage-controlled vibrator. (VCO circuit) Acceptable analog signal operation, the charge pump (cp circuit) is subjected to the control signal of the frequency phase detector (pFD circuit) up (down) and down (DN) to the low-pass The resistance and capacitance of the filter (LpF circuit) are used for charging and discharging. The voltage control oscillator (circuit) uses charge pump (cp circuit) to oscillate relative signals generated by the low-pass filter (LPF circuit). High-frequency output frequency, and then send this high-frequency to the divide-by-2 circuit for 50% duty cycle waveform shaping operation, and finally use divide N (Divider-by-N) to down-frequency To a low frequency signal close to the external reference input signal Phase comparison frequency detector (PFD circuit) for the phase difference, as this has been the operating cycle until the phase difference of both very nearly equal, then PLL circuit locked to complete the operation. In the case of the above-mentioned general phase-locked loop circuit, at the beginning, the frequency phase detector (PFD circuit) generates an external reference input signal (eference Input) and a phase frequency divided by N (Divider-by-N). The difference t number is up (UP) and down (⑽), and the signals of the two are used to control the charge pump to generate a fixed current to the low-pass filter (Low -Pass Filter) capacitor starts to charge and discharge, so that the voltage-controlled oscillator (VC0 circuit) generates a corresponding high-frequency frequency, so we can write the following two equations to represent the work of the entire 1239146 phase-locked loop circuit relationship:

Vc (t) = Ιρ. Φβ / 2π [R + t / C]

Wout (t) = W〇 + KvcoVc (t) where

Vc (t): input voltage of voltage controlled oscillator (vc0 circuit), ίρ: fixed output current of charge pump circuit, R: resistance of low-pass filter (LPF circuit), C : Is the capacitance of the low-pass filter (lpf circuit), ΐ: is the time for charging or discharging the low-pass filter (LPF circuit) for charge pump controlled by the frequency phase detector (pfd circuit) ,

Wout: is the output high frequency frequency of the voltage controlled oscillator (VC0 circuit),

Wo: is the high frequency generated by the voltage controlled oscillator (vco circuit) in the initial state,

Kvco: is the gain value of the voltage controlled oscillator (VC0 circuit). Because the operation of the phase-locked loop circuit is constructed by a recursive theoretical model, the operation of the phase-locked loop circuit from the beginning to the lock can be more completely expressed according to the above two mathematical formulas. When the phase loop circuit completes the frequency-locking operation, the first step is to write the mathematical relationship between the frequency phase detector ⑽), the charge pump (CP), and the low-pass filter (LP F):

Vc (to) = Vc (〇)

Vc (ti) = lp. Φ ^ χ2π (R + ti / C) + Vc (to) Vc (t2) = lp- φ ^ / 2π [R + t2 // C] + Vc (ti) 1239146

Vc (t3) = I P · 0Θ3 / 2 7Γ [R + t 3 / X] + Vc (t2) ： ： ： ： ······

Vc (tn) = I p · 0en / 2 7Γ 〔R + tn / C〕 + Vc (tn−l) Next we can write the complete mathematical formula of the voltage controlled oscillator (VC0 circuit): W〇ut ( to) = W〇ut (0) + Kvc〇 [Vc (to) -〇] Wout (tl) = Wout (t〇) + Kvco (Vc (t〇-Vc (to)) Wout (t2) = Wout ( tl) + Kvco [Vc (t2) ~ Vc (tl)) Wout (t3) = Wout (t2) + Kvco [Vc (t3) -VC (t2)] • Spring

Wout (tn) = Wout (tn-l) + Kvco (Vc (tn)-Vc (tn-l)] Therefore, the frequency-locking operation of a phase-locked loop circuit is successful from the beginning to the final frequency-locking. Only the recursive operation can complete the frequency-locking action. It is stated in a simple relationship diagram, as shown in the second diagram: the relationship between Vc 〇 input voltage and frequency-locking time. In the initial state, the low-pass filter The capacitor voltage in the (LPF circuit) does not have any voltage and electric charge, so it will start from 0 volts, and then the phase-locked loop circuit operates over time to make the charge pump current flow. Will slowly charge the capacitor of the low-pass filter (LPF circuit) and gradually rise, and as shown in the third figure: the characteristic diagram of the voltage controlled oscillator (VCO circuit). It can be seen that when As Vc (t) increases with the number of recursions, the high-frequency output frequency generated by the voltage-controlled oscillator (VC0 circuit) also increases with 1239146. Figure 'can find an important phenomenon, because in the initial state, low || ⑽ Wei Yi) I ⑽ Renhe Long Choi, the input power required VCO circuit MVc slowly begins to rise ◦ V 'before it dog control circuit controls every device vibrator (VCO circuit) the oscillation frequency can be. b In-phase-locked loop circuit towel, _ its _ said that the circuit is a dream by the idea of recursive silk movement, in _ countless: field she shouted

, Adjust the voltage (Zheng Zhenwei, Wei), such as the high-frequency frequency,-until the external reference input creed ference Input) and divide N (D mde-by-N) «is the same, the lock circuit does not complete its action It can be seen that it takes a very long time for the phase-locked loop circuit to complete its operation. However, the general-locked circuit is the clock of the digital system circuit (ClQd〇 来 _, foot contact button electricity_Wei Xiang The output of the loop circuit is very light, so that the digital circuit can enter the normal working state. If the phase-locked loop circuit takes too long, it will «digital system circuits need to wait for the coffee, especially At the beginning, when the power supply voltage supplied by the system circuit has not reached a stable state, the digital system circuit has to wait longer. Generally, in order to shorten the locking time, there are two methods. 1239146 In addition, One method is to use an additional circuit to control the charge pump ([harge Ρ_) so that each step can be larger. Although this method does not require another set of charge pumps (Charge P_), it needs to -An extra number The potential is turned off, but this method has two disadvantages. As far as a circuit designer is concerned, the charge pump (Charge P_) circuit itself is an analog circuit, g) the age and consideration of this design Will be much more than digital circuits_many, at the same time more-analog circuits are more-a problem vulnerable to noise interference, for the entire phase-locked loop circuit, it is equivalent to more-a problem to be considered, while using hardware From the viewpoint of hardware, it seems that the hardware cost of paying an additional set of Charge Pump circuit is too high, because this method is to increase the additional extra without changing the architecture of the phase-locked loop circuit. Auxiliary circuits, so there is no fixed architecture, and the additional 'circuit complexity and frequency-locking operation of the phase-locked loop circuit can be accelerated depending on the designer's circuit design skills. In order to speed up the frequency-locking of general phase-locked loop circuits Action, so you must pay some additional hardware costs in the design to get the benefits. With the phase-locked loop circuit architecture that can be found now, the hardware costs paid are too large. In order to cause excessive hardware costs in exchange expect to achieve the benefits become uneconomic cost-effective. [Summary of the Invention] Therefore, the present invention addresses these shortcomings by designing an additional digital circuit that can speed up the frequency-locking action of the phase-locked loop circuit. p〇w er-On-Reset) # to pre-set the function of the phase-locked loop circuit, 1239146 enables the phase-locked loop circuit to generate a signal with an intermediate frequency in the internal self in advance in the initial state, and After the start of the work, the charge pump (c harge pump) circuit charges the capacitor of the low-pass filter (LPF circuit) each time by the frequency phase detector (PFD circuit) according to the phase-locked loop circuit external reference input signal ( The phase difference between the Reference Input) and N (Divide r by-N) ^ sign is used as the charge and discharge time. In the frequency phase detector (PFD circuit), an additional logic (iogicai) circuit is added to control the upward Up (UP) and down (DN) signals are treated as if the charge pump circuit can charge and discharge the low-pass filter (LPF circuit) valley, such as As a result, the input voltage Vc of the voltage-controlled oscillator (vc0 circuit) can be arbitrarily increased or decreased, which can greatly speed up the frequency-locking action required by the phase-locked loop circuit, and at the same time, the hardware cost it has to pay It is currently the least. The present invention provides a phase-locked loop circuit with fast frequency-locking, which only requires very low additional hardware costs, and only needs to locally modify the general phase-locked loop circuit without affecting the phase-locked loop. The operating characteristics of the circuit are capable of accelerating the frequency-locking action. Before starting the work, if the capacitor of the low-pass choke (LPF circuit) can be charged in advance in the phase-locked loop circuit, the number of repetitions of the frequency-locked operation of the phase-locked loop circuit can be greatly increased. Reduction can greatly speed up the frequency locking of the phase locked loop circuit. After starting work, if the frequency phase detector (pFD circuit) can be controlled to increase (UP) and decrease (down) the chirp signal, it is considered as controllable.

Control the charge pump and discharge time of the low-pass filter (LpF circuit) valley of the electricity pump circuit. In this way, the input voltage Vc of the voltage controlled oscillator (v 1239146 CO) circuit can be increased arbitrarily. Or it is down, so the frequency-locking of the phase-locked loop circuit can be greatly accelerated in this way. The present invention is based on this theory to construct an improved circuit designed. [Embodiment] In order to familiarize the expert with this technology Those skilled in the art can easily understand the design content of the present invention and the functional benefits that can be achieved. Here are a specific embodiment and the detailed description with the drawings as follows: The present invention is a phase locked loop circuit with fast frequency lock and The control method is to use a Power-On-Reset signal often used in general digital system circuits to pre-set the phase-locked loop circuit so that the phase-locked loop circuit can be in the initial state. A signal with an intermediate frequency is generated internally in advance, which can greatly speed up the frequency-locking action required by the phase-locked loop circuit. In general digital system circuits, it is often necessary to perform a Reset operation before the digital circuit starts to ensure that the digital circuit is in the initial state value as our default value, so when the digital system circuit is officially started to operate The time allows the system to enter the correct calculation mode. This type of circuit is called a power-on-reset circuit, and it outputs a reset signal before the power supply voltage of the digital system circuit has stabilized. Set (Reset) # to reset the digital system circuit, wait until the digital system circuit enters a normal working mode to operate, as shown in the fourth figure is a start 4 set (P〇wer—〇 n-Reset) circuit. The fifth figure shows the ^ Weir reset (PGwer_Gn_Reset ^ _ # ^ 1239146 line diagram. The sixth figure shows a circuit diagram of a power-on reset (Power-0n-Reset) circuit. The present invention uses digital system circuits often used Power-On-Reset circuit to reset the phase-locked loop circuit (this set) in advance, so that the voltage-controlled oscillator (% 〇 circuit) of the phase-locked loop circuit starts in the entire digital system circuit There is already an initial voltage when working. Unlike the general phase-locked loop circuit, which starts from 0 volts, its use of a power-on-reset circuit to improve the frequency-locked operation of the phase-locked loop circuit can It is divided into seven steps to explain its operation ... 1. Before the power supply voltage to the digital system circuit has reached stability, the Power-On-Reset circuit will send a Reset signal to enable The digital system circuit performs a Reset action. At this time, this signal is used to control the phase phase detector (Phase Frequency Detector, PFD circuit for short) of the phase-locked loop circuit, so as to increase upward (UP) Downward (DN) output signal is at the same time high (2) Because the frequency phase detector (pfd circuit) is upward (up) and down (DN) at the same time the output is high (HIGH) Signal, so the P-type transistor (PM0S) and N-type transistor (NM0S) at the last stage of the charge pump circuit will be turned on at the same time. 3 · Because of the end of the charge pump circuit The primary output element P-type transistor (PM0S) and N-type transistor (NM0S) are both on, so that the charge pump circuit will output a fixed current to charge the capacitor of the low-pass filter (LPF circuit). 4. Because the capacitive element in the low-pass filter (LPF circuit) is affected by the fixed current charging of the charge pump circuit 13 1239146 Charge (Charge Pump) circuit, the capacitor's power-up surface rises, which in turn makes the voltage-controlled shipboard device ⑽ The circuit) has a slowly rising input voltage, so the voltage-controlled relay (circuit) at this time will oscillate and record a gradually increasing frequency signal output. 5. When the power supply of the digital system circuit reaches a stable state, the power-on-reset circuit will output an unReset signal, so that the digital system circuit enters the normal working mode. 6 · Because the Power-On-Reset circuit sends out an un-Reset # number, the frequency phase detector (pFE) circuit will control this signal to enter the general phase-locked loop circuit It works under the normal operation mode, that is, the frequency phase detector (pFD circuit) is incremented upwards by OJP) and downwards. ⑽) Money is no longer-it is maintained at a high level (HIGH) signal level. 7 · Because of the signal control of the power-on-peset circuit reset (set by CD), the capacitor voltage of the low-pass filter (LpF circuit) is already close to that of the initial operation. The voltage level of 1 / 2VDD, instead of the ordinary phase-locked loop circuit, is an initial voltage of 0 volts. At the same time, the voltage-controlled oscillator (vco circuit) has also generated a signal with an intermediate frequency by itself. At this time, the phase-locked The loop circuit begins to function normally. Please refer to the seventh figure. It is a characteristic diagram of the phase-locked loop circuit of the present invention plus a power-on-reset circuit. From this figure, it can be clearly seen that the general lock circuit is because the capacitor in the 1239146 low-pass filter (LPF circuit) does not have any initial voltage in the initial state, so the capacitor voltage must be started from 0 volts. Rise, and after using the characteristics of a power-on-reset circuit, when the phase-locked loop circuit starts to work, because the capacitor of the low-pass filter (LPF circuit) is charged in advance, so When the phase-locked loop circuit starts to work, the capacitor voltage of the low-pass wave filter (LPF circuit) will have an initial value close to 1/2 VDD. At the same time, the voltage-controlled oscillator (VC0 circuit) will also generate a stable intermediate frequency. Frequency output, so after the phase-locked loop circuit enters the normal working mode, 'if the external reference input signal (Reference I nput) of the phase-locked loop circuit is higher than the frequency signal divided by N (Divide-by-N), the frequency The phase detector (PFD circuit) will set the UP (up) signal to HIGH (lower) ⑽) signal to low (L0w). At this time, the Charge Pump circuit will Low The filter (lpf circuit) performs a charging action so that the Vc voltage will rise from approximately 1/2 VDD, and on the contrary, if the external reference input signal (Reference Input) signal is lower than N (Divide-by-N) Signal frequency, the frequency and phase detector (pro circuit) will set the UP signal to a low potential (L0w), the DN signal to a high potential (HIGH), and a charge pump (Charge). The p ump) circuit will cause the capacitance of the low-pass filter (LPF circuit) to discharge toward the charge pump circuit, so the Vc voltage will drop from approximately 1/2 VDD voltage, regardless of the voltage-controlled oscillator ( vc〇 circuit) Whether the input voltage Vc will rise or fall, the locking time required by the phase-locked loop circuit is greatly reduced, so that the digital system circuit can enter the normal working mode faster to reduce Unnecessarily wait 15 1239146 for time. Please refer to the following, which shows: This is an improved fast frequency-locked phase-locked loop circuit. Qian Caiyi added a wire reset (p0w eMMeset) Wei _ Thin Road Wei Chou In order to cooperate with the Jing signal of the start reset (P-Gn-Reset) circuit, it is necessary to change the phase lock. The frequency and phase detector of the loop circuit (Qing circuit), so that the two are closely combined. Please refer to the ninth figure: the present invention is to cooperate with the start reset (p

On-Reset) circuit to partially modified fresh phase detector (circuit). Among them, in the part of modifying the frequency phase detector (circuit), we only need to add an additional 2X1 poly jade to the original _rate phase detector (PFD circuit), so that the required circuit requirements can be made, so the required The extra hardware cost can be said to be very small, _ only needs to pay-a low-cost 2XI more: qh, instead of-a group of charge pump gamma pump circuit or additional control circuit, and because it must be modified The digital circuit and the additional circuit to be used are digital circuits, so the influence on the overall phase-locked loop circuit's circuit sensitivity can be said to be minimal, and the characteristics of the phase-locked loop circuit have not been modified. Please refer to the tenth figure: the simulation result of the phase-locked loop circuit of the present invention and the power-on-reset circuit. The result proves that after using the characteristics of the start-reset (Reset) circuit in the phase-locked loop circuit of the present invention, the frequency lock time can be greatly reduced. The present invention relates to a phase-locked loop circuit with fast frequency-locking and a control method thereof. It uses a signal of a control frequency phase detector (PFD circuit) to forward 1239146 both up (up) and down (DN). , So that the input voltage Vc of each voltage-controlled oscillator (VCO circuit) can be greatly increased or decreased. Please refer to FIG. 11 for a block diagram of an improved phase-locked loop circuit designed by the present invention. It does not change or modify the analog circuit in the phase-locked loop circuit. Instead, it starts from the original digital circuit to make partial modifications. Because the circuit sensitivity of the digital circuit is much smaller than that of the analog circuit, the circuit design can be greatly reduced. At the same time, the verification and design of digital circuits are much faster and simpler than analog circuits, so the time it takes to design a circuit can be accelerated. The method adopted by the present invention is a frequency phase detector (PFD circuit) for digital circuits. Make partial modifications and keep the rest unchanged, so you can reduce the number of parts that need to be modified. Please see the twelfth ®: a typical frequency phase detector (PFD circuit). This frequency phase detector (pFD circuit) refers to the phase-locked loop circuit architecture of the 1999 IEEE Solid-State Journal Paper. From this architecture, it can be seen that the constituent circuits of the frequency phase detector (pFD circuit) are all digital. Logic circuit, therefore, the present invention makes it easy to modify the local phase of the frequency phase detection circuit (H 且 circuit) without causing the effect of the frequency phase detector (PFD circuit). See Figure 12 for a block diagram of a modified frequency phase detector (PFD circuit) of the present invention. As shown in Fig. 14, the present invention is a frequency phase detector (pFD circuit) which is partially modified to speed up the phase locked loop circuit. The present invention additionally adds a simple logical circuit and an OR gate to the frequency phase detector (pFD circuit), and uses this logical circuit to determine whether the current phase-locked loop circuit needs 17 1239146 to control Up (up) and down (⑽) signals, so you only need to add an additional logical t and an OR (ask, so the hardware cost to pay is very small, and because it It is a digital circuit, so it can be easily combined by standard cells, and it will not affect the operation of the overall phase-locked loop circuit, and change the recording of the overall phase-locked loop circuit. This improvement The circuit is much simpler in terms of hardware cost and difficulty of circuit design than the additional multi-use charge ρ_ circuit. It is easy to see that the circuit's anti-noise tolerance when π is also Much better than using an additional charge pump circuit. The present invention utilizes simple digital wire control and phase difference of the phase-based H (PFD circuit). If the phase difference value of its frequency phase detector (PFD circuit) is too large, then the signals of upward (UP) and downward (DN) are controlled, so that the charge pump circuit (Charge P_) circuit to the low-pass filter ⑽ The charging and discharging time of the capacitor can be lengthened or shortened. Please refer to Figure 15 for a block diagram of the simple digital logic judgment circuit of the present invention. Unlike a normal phase-locked loop circuit, a frequency phase detector (PFD circuit) simply generates a phase difference between an external reference input signal (Reference I 叩 ut) and a divide-by-N (Divider-by-N) signal. It uses a simple digital judgment circuit to improve the operation of the frequency-locked operation of the phase-locked loop circuit. It can be divided into two recursive loop steps to explain its working situation: 1. If at the beginning, the external reference input signal (Reference Input) and division by N (Divider-by-N) The phase difference between the two signals is greater than the critical value of 1239146, the simple digital judgment circuit starts to operate, and then controls the frequency phase detector (PFD circuit) to increase (up) and decrease (M) signal. 2 · If the phase-locked loop circuit works until the phase difference between the external reference input signal (Referen ce Input) and the divide-by-N (Divider-by-N) signal is less than the critical value, it means that the phase-locked loop circuit is close to the frequency-locked When it is activated, the simple digital judgment circuit stops moving. At this time, the frequency and phase detector (PFD circuit) enters the normal operation mode, that is, the frequency and phase detector (PFD circuit) simply compares the external reference input signal (Reference I叩 ut) and Divider-by-N signals. Please refer to the sixteenth riding instruction: the efficiency ratio of the improved phase-locked loop circuit and the general phase-locked loop circuit of the present invention is simple. It can be seen that the frequency lock time of the improved phase-locked loop circuit is much shorter than that of the ordinary phase-locked loop circuit. Please refer to the seventeenth chapter: The comparison diagram of the analog phase-locked loop circuit and the phase-locked loop circuit. Therefore, it can be proved that the improved circuit of the present invention is much faster than the general phase-locked loop circuit in terms of lock operation, and that the additional circuit has a hardware requirement cost for the overall phase-locked loop circuit. _Much better than the current phase-locked loop circuit that speeds up the frequency-locked operation of the phase-locked loop circuit. The advantages of the present invention: 1. Utilize the start reset (powebuonRes) feature of the digital system circuit to promote the phase-locked loop circuit to speed up the frequency-locking operation. The additional hardware cost of only 19 1239146 is very small. The required frequency-locking time. The part of the circuit will not affect a small part of the overall circuit, so it is required. 2 · It can significantly shorten the phase-locked loop circuit. 3. · The circuit characteristics of the phase-locked loop that need to be modified. Simple explanation] The first ® •• is a general phase-locked loop circuit architecture diagram. The second graph: the relationship between the voltage of the system and the voltage-controlled oscillator (vco circuit) and the frequency lock time.

The third figure is a characteristic diagram of a voltage controlled oscillator (vc0 circuit). The fourth figure is a schematic diagram of a start reset (power_n_Reset) circuit. The fifth figure is a characteristic curve diagram of a power-on-reset circuit. The sixth figure is a circuit diagram of a power-on-reset circuit. The seventh diagram is a characteristic diagram of the phase-locked loop circuit of the present invention plus a poWer-On-Reset circuit.

FIG. 8 is a block diagram of a phase locked loop circuit of the improved fast frequency lock of the present invention. Ninth figure: The frequency phase detector (PFD circuit) of the present invention is partially modified to match the Power-On-Reset circuit. 0 Tenth figure: The phase-locked loop circuit of the present invention plus the start-up reset Set (Power -On-Reset) circuit simulation results. Fig. 11 is a block diagram of the improved phase-locked loop circuit 20 1239146 designed by the present invention. Figure 12: A typical frequency phase detector (PFD circuit). The thirteenth figure is a block diagram of a modified frequency phase detector (PFD circuit) of the present invention. Fig. 14 is a frequency phase detector (PFD circuit) of the present invention which is partially modified to speed up the phase locked loop circuit. Fig. 15 is a block diagram of a simple digital logic judgment circuit according to the present invention. Fig. 16 is a comparison diagram of the benefits of the improved phase-locked loop circuit and the general phase-locked loop circuit of the present invention. Fig. 17 is a simulation comparison diagram of the improved phase locked loop circuit and the general phase locked loop circuit of the present invention.

twenty one

Claims (1)

Dian Lin page, patent application scope: 1 · A phase locked loop circuit with fast frequency locking, including: Frequency phase detector, used to detect whether the phase and frequency output by the frequency divider are consistent; Charge pump, It is used to convert the digital signal of the frequency phase detector into an analog signal acceptable to the voltage controlled oscillator. The low-pass filter converts the signal sent by the phase detector to the charge pump into an equivalent low-frequency voltage value. Filter out high-frequency parts generated by the phase detector Voltage-controlled oscillator, the output frequency will be increased or decreased by the output voltage value of the low-pass filter as a proportional increase or decrease; the frequency divider will reduce the high-frequency signal to a low-frequency signal close to the input reference input; Power-on reset circuit (p〇wer_Qn-Reset), and adding a logical (Logical) circuit, or (〇R) gate, and a 2 X 1 multiple Worker. 2 · A method for controlling a phase-locked loop circuit with fast frequency-locking, wherein a power-on reset circuit (power_Qn_Reset) is used to perform a reset operation on the phase-locked circuit in advance, which tends to control the voltage of the phase-locked circuit The oscillating circuit already has an initial voltage when the entire digital system circuit starts to work. 3. The method for controlling a phase-locked loop circuit with fast frequency locking as described in item 2 of the scope of patent application, wherein when the power supply voltage to the digital system circuit has not reached stability, the power supply resets the circuit (p_p〇n- Reset) will send a Reset signal to make the digital system circuit 22 perform ii (Reset) operation. At this time, use this signal to control the phase detection circuit of the phase-locked circuit and use up The output signal of the downward and downward (DN) signals are both HIGH. At this time, the last-stage output element of the charge pump circuit (ChargePump), the p-type chip (pM0s) and the N-type chip (NM0s) will be simultaneously. Turn on, so that the charge pump circuit (ChargePump) will output-a fixed current to charge the capacitor of the low-pass filter circuit (LpF_), so the voltage on the capacitor will rise accordingly, which will make the voltage-controlled vibrating circuit slower. The input voltage slowly rises, so the voltage-controlled vibration surplus circuit will start to oscillate output-a gradually increasing frequency signal input & φ, when the power supply voltage of the digital system circuit reaches a stable state, the power supply starts The reset circuit (P〇wer-〇n-Reset) will output a "No Reset" message to make the digital system circuit enter the normal jade-side type, because the Power-On-Reset (un- The signal of “Reset” is continued. The PFD will be controlled by this signal and enter into the normal operation mode of the phase-locked circuit, that is, the phase detection power_up (UP) and down ( DN) signal is not-it is maintained at a high level (HIGH) signal level, because it is controlled by the electrical reset circuit (P_M) n_Reset) Reset (Reset) signal control, making the low-pass chirp circuit (LPF) ) The capacitor voltage has a voltage level close to k1 / 2vdd during initial operation, instead of-the phase-locked circuit is an initial voltage of 0 volts. At the same time, the voltage-controlled oscillation circuit has also generated itself- A signal with an intermediate frequency, the phase-locked circuit begins to operate normally. 4 kinds of phase-locked loop circuit control methods with fast frequency-locking, 23 It uses a simple digital circuit to control and judge the phase difference value of the phase detector circuit. If the phase difference value of the phase detection circuit is too large, it controls the signal of increasing (UP) and decreasing (DN) downward so that The charge pump and discharge circuit (Charge Pump) can charge or discharge the capacitor of the low-pass filter circuit (lpf) for a longer or shorter time. 5. The method for controlling a phase-locked loop circuit with fast frequency locking as described in item 4 of the scope of patent application, wherein if the phase difference between the external input reference signal and the frequency-divided signal is greater than a critical value at the beginning, then The simple digital judgment circuit starts to operate, and then controls the phase detection circuit to increase (UP) and decrease (DN) signals. If the phase lock circuit works to the external input signal, the input reference signal and the divided signal The phase difference is less than the critical value, which means that the phase-locked circuit is close to the frequency-locked operation. Then the simple digital judgment circuit stops moving. At this time, the phase detection circuit enters the normal operation mode, that is, the phase detection circuit is only a simple comparison. The phase difference between the input reference signal and the divided signal. twenty four