TWI239070B - Manufacture method of semiconductor device, semiconductor wafer, and semiconductor device - Google Patents

Abstract

The purpose of the present invention is to provide a manufacturing method of semiconductor device having high yield and the capability of cutting the scribe area. The manufacturing method of semiconductor device contains the followings: (a) preparing the semiconductor wafer containing plural-chip area formed with semiconductor devices, the scribe area for separating plural-chip area and containing the scribe area for cutting off, and the trench formation area formed at outside of the scribe area compared with inside of the scribe area to surround each chip area; (b) disposing multi-layered wiring structure and virtual wiring alternately formed with interlayer insulation film and the wiring layer on the top of semiconductor device; (c) forming the cap layer that wraps the multi-layered wiring structure and contains the passivation layer; and (d) forming the individual trench to respectively surround plural-chip area by at least penetrating the passivation layer from the upper side in the trench formation area.

Description

1239070 发明 Description of invention:

TECHNICAL FIELD The invention relates to a method for manufacturing a semiconductor device, a semiconductor wafer 5 and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with a multilayer wiring structure, a semiconductor wafer, and a semiconductor device. Device. I: Prior Art 3 Background of the Invention 10 In the manufacture of semiconductor integrated circuit devices, most wafer areas are divided on the semiconductor wafer by scribe areas. A plurality of semiconductor elements are formed in each wafer area, and a multilayer wiring structure in which a wiring layer and an interlayer insulating film are alternately stacked is formed thereon. After forming a semiconductor integrated circuit structure in each wafer area, dicing is performed in the dicing area to separate each wafer. The dicing is performed by a dicing saw 15 that cuts the entire length of the semiconductor wafer by chipping. The dicing field is not used as a circuit field. In the past, although alignment marks and test device groups were formed, other fields were cut with the semiconductor wafer surface exposed. The cross-section of the semiconductor wafer that has been separated by splitting has an uneven state with a burr 20 shape. Japanese Laid-Open Patent Publication No. 4-282852 proposes a method of leaving a narrow width insulating layer on both sides of the center line in the scribe field and cutting in the area between the insulating layers. It is also explained that the insulating layer is harder than the semiconductor, and it can prevent the unevenness of the cut surface from expanding beyond the scribe area and expanding inside the wafer. 1239070 When the semiconductor wafer is cut with a dicing knife, the top insulation film on the semiconductor wafer will be rolled into the dicing knife and peeled off, and the wiring and electrodes will be partially exposed, causing short circuits, damage, and corrosion. Japanese Patent Application Laid-Open No. 9-199449 proposes a method for forming a peeling prevention groove on the top insulating layer. 5 帛 22 relationship is shown in Japanese Unexamined Patent Publication No. 9] 99449 _ the structure of the stop ditch. A semiconductor element is formed on the surface of the silicon substrate 101, and an interlayer insulating film 102 is formed thereon. Wiring is formed on the interlayer insulating film 102, and an interlayer insulating film 104 is formed thereon. In addition, a bonding pad 113 connected to the wiring u0 is formed. The upper layer is formed with an insulating layer 105 and a polycrystalline silicon layer formed by a laminate of an oxygen-cut layer and a 10-nitride residual layer. The imine protective layer 107 serves as a top insulating layer. When the etching to penetrate the polyimide protective layer 107 and the insulating layer 105 is performed to expose the surface of the bonding pad 113, the peeling prevention of the through polyimide protective layer 107 and the insulating layer 105 is also formed along the periphery of the wafer. Ditch 108. At the time of dicing, even if the polyimide protective layer 107 and the insulating layer 105 are wound into the dicing blade on the wafer end surface, 15 because the peeling prevention groove 108 exists, the peeling will stop at the peeling prevention groove 108. In order to improve the integration degree of semiconductor integrated circuit devices and speed up the operation speed, semiconductor components as constituent elements have also gradually been refined. At the same time of miniaturization, the exposure procedure requires a lower resolution than the South, the aperture ratio increases, and the focal depth decreases. For imaging at a shallow focal depth, the substrate of the photoresist layer should be flat. 20 Therefore, the industry uses chemical mechanical polishing (CMP) and other planarization processes. Japanese Patent Application Laid-Open No. 10-335333 discloses integrated circuits using w or A1 wiring. It is pointed out that even after the wiring is formed, even if an interlayer insulating film is formed and CMP is performed, the surface cannot be completely flattened. , The wiring interval must be within a certain range up to 2 times. It is not limited to the 1239070 area of the wafer collar. In the scribe area, it is also possible to form an insulating layer with a flat surface on the entire surface of the wafer by configuring dummy wiring. FIG. 22B shows five examples of the structure of a semiconductor device in which dummy wirings are comprehensively arranged in a wafer field and a dicing field disclosed in Japanese Patent Application Laid-Open No. 10-335333. In the figure, the electrode pad (pad) and peripheral circuit area b are on the right, and the scribe area A is on the left. The surface of the silicon substrate 101 is formed with a device separation region 103 by a shallow trench process technology (ST1). A gate insulating film, a gate, and a MOS transistor are formed on the active area of the silicon substrate. At the same time, a wiring 106 is also formed on the element separation area 103 using the same material as the gate electrode. In addition, an interlayer insulating film 109 is formed to cover the gate. A wiring layer including the wiring 110 and the dummy wiring 111 is formed on the interlayer insulating film 109. The dummy wiring 111 is not limited to the electrode pad and the peripheral circuit area B, and is also disposed in the scribe area A. The wirings 110 and 111 are covered with the interlayer insulating film 112, and the surface of 15 is flattened. Similarly, a wiring 114 and a dummy wiring 115 are formed on the interlayer insulating film 112, and are covered with the interlayer insulating film 116. The surface of the interlayer insulating film 116 is flattened, and wirings 117 and dummy wirings 118 are formed thereon, and the interlayer insulating films 1 and 9 are covered. Wiring 120 and dummy wiring 121 are formed on the interlayer insulating film 119, and are covered with the interlayer insulating film 122. 20 „An interlayer insulating film 122 is formed with a top wiring layer including a bonding pad 113 and a wiring 123, and is covered with a capping layer composed of an insulating layer 124 and a passivating layer 125. The surface of the bonding pad 113 Then, it is exposed by selectively etching the passivation layer 125 and the insulating layer 124. With the above structure, it has been shown that it is possible to achieve a complete flatness of the wafer's full flatness. 1239070. In the scribe field, there is a top wiring layer covered by a cap layer. Structure. With the miniaturization of the components, the density of the wiring also increases, which necessitates the need to reduce the cross-sectional area. Once the resistance of the wiring increases due to the reduction of the wearing area, the operating speed of the semiconductor integrated circuit device will also increase. Decrease. In order to suppress the increase in wiring resistance, copper wiring is used instead of Lu wiring. Copper layers cannot be formed like aluminum, using photoresist masks to form patterns by reactive ion etching (RIE) to the south. Therefore, the copper wiring is formed by the damascene process. That is, a groove or a hole-like recess is formed in the insulating layer, and the recess is filled with a copper layer, and then the insulation is removed by chemical mechanical polishing (CMp). 10 useless copper layer and leave wiring in the recess. CMP can set conditions to polish the copper wiring layer. If the density of the wiring can be separated, it can be polished in the area where the wiring is consistent and the degree is relatively high to produce an insulating layer. Erosion of the surface depression. That is, depending on the density of the wiring, a step difference will occur. The step difference on the surface of the semiconductor wafer will cause the 15 process range of the photolithography program to be reduced. Also, in the wiring layer When performing CMP, it will be difficult to remove the wiring layer on the recessed portion, resulting in Cu residue. To prevent erosion during CMP, dummy wiring can be arranged to uniformize the wiring density. The dummy wiring is formed of the same material as the wiring, but Pattern without wiring function. The dummy wiring to prevent erosion during CMP does not have the function of transmitting electrical 20 signals. It is formed to make the polishing speed of CMP uniform and the same material and wiring pattern. When the wiring is double-embedded In the case of dual damascene wiring, the dummy wiring does not need to have the same structure, but can also be a single damascene structure. Another is chemical vapor deposition (CVD) In procedures such as etching, if the density of the object's pattern 1239070 differs sparsely, it may also impair the stability of the process. At this time, dummy wiring can also be used to ensure the uniformity of processing. The dummy wiring only needs to reach the processing The uniformity is ensured without extending the setting. Generally, the dispersed pattern is adopted to avoid accidentally increasing the parasitic capacitance of the wiring and restricting the freedom of design. Each of the 5 types of dummy wiring can be collectively referred to as a dummy pattern. By using dummy wiring, it can prevent intrusion, make the surface after CMP non-tantalizing, and increase the process range of the photo-etching process. It is also possible to prevent the wiring layer of the subsequent damascene type wiring formation process from remaining. With the increase of LSI speed, the influence of the delay of the wiring layer on the circuit operation has gradually increased. The additional capacitance requirements of the wiring layer are reduced, and the interlayer insulation film is gradually adopting a low dielectric constant (10w-k) material with a significantly lower dielectric constant than silicon oxide. At the same time as the LSI has become more integrated, the wiring has gradually become multilayered. Multi-layer wiring also has different requirements depending on the different layers. Interlayer insulation films with low dielectric constant are mainly used for lower-layer wiring. Low dielectric constant materials generally have low physical strength. 15 Therefore, once an interlayer insulating film with a low dielectric constant is formed, the interlayer strength is reduced. In the cutting process of cutting a wafer from a wafer, interlayer peeling will occur at the interface of the lower interlayer insulating film due to the impact during dicing. And because of its diffusion into the chip, the problem of yield reduction occurs. In particular, the corners of the wafer are subject to peeling because they are affected by the two cutting processes of vertical cutting and horizontal cutting. 20 Normally, there is stress in the cover. In the dicing field of the conventional structure, the cover layer is removed by removing the entire cutting field, thereby suppressing the peeling of the cover layer (crack diffusion inside the cracked wafer. The adhesion of the interlayer insulating film of the low dielectric constant material is also not good) 1239070 [Summary of the invention] The object of the present invention is to provide a method for manufacturing a semiconductor device with a high yield and a dicing field. 5 The present invention Another object is to provide a method for manufacturing a semiconductor device, which has been expanded to a process range limited by a dicing process. Another object of the present invention is to provide a semiconductor wafer that can be manufactured with a larger process range and a higher yield. Semiconductor device. Another object of the present invention is to provide a method, a semiconductor wafer, or a semiconductor device manufacturing method capable of suppressing the adverse effects caused by using the dummy wiring 10 and suppressing the peeling of the insulating layer in the dicing process. According to a first aspect, a method for manufacturing a semiconductor device may be provided, including the following procedures: (a) standard A 15-chip area including a plurality of wafer areas in which semiconductor elements are formed and a dicing area for cutting which separates the plurality of wafer areas, and a groove surrounding each wafer area is defined on the outer side of the dicing area than in the scribe area. Forming semiconductor wafers in the field; (b) arranging a multilayer wiring structure having an interlayer insulating film and a wiring layer alternately formed on the aforementioned semiconductor wafer, and arranging dummy wiring in the area where the wiring layer has a small wiring density; (c) ) Forming a capping layer covering the multilayer wiring structure and including a passivation layer; and (d) forming at least the passivation layer through the passivation layer from above in the trench 20 formation area to form individual trenches respectively surrounding the plurality of wafer areas. According to another aspect of the present invention, there can be provided a semiconductor wafer including a semiconductor wafer, a plurality of wafer fields including a semiconductor element formed thereon, and a dicing field that separates the plurality of wafer fields and includes a dicing field for cutting. And at 10 1239070, a groove shape surrounding each wafer area is defined outside the cutting area in the dicing area. Into a field; a multilayer wiring structure, which is formed on the above-mentioned semiconductor wafer and has an interlayer insulating film and a wiring layer alternately stacked, and includes a dummy wiring configured in a field having a low wiring density in the wiring layer; a cover layer, a covering The multilayer wiring 5 is formed by a structure including a passivation layer; and a trench is formed in the trench formation field by penetrating at least the passivation layer from above and can surround each of the plurality of wafer fields. In another aspect, a semiconductor device may be provided, including: a semiconductor substrate, a wafer area including a semiconductor element formed thereon, and a scribe area around the aforementioned wafer area, and a region surrounding each wafer area is divided within the aforementioned scribe area. Trench formation area; multi-layer wiring structure, which is formed on the above-mentioned semiconductor wafer and has interlayer insulating films and wiring layers alternately stacked, and includes dummy wirings arranged in areas where the wiring layer has a small wiring density; cover layers, packages It is formed by covering the above-mentioned multilayer wiring structure and includes a passivation layer; and the trench is based on the above 15 Forming at least from above the field through the passivation layer are formed. The wiring layers other than the top wiring layer should be low-resistance copper wiring. In multilayer wiring, the lower interlayer insulating film should be formed of a low dielectric constant material. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view of a semiconductor wafer according to an embodiment of the present invention. 2A to 2E are cross-sectional views showing main procedures of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3A to 31 are sectional views showing the procedures for forming the wirings of Figure 2A in more detail. 11 1239070 Figures 4A and 4B are cross-sectional views showing main procedures of a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 5 is a schematic plan view of a semiconductor wafer according to another embodiment of the present invention. 6A and 6B are cross-sectional views showing main procedures of a method for manufacturing a semiconductor device according to the embodiment shown in FIG. 5. 7A and 7B are cross-sectional views showing main procedures of another method for manufacturing a semiconductor device according to the embodiment shown in FIG. 5; 8A and 8B are cross-sectional views showing main procedures of another method for manufacturing a semiconductor device according to the embodiment shown in FIG. 5; 10 FIG. 9 is a schematic plan view of a semiconductor wafer according to another embodiment of the present invention. Figures 10A and 10B are cross-sectional views showing main procedures of other manufacturing methods of the semiconductor device of the embodiment shown in Figure 9; FIG. 11 is a schematic plan view of a semiconductor wafer according to another embodiment of the present invention. Figures 12A and 12B are cross-sectional views showing the main procedures of the other manufacturing methods of the semiconductor device of the embodiment shown in Figure 11; Fig. 13 is a cross-sectional view schematically showing the structure of a first embodiment of a semiconductor device having 10 layers of wiring. Fig. 14 is a sectional view schematically showing the configuration of a modification of the first embodiment of the semiconductor device having 10 layers of wiring. 20 Fig. 15 is a cross-sectional view schematically showing the structure of a second embodiment of a semiconductor device having 10 layers of wiring. Fig. 16 is a sectional view schematically showing the configuration of a modification of the second embodiment of the semiconductor device having 10 layers of wiring. Fig. 17 is a cross-sectional view schematically showing the structure of a 12th embodiment of a third embodiment of a semiconductor device having 10 layers of wiring. Fig. 18 is a sectional view schematically showing the configuration of a fourth embodiment of a semiconductor device having 10 layers of wiring. 19A to 19E are sectional views showing a procedure for forming a metal damascene wiring of 5 in the organic insulating layer shown in FIG. 5. Figures 20A and 20B are micrographs of the top surface of the wafer after cutting the wafer based on the structure shown in Figure 17.

Figures 21A to 21E are schematic diagrams showing modification examples of the shape of the groove formed in the groove formation area. 10 Figures 22A and 22B are schematic cross-sectional views showing a structure of a peeling prevention groove when a semiconductor wafer is cut by a conventional technique, and a structure of a semiconductor device having a dummy wiring. Fig. 23 is a cross-sectional view showing the results of a review conducted by the present inventor on a conventional technique. 15 Figure 24 is a schematic representation of the results of other reviews

Sectional view. Fig. 25 is a schematic sectional view showing a phenomenon found by the present inventors. LEmbodiment Mode 3 20 Detailed Description of the Preferred Embodiments Before describing the embodiments of the present invention, the review results obtained by the present inventors will be described first. As shown in the structure shown in FIG. 22B, if dummy wiring is also arranged in the dicing area, the overall flatness of the wafer can be easily ensured. The dicing area is the same as that of the electrode pads and peripheral circuits. The 1239070 areas are all formed with dummy wiring and are covered by a cap layer including a passivation layer 125. Fig. 23 is a cross-sectional view schematically showing the configuration of a semiconductor device actually used in the review conducted by the inventors. A semiconductor element is formed on the semiconductor substrate 10, and is covered with an insulating layer 21. Above it, multilayer wiring is formed. The buildup of the multilayer wiring insulation layer includes an interlayer insulating film IL1, an etch stopper and copper diffusion preventing layer ES2, an interlayer insulating film IL2, an etching stop and copper diffusion preventing layer ES3, an interlayer insulating film IL3, and an etching stopper. A copper diffusion preventing layer ES4, an interlayer insulating film IL14, a top insulating layer 18, and a passivation layer! ≫ 10 The insulation build-up layer of the etching stop layer Esi and the interlayer insulating film m is filled with a first metal (copper) wiring layer W1 having a dummy wiring, a second metal (copper) wiring layer W2, and a third metal (copper) wiring layer. W3. A top-level wiring layer including an aluminum layer is formed on the third metal wiring layer W3 through a via portion. The top wiring layer does not have a dummy wiring, it is partly an electrode pad P, and the other parts constitute a sealing SR. The top 15 layers are covered with a cover layer including a top layer, an insulation layer, and a purification layer ^. In addition, the openings penetrating the passivation layer ps and the top insulating layer is exposed to expose the electrode pad P0. In the structure of the drawing, the semiconductor wafer includes a plurality of wafer areas cn, c2, and the dicing area can be divided in the meantime. By cutting seven areas in the scribing area sc, the wafers ci and C2 can be separated. Because there is stress in the cover layer, once it is in the state of the cover layer; if it is cut underneath, it is easy to cause hair at the interface of the insulation layer due to the impact of cutting. At the time of the impact, the top insulating layer 18 of the cover layer of the wafer C1 is separated and peeled off from the interface between the top insulating layer 18 and the interlayer insulating film 4 and expands to the inside of the wafer. And, it is not limited to the interface of the cover layer, between the layers below 14 1239070! Peel membrane interface also peeled. The peeling is not limited to the periphery of the wafer, and it is easy to expand into the circuit field. Once the peel spreads to the inside of the wafer, the wafer becomes defective and the yield is reduced. If a low " Igwk " material is used for the interlayer insulating film of the multilayer wiring, the interface will be easily peeled. The purification layer PS is formed of nitride oxynitride or oxynitride. In the internal sequence, cutting the passivation layer is considered to be the cause of the peeling due to the stress concentrated on the cut surface.

Therefore, the method of removing at least the passivation layer pS in the scribe area before the cutting process has been reviewed. If the passivation layer PS on the scribe area is removed, it is approved to increase the distance between the cut surface and the passivation layer, and alleviate the stress on the cut surface. When the electrode is punched, the capping layer including the passivation film and the insulating layer underneath can be performed. At the same time that the electrode engraving is performed, if the engraving is performed in the scribe area, the cover layer containing the passivation layer can be removed. ft Figure 24 is a schematic diagram of the 垾 15 pad opening process of the semiconductor wafer with the structure shown in Figure 23. It is also intended to etch the scriber between the seal ring SR of the wafer ci and C2 or the cover layer of SC. A cross-sectional view of a semiconductor wafer in a state. The semiconductor wafer has the same structure as that in FIG. 23, and a top wiring layer including an electrode pad p and a top ring sr is formed, and a top insulating layer IS and a passivation layer are covered, and then formed on a purification layer PS. In the electrode pad p and dicing area 8 (: photoresist pattern pR of openings. 20) Secondly, the passivation layer PS and the top insulating layer IS are engraved with dry etching using a plasma to expose the electrode 塾 p. When The top insulating layer IS is exposed on the receiving side, and the top insulating layer iS is also engraved by the last name to expose the fourth interlayer insulating film IL4 under it. At this time, the over-etching (〇ver etching), In the domain of scribe 1, the fourth interlayer insulating film IL4, the fourth etched 15 1239070 terminating layer ES4, and the third interlayer insulating film IL3 under the top insulating layer is also etched. Thus, the third interlayer insulating film was originally filled The dummy wiring in the film IL3 is exposed in the plasma, and is scattered with the etching of the insulating layer. The dummy wiring scattered in the plasma will be attached to the surface of the semiconductor wafer, even if it is cleaned with pure water. 5 As mentioned above, once a dummy is configured in the scribe area Wire, and cut in the state covered by the insulating layer and the passivation layer, peeling will occur between the insulating layers. If dry etching is performed to remove the cap layer, the dummy wiring will be scattered due to excessive etching. 10 copies The inventors have discovered that when a through-cover layer is formed and a trench having a limited width is surrounded in the dicing field without removing the comprehensive cover in the dicing field, the intrusion from the cut surface during cutting will Stop in the vicinity of the trench. Figure 25 shows the above phenomenon in outline. The structure of the semiconductor device is the same as that of Figures 23 and 24. It has multilayer wiring with 15 dummy wirings arranged in the wafer area C and the scribe area SC. Although the top insulation layer IS has been flattened, the same phenomenon is also found when it is not flattened. In addition to removing the cover layers PS and IS on the electrode pad P to expose the electrode pad, it is also used to mark the area surrounding the wafer C. The outer side of the chip area SC is removed in a circle to form a groove G. In the drawing, it can be found that when the right side is cut by cutting and peeling occurs from the wafer end 20, the outer side of the wafer unit The upper part of the peeled part is peeled off as shown in Z, and the peeling can stop at the trench. If a deeper trench is formed than peeling, it may be necessary to prevent the diffusion of the peel by the trench, but the formation of a shallow trench also The peeling can be stopped. The reason why the deeper peeling can be stopped by shallow grooves, or it can be deduced as 16 239 0007. The passivation layer PS has tensile stress inside, and it is on the inner wall portion Z1 outside the groove g. As shown by the arrow, the stress expanding toward the inside can be accumulated. If the outer side Z2 of the bottom surface of the groove G is used as a fulcrum, the stress facing inward at the point Z1 will squeeze the lower layer from the fulcrum Z2 outward. Once If the peeling of the CL occurs so that the bond between the upper and lower layers does not exist, the force toward the outside will be concentrated on the upper layer where it is peeled off. Therefore, the splitting portion CL will be split toward the fulcrum Z2. Once the stress is relieved by the splitting, the peeling stops. By using this phenomenon ', it is possible to prevent the peeling from spreading to the inside of the wafer area while the cover layer remains in the dicing area. The same applies when a dummy wiring is formed in the dicing area, and it is only necessary to avoid the scattering of the dummy wiring when a groove having a limited width is formed. Although the trench should be at least deeper than the passivation layer, and more practically speaking, it should be deeper than the capping layer, it need not be deep to the depth where peeling may occur. Hereinafter, more specific embodiments of the present invention will be described. FIG. 1 is a schematic view showing a semiconductor wafer according to an embodiment of the present invention, particularly a planar structure example in the field of 15 dicing. Figures 2A to 2E show the main procedures of the manufacturing method of the semiconductor device used to fabricate the semiconductor wafer shown in Figure 1 and cut it to form a semiconductor wafer. It is a top view of the imaginary line Π · Π of Figure 1 . In FIG. 1, wafer areas C1 to C4 are divided in four corners. The wafer field C1 ~ C4 are the fields that constitute the semiconductor integrated circuit structure with multilayer wiring. An electrode pad P is disposed in a peripheral portion of the wafer area. In addition, seal rings SR1 to SR4 are formed to surround the periphery of the wafer areas C1 to C4 to prevent the intrusion of moisture and the like. The area outside the seal rings SR1 to SR4 is the scribing area SC. A dummy wiring dw is also arranged in the dicing area SC. The area with a certain width on both sides of the center line CC of the slicing area is the cutting area Dc, and the cutting operation for cutting 17 1239070 broken semiconductor wafers is performed in the cutting area DC. Outside the cutting area DC, a groove formation area GR for forming a through-passivation layer and surrounding the grooves C of each wafer area C can be divided. In the wiring layer accessible by the etching function for removing the passivation layer, the dummy wiring dw is not arranged in the groove formation area GR. At this time, in order to suppress the deterioration of the flatness caused by the absence of the dummy wiring, the width of the groove formation area should be 1/3 or less of the width of the scribe area. In the trench formation area GR, trenches G1 to G4 at least penetrating the passivation layer can be etched at the same time as the etching process of the electrode pad window opening. The width of the groove G is preferably in the range of 0.5 / zm to 10 / zm. If the width of the trench is too narrow, the etching may be insufficient or the stress may not be released sufficiently. If the width is too large, the width of the cutting area may also be limited, which is not sufficient to ensure flatness. A groove G is formed in the groove formation area GR on the outside of the cutting area DC, and the cutting is performed in the cutting area DC. There will be 15 areas where a passivation layer remains between the end of the wafer and the groove G after the cutting. For example, when the width of the scribing area SC is 126 // m, a range from 54 # m to 61 # m from the centerline CC of the cutting area DC can be used as the groove formation area GR, and from the center line In the area from 55 / zm to 60 / zm from CC, the passivation layer and the insulating layer thereon are etched to form the trenches G1 to G4. Cutting is performed in a field with a width of 40 ~ 50 # m from the centerline CC 20. The reason why the width of the groove formation area is 1 # m larger on each side than the width of the groove is to consider the mask alignment error. When the mask registration accuracy is high, the reserved width can also be reduced. The reserved width should be set to approximately 0 · 1 ~ 5 / zm according to the accuracy of mask registration. Dummy wirings DW are arranged on both sides of the trench formation area. 18 1239070 The trench can at least separate the passivation layer with stress inside, reduce the thickness of the insulation laminate, and locally weaken the strength of the insulation laminate. In the cutting field, since a passivation layer with internal stress remains, during cutting, cracks may occur from the cutting side, and peeling between the insulating layers may occur. If the peeling is above the bottom surface of the groove, of course, peeling 5 can be prevented by the groove. When the peeling is located further below the trench bottom surface, once the peeling extends below the trench, the insulating layer will split from the peeling surface toward the trench upward, and release the stress. This can also be inferred that the stress accumulated in the passivation layer and the locally weakened strength caused the upper insulating laminate to deform from the peeling surface. From this point of view, the groove 10 has the function of promoting the liberation of stress. In addition, as shown in the drawing, in the corners of the rectangular wafer field, the sealing ring SR should form a flat shape of the corners, and the groove formation field and the grooves should also be matched to form the corners. Sharp corner plane shape. At this time, as far as the corners are concerned, the aforementioned numerical range does not hold. 15 Since the cutting is performed in two directions that are approximately orthogonal, the corners of the wafer are affected by two cuttings. When the corners are slightly right-angled, they will be impacted twice, so even if grooves are provided, the stresses will cause peeling from the corners to the circuit area. By forming the grooves into a flat shape with sharp corners removed, the concentration of stress can be avoided, thereby effectively preventing peeling. Below, the main procedure of the manufacturing method will be described using a semiconductor device provided with a multilayer wiring layer having three layers (other than the electrode pad layer) having the structure shown in FIG. 1 as an example. The silicon substrate 10 shown in FIG. 2A can be divided into a dicing area SC and wafer areas C3 and C4 on both sides thereof. In the scribing area SC, the cutting area DC and the groove forming areas GR on both sides can be distinguished. Although the figure also shows the scribe area where the dummy wiring is still left outside the groove formation area GR 19 1239070, when flatness is required #Low Nissan Formation area GR can also extend beyond the scribe area. After the element separation area and the semiconductor element are formed on the surface of the Shixi substrate 10, the surface is covered with an insulating layer such as a silicon oxide film. After the conductive plug for drawing is formed, an etch stop layer ESI having an oxygen shielding function and a copper diffusion preventing function is formed on the insulating layer 21, and an interlayer insulating film IL1 is formed thereon. In the interlayer insulating film IL1 and the etching stopper layer ES1, a wiring trench and a via are formed again, and a first wiring layer including an i-th wiring W1 and a dummy wiring DW1 is formed by a Damascus process. The procedure for forming the damascene wiring is described later. 10 Similarly, an etching stopper layer ES2 covering the first wiring layer and having a function of preventing copper diffusion is formed, and an interlayer insulating film IL2 is formed thereon. Then, a recess for metal damascene is formed, and a second wiring layer including the second wiring W2 and the second dummy wiring DW2 is filled. Further, a third etch stop layer ES3 and a third interlayer insulating film IL3 are formed, and a recess for metal damascene is formed to fill the third wiring layer including the third wiring W3 and the 153rd dummy wiring DW3. Figures 3A to 3F are diagrams illustrating the wearing surface of the dual-embedding process. As shown in FIG. 3A, an element separation area 1 is formed on the surface of the silicon substrate 10 by STI to distinguish the active area. On the surface of the active area, a gate insulating film 12 is formed by thermal oxidation, and a polycrystalline silicon layer or a metal silicide (plylyde) 20 layer is formed thereon to form the gate electrode 13. A gate / source region 15 is formed on both sides of the gate electrode 13 to obtain a transistor structure. Next, the gate electrode 13 is further coated to form a stacked layer of a silicon nitride layer 21a and a silicon oxide layer 21b to form an insulating layer 21. Then, a conductive plug 17 is formed which penetrates the insulating layer 21 to extend the W of the electrode of the MOS transistor structure. Next, a stacked layer of an interlayer insulating film 23 such as silicon nitride, which has an oxygen shielding function of 20 1239070, such as silicon nitride, which covers the conductive plug 17, the insulating layer 21, is formed. A photoresist layer is formed on the build-up layer, and the wiring layer is patterned with holes. Then, the required portions of the interlayer insulating film 23 and the etching stop layer 22 are removed to form a trench for wiring, and then a key is borrowed to form a barrier metal layer 24 that can shield the diffusion of copper, and a seed metal is applied to the key 5. (Seed metal) layer (copper) layer, and a copper layer 25 is deposited thereon. Next, the useless metal layer on the insulating layer 23 is removed, and then a lower wiring layer is formed. Secondly, by using a plasma to promote chemical vapor deposition (PE-CVD), the silicon nitride layer 31, the oxide layer 32, the nitride layer 33, the oxide layer 34, and the silicon nitride layer as an anti-reflection film are formed. The thicknesses of 50 nm, 300 nm, 30 nm, 300 nm, and 50 nm are respectively formed to cover the base wiring layer. In addition, the middle silicon nitride layer 33 can be used as an etch stop layer when etching an alignment pattern. Even without an intermediate etch stop layer, a dual engraving process can still be performed. Next, a photoresist pattern PR1 having openings corresponding to the through-holes is formed on the anti-reflection silicon nitride layer 35 by applying a photoresist layer and performing an exposure display. Second, by using the photoresist pattern type PR1 as a mask, the reflection prevention nitride layer 35, the emulsified stone layer 34, the nitride stone layer 33, and the oxide stone layer 32 can be used. Then, remove the photoresist pattern PR1. 20 As shown in Figure 3B, fill the formed hole with a resin with the same composition as the photoresist mask without photosensitivity, and then return to the last name with an oxygen plasma to form a predetermined height. . For example, as shown in the drawings, the height may be approximately between the upper oxygen cut layer 34 and the lower oxygen cut button. As shown in FIG. 3C, a photoresist pattern with an opening corresponding to the wiring trench is formed at the reflection prevention nitrogen cutting layer, and then the first resist pattern PR2 is used as a mask to etch the silicon nitride layer 35 and the silicon oxide layer. When the etching is performed, the silicon nitride layer 33 is used as the etching stop layer 21 1239070. The pre-formed through holes are protected by a resin filler 37. Then, ashing is performed by using a plasma of O2 and CF4 to remove the photoresist type PR2 and the organic resin filler 37. As shown in FIG. 3D, 5% of the nitride nitride layer exposed on the bottom of the groove for wiring and the nitride nitride layer 31 exposed on the bottom of the via hole are etched again. In this way, the surface of the underlying wiring is exposed. At this time, you can also perform pre-treatments such as Ar sputtering, Η! Plasma, and Η annealing in the environment, and perform a reduction treatment on the exposed wiring layer surface to remove possible natural oxide films (including chemical oxides). . As shown in FIG. 3D, a Ta layer 38a having a thickness of, for example, 25 nm can be formed by sputtering, and a thick copper metal seed layer can be formed. On the seed layer, a Cu layer can be formed by electroplating to obtain a Cu layer 38b having a sufficient thickness. As shown in FIG. 3E, by chemical mechanical polishing (CMP), the metal layer on the surface of the silicon nitride layer 35 can be removed, and 〇1 wiring composed of 1 ^ layer 38 & (11 layer 3813) can be obtained. In the case of multilayer wiring, the same procedure is repeated. In addition, in this specification, a Cu alloy layer containing an additive is also referred to as a Cu layer, and an Ai alloy layer containing an additive is also referred to as an A1 layer. Hereafter, return to FIG. 2A An etch stop layer ES4 and a fourth interlayer insulating film IL4 are formed on the third wiring layer W3, and a through hole is formed to fill the via conductor TV. The fourth interlayer insulating film IL4 is formed on and communicates with The aluminum 20 top wiring layer connected to the hole conductor and forms the pattern of electrode pad P and sealing ring SR. Above the aluminum top wiring layer, the flatness requirements are lower, so it can not be configured on the aluminum top wiring layer Dummy wiring. This procedure will be described in detail below. Figures 3F to 31 are schematic diagrams showing the manufacturing process of the top wiring layer. As shown in Figure 3F, the third copper wiring W3 is formed by pE-CVD 22 1239070 Etch stop layer ES4 with a thickness of 70nm silicon nitride layer, and a silicon oxide layer with a thickness of 600nm The fourth interlayer insulating film IL4. Next, a photoresist pattern PR3 having an opening with a through-hole pattern is formed, and the fourth interlayer insulating film IL4 is etched to a thickness of 600mm. The etch stop layer ES4 is used as the etching operation. The use of a stop layer. Then, ashing is performed to remove 5 photoresistive pattern PR3. As shown in FIG. 3G, the fourth interlayer insulating film IL4 formed with a through hole is used as a mask, and the remaining nitride is etched. The etching stop layer ES4 of silicon. In this way, the surface of the lower wiring layer W3 is exposed. As shown in FIG. 3H, after the surface of the lower wiring layer is exposed by Ar sputtering, 10 thick TiN layer 39a is formed by sputtering or the like. A film is formed on the TiN layer 39a, and then a w-layer 39b with a thickness of 300 nm is formed by CVD to fill the vias. Then, the w-layer 39b and the TiN layer 39a on the surface of the interlayer insulating film IL4 are removed by CMP. The through-hole conductor filled in the through-hole can be obtained. As shown in FIG. 31, a Ti layer 40a with a thickness of 40 nm, a TiN layer 40b with a thickness of 30 nm 15 and a Aw40c with a thickness of lvm are stacked by sputtering. 5〇nn ^ Ti] sut4〇d. Then, a photoresist pattern is formed on the multilayer wiring layer and the last name is engraved to form the desired pattern. Shaped top wiring pattern. When the top wiring layer is aluminum wiring, the surface of the electrode pad is aluminum, which is suitable for wire bonding, etc. Hereafter, return to Figure 2A, where the top wiring is formed. After the layer is formed, a thick HOOnm high-density plasma (HDp) silicon oxide layer 18 with a thickness of 50001111 and a gasified stone layer PS with a thickness of 50011111 are formed on the layer 20. The nitride stone layer can form a moisture-proof layer. Purified film. As shown in FIG. 2B, by applying a photoresist layer pR4 on the passivation layer PS and performing parallel exposure and development, a window pw on the electrode pad and a window GW opened in the trench can be opened. Next, the photoresist pattern PR4 is used as a grass cover to etch the passivation layer ps, the insulating layer is, 23 1239070, and then etch the TiN layer on the surface of the electrode. In this way, the electrode pads with the exposed surface are exposed. After the passivation layer PS and the interlayer insulating film IL are etched in the dicing field, the fourth interlayer insulating film IL4, the etch stop layer ES4, and the third interlayer insulating film 5 IL3 underneath are etched. Depending on the degree of over-etching, further etching can be performed. The areas etched for this etching operation are not provided with dummy wiring. In the state of the drawing, although the third interlayer insulating film IL3 is etched, the second wiring layer underneath is not exposed.

Fig. 2C shows the state where the photoresist pattern PR4 has been removed after the etching is completed. The TiN layer on the surface has been removed, and grooves G are formed around the wafer areas outside the electrode pad P and the scribing collar 10 in the scribe region SC outside the cutting area DC. Since the dummy wiring is not arranged at least on the etchable wiring layer in the trench formation field, the dummy wiring is not scattered due to the moment of the trench G. By cutting the domain dc within the domain DC, the individual wafers can be separated.

As shown in FIG. 2D, 15-area dc within the full-thickness cutting dicing area DC of the wafer is performed to separate each wafer. During dicing, peeling between the insulating layers may occur from the side of the cut portion, but it prevents peeling from entering the circuit area. As shown in Figure 2E, when the insulation layer interface PL is peeled due to the impact of the cutting process, once the peel extends to the lower part of the groove G, the crack will spread toward the groove G, and the peeling will not go to the inside. diffusion. 20 As described above, the present invention can prevent peeling caused by the cutting process, and at the same time prevent scattering of the dummy wiring caused by the etching of the cap layer. Since the wiring layer in the trench formation field where no dummy wiring is configured can be limited to the top wiring layer and the wiring layer nearby, the underlying wiring layer can be configured with dummy wiring in the entire area of the scribe field. That is, in the wiring layer in which the dummy wiring is not arranged in the groove formation field, the width of the groove formation field is limited by 24 1239070. Therefore, by arranging dummy wiring in other fields, the deterioration of flatness can be suppressed to a negligible range. . When the wire bonding method is implemented, although: §: an electrode pad having an aluminum surface is provided, it is not necessary to use aluminum on the top layer when assembling by bumps. All wiring layers can be formed with copper wiring. At this time, dummy wiring is also arranged on the top wiring layer. Figures 4A and 4B show examples in which an aluminum wiring layer is not formed. As shown in FIG. 4A, the formation up to the third wiring layer W3 on the silicon substrate is the same as the previous embodiment. Next, a silicon nitride layer 43 having a thickness of 50 nm, a PE-CVD silicon oxide layer IS having a thickness of 400 nm, and a silicon nitride layer PS having a thickness of 500 nm were formed as cap layers. On the passivation layer PS of the silicon nitride layer, a photoresistive pattern PR5 having a window for electrodes and a window for stress relief trenches GW is formed. Then, the photoresist pattern pR5 is used as a mask to etch the purification layer PS and the insulating layer is. Thereafter, the photoresist pattern PR5 is removed. With the purification layer ps and the insulating layer IS as masks, the nitride nitride layer 43 is etched. 15 As shown in FIG. 4B, the electrode pad P of the third wiring layer has been exposed. The trench G is over-etched to the third interlayer insulating film IL3 for the third wiring layer. If dummy wiring is pre-arranged in the etching area, the dummy wiring will be scattered. By not disposing the dummy wiring in the trench formation area to the depth limit that can be engraved by the surname, the scattering of the dummy wiring can be avoided. In addition, in the above embodiment, although the formation of the dummy wiring is restricted while the openings and grooves for the electrode are formed at the same time, the selection and the control of the surname can also be performed to prevent the scattering of the dummy wiring. When there is another etching procedure, the groove can also be engraved by a different etching procedure than the electrode pad opening. In such cases, the dummy wiring can be fully deployed in the scribe area, including under the trench. 25 1239070 FIG. 5 is a plan view showing a semiconductor wafer according to another embodiment of the present invention. In this embodiment, the dummy wiring DW is disposed in the entire area of the dicing area SC. The bottom surfaces of the trenches G1 to G4 are located on a horizontal surface higher than the dummy wiring DW. Therefore, even if the trenches G1 to G4 overlap the dummy wiring DW, the dummy wiring dw is not scattered. 5 Although the other points are the same as those of the semiconductor wafer shown in FIG. 1, since the dummy wiring DW 'is also formed below the trenches G1 to G4, the restrictions on the width of the trenches gi to can be relaxed. Figures 6A, 6B, 7A, 7B, 8A, and 8B are cross-sectional views schematically showing three manufacturing methods that can realize the structure of Figure 5. 10 FIG. 6A corresponds to the procedure of FIG. 2A, but a dummy wiring DW is also arranged below the groove formation area gr. The passivation layer PS is formed with a photoresist pattern (shown in FIG. 2B) having an opening for electrode pads and a window for forming a trench, as shown in FIG. 2B, so that the passivation layer pS and the top insulating layer IS are engraved. When the passivation layer ps and the top insulating layer 13 on the electrode pad p are etched, the passivation layer PS and the top insulating layer IS are also substantially etched in the groove 15 and the grooves 0. Once the etching is excessive, the fourth interlayer insulating film IL4 will be etched thereunder. When this etching is performed, for example, by using an etching gas having a higher selectivity with respect to silicon nitride and silicon oxide, even if the fourth interlayer insulating film IL4 is etched, the fourth etch stop layer ES4 under it can be hardly etched. Leave it. Therefore, the dummy wiring DW3 disposed under the fourth coin-cut termination layer ES4 is not exposed, and scattering can be avoided. FIG. 6B shows a state where the photoresist pattern above the passivation layer has been removed. Although the electrode is 塾? There are openings, and the trench G reaches from the surface of the passivation layer PS through the top insulating layer IS and the fourth interlayer insulating film IL4 to the surface of the root stop layer ES4, but the fourth stop layer ES4 remains almost completely, and The dummy wiring DW3 is not exposed. 26 1239070 The above selective etching gas, for example, can be used to remove the silicon nitride layer of the passivation layer PS by an etching method using CF4 as the main etching gas. The etching rate for the silicon oxide layer is set to be slower. Figures 7A and 7B are schematic illustrations of other manufacturing methods that can realize the structure of Figure 5. As shown in FIG. 7A, when the same layered structure is formed as in FIG. 2A, the surface is planarized by a method such as CMP after the top insulating layer IS is formed. The thickness of the top insulation layer IS on the electrode 塾 P is significantly thinner than the thickness of the top insulation layer 10S of the trench formation area gr. A purified layer PS is formed on the planarized top insulating layer 18. As shown in FIG. 7B, a photoresist pattern PR4 is formed on the passivation layer PS, which can open the electrode pads and the trenches, to etch the passivation layer PS and the top insulating layer IS. Since the passivation layer PS has approximately the same thickness over the entire area, the remaining time will be completed at the same time on the electrode pad p and the groove θ 15. Once the top insulating layer IS is etched, the etching of the electrode pad p is completed when the top insulating layer IS remains under the trench G because the top insulating layer 岱 on the electrode pad P is thin. By controlling the etching time by controlling the etching time, even if the etching is excessive, the trench G may remain in the top insulating layer. Alternatively, the over-etching may be performed more frequently to etch the top insulating layer IS and the fourth interlayer insulating film IL4 below it. In addition, an etching gas with a high selectivity can be used as the engraving gas, so that it has an etching selection ratio with respect to silicon oxide and silicon nitride. If the trench G penetrates at least the passivation layer PS, its effect can be expected. The etching performed after the formation of the passivation layer PS is not limited to the engraving of the electrode pad opening. When there is another etching process independent of the electrode pad opening, the grooves can also be formed by using the other etching processes described in 27 1239070. Alternatively, a separate etching process for trench formation may be provided. Fig. 8A shows the procedure for engraving the electrode pad opening. After forming the top insulating plutonium and purifying the layer PS, a photoresist having an opening on the electrode plutonium_5 PR6 is formed. Next, the U photoresistive pattern PR6 is used as a mask to perform purification on the electrode pads and the top insulation layer IS. After opening the counter electrode 塾 p, the photoresist pattern PR6 is removed. In other etching processes, a photoresist pattern PR7 is formed. The photoresist pattern PR7 is provided with a trench-window forming window GW in the trench. In other surname engraving procedures, at least 10 surname engraving of the passivation layer ps is performed in the opening GW. Since the electrode 塾 p has already been perforated, the engraving can be performed independently of the conditions of the electrode pad opening. According to the above method, even if dummy wirings are arranged on the scribing area SC, the trenches G1 to G4 can be selectively formed in the scribing area. In addition, after forming a multilayer wiring of copper wiring, it is intended to form an electrode potential thereon! In the case of wiring, the flatness on the top copper wiring layer is not particularly required. Therefore, the dummy wiring of the top copper wiring layer may also be omitted. Fig. 9 shows a case where dummy wiring is not arranged on the top copper wiring layer in the scribe area SC. In addition, dummy wirings may be arranged on each chip area further inside than the seal ring SR. 20 The cross section of the imaginary line χ-χ in FIG. 10A and FIG. Fig. 10A corresponds to the cross section of Fig. 2a. Although the dummy wiring DW3 in the wafer is formed in the third wiring layer together with the wiring W3, no dummy wiring is formed in the scribe area Sc. The other points are the same as those in FIG. 2A. A person performs the same rest cutting process as that shown in Fig. 2B, and makes a hole in the electrode with 28 1239070. Figure _ shows the last name of the electrode pad, and the photoresist pattern is removed. The top insulating layer 18 and the purification layer "on the electrode pad p are etched to expose the surface of the electrode pad. The trench G penetrates the passivation layer ps' and penetrates the top insulating layer IS, the fourth interlayer insulating film IL4, the fourth The etch stop layer ES4 extends to the third interlayer insulating film IL3. However, since the dummy wiring of the third wiring layer is not provided in the dicing field, the trench G does not scatter the dummy wiring. In the wafer field, due to the configuration of the dummy wiring, Because of the wiring, the necessary flatness can be ensured. In the dicing field, the deterioration of the flatness caused by the omission of the third wiring can be controlled to a minimum. 10 In addition, when the flatness does not require special flatness, It is also possible to omit the dummy wiring of the third wiring layer in the wafer field. In the above-mentioned embodiment, grooves surrounding each wafer field are formed on both sides of the scribe field%. That is, two grooves are formed in the scribe field. However, the number of grooves is not limited to two. In addition, the passivation layer in the cutting area can be removed. Once 15 is removed, the cutting process can be simplified. The U-series is shown in the scribe area. There are 3 grooves A plan view of another embodiment. A groove CG having a larger width along the center line of the row is formed in the center of the scribing area SC. The central groove CG should actually be located in the cutting area. The other points are the same as the structure of FIG. 1 The same. Ί〇 Figures 12A and 12B are cross-sectional views of an imaginary line χπ-χϋ in Figure 11. As shown in Figure 12A, a semiconductor wafer having the same structure as that shown in Figure 2A is formed. Photoresistive pattern type PR8. Photoresistive pattern type pR8 has the same electrode pad window pw for opening electrode pads and the trench window GW for opening holes, as in the previous embodiment, and is used in the cutting field. The DC has a center window 29 1239070 for CW. Secondly, the photoresist pattern PR8 can be used as an etching mask, and the etching layer can be etched with an insulating layer containing a passivation layer PS and a top insulating layer IS. The money itself can be乂 The same procedure is performed as in the previous embodiment. For example, a nitrided nitride film can be used as an etch stop layer and etching can be completed by selective etching. Figure 12B shows the state after the photoresist pattern PR 8 has been removed. ~ Front view. The electrode pad P is open and the groove G is shaped. The completion point is the same as the previous embodiment, and the central groove CG is etched in the cutting area. The cutting process by forming the central groove cg in the cutting area dc can be simplified. The state after cutting is the same as the previous embodiment. The same effect as that of the foregoing embodiment can be expected. 10 15

In the above embodiments, the case where silicon oxide and nitride nitride are mainly used as the layer insulating film and the etching stopper has been described. However, it is also possible to use an oxide: insulating material as an interlayer insulating film. In particular, in a half-body device having multilayer wiring, a fluorine-containing silicon oxide having a lower dielectric constant than silicon oxide, silicon carbide SiOC, an organic insulating layer, etc. may be used to reduce the parasitic capacitance of the wiring. Etch = Stop layer In addition to silicon nitride, SiC can also be used. $

13 and 14 are cross-sectional views of a semiconductor wafer showing a manufacturing process of a conductor device according to another embodiment of the present invention having multilayer wiring. “As shown in FIG. 13, the element isolation region η is formed on the surface of the substrate 1G by shallow trench light branching (STI), and an electric field is formed in the active region already in the region of the element isolation region n. Crystal. The transistor structure includes the gate insulating film 12 on the channel field, the polycrystalline silicon gate 13 on the gate insulating film, the J ^ drain region 15 and so on. Then, the silicon oxide and other insulation covering the gate are formed. The layer 2m, and then the conductive plug 17 of the deep source / drain region is formed by w. 〃 An etch stop layer Esi having an oxygen shielding function is formed on the surface, and an interlayer insulating film IL1 is formed. A first wiring layer forming recess is formed on the first interlayer insulating film IL1 and the etch stop layer eS 丨, and a first wiring layer W1 made of copper wiring is filled. A second etching stopper is formed on the first wiring layer W1. Layer ES2, second interlayer insulation 5 film IL2 ', and fill in the second copper wiring layer W2. On the second wiring layer W2, a final cut-off layer ES3 and an interlayer insulation film IL3 are formed, and the third wiring layer W3 is filled. 3 On the wiring layer W3, an etch stop layer ES4 and an interlayer insulating film IL4 are formed, and the fourth wiring is filled. Layer W4. In addition, the interlayer insulating film for accommodating the first to fourth wiring layers is formed of a SiLKnet organic insulating layer. 10 The 19A to 19E diagrams illustrate the use of an organic insulating layer to form a metal damascene wiring. As shown in FIG. 19A, after forming the lower-layer wiring 50, the surface is covered with a copper diffusion preventing layer 51. The copper diffusion preventing layer is made of SiN or SiC, and it also has an engraving. Termination, oxygen shielding function. For example, a SiC layer 15 51 with a thickness of 30 nm can be formed. SiLK is spin-coated on the SiC layer 51 and cured at 400 ° C for 30 minutes to form a SiLK layer with a thickness of 450 nm. 52. On the SiLK layer 52, a 50-nm-thick SiC layer 53 is formed by PE-CVD, and further, PE-CVD is used to form a 10-nm-thick oxidized stone layer 54. A wiring recess may be formed on the oxidized-stone layer 54. The photoresist pattern 20 PR1 of the trench opening is scribed with a silicon oxide layer 54. The silicon oxide layer 54 is transferred to form a pattern for wiring grooves. Then, the photoresist pattern PR1 is removed by ashing. As shown in Figure 19B, a photoresist pattern PR2 having an opening for a through hole is formed therein. The photoresist pattern PR2 is used as a cover Then, 81 (: layer 53) can be etched. Second, the plasma containing oxygen is used for etching, and the photoresist pattern PR2 is ashed, and the SiLK layer 52 31 1239070 is etched to half. In this way, the photoresist pattern PR2 disappears. As shown in FIG. 19C, the silicon oxide layer 54 is used as a metal light-shielding film (hard mask) to etch the exposed SiC layer 53. In this way, the silicon oxide layer 54 and the SiC layer 53 can constitute a metal light-shielding film. 5 As shown in FIG. 19, the silicon oxide layer 54 and the SiC layer 53 are etched as a mask.

SiLK layer 52. In this etching process, the siLK layer 52 at the bottom of the via is also etched, and the SiC layer 51 is exposed. For example, the siLK layer 52 can be etched to a depth of 200 nm as a wiring groove. Next, 81 (: layer 51 exposed at the bottom of the via is etched to expose the surface of the underlying wiring. 10 As shown in FIG. 19E, a Ta layer 57a with a thickness of 25 nm is formed by sputtering, and then formed by sputtering thereon A copper metal seed layer with a thickness of about 100 nm. In addition, at the stage when the underlying wiring layer 50 has been exposed, the underlying copper wiring can also be removed by pretreatment by ΑΓ sputtering, h2 plasma, and annealing in H2 environment. The layer 50 is a natural oxide film on the surface. The copper metal seed layer can be formed by electroplating (^^ layer. The wiring structure groove can be filled with Cu 15 layers. Then, CMP is performed to remove the silicon oxide layer 54 surface. Excess metal layer. In addition, the oxidized stone layer 54 can also be removed by CMP. The following returns to FIG. 13, where an etching stop layer ES5, an interlayer insulating film IL5 are formed on the fourth wiring layer, and a wiring groove is formed , Through hole, and then fill the wiring layer W5. Similarly, a sixth wiring structure composed of an etch stop layer ES6, an interlayer insulating film IL6, and a 20 wiring layer W6 is formed thereon, and then an etch stop layer is formed. §7, The seventh wiring structure composed of the interlayer insulating film IL7 and the wiring layer W7 is formed later The eighth wiring layer composed of the etch stop layer ES8, the interlayer insulating film IL8, and the wiring layer | 8. The interlayer insulating film IL5 ~ ILm ^^ for receiving the fifth wiring layer to the eighth wiring layer is formed of SiOC. 32 The 1239070 苐 8 wiring layer is formed with a ninth wiring structure composed of an engraved termination layer ES9, an interlayer insulating film 1-9, and a S9 wire layer W9, and an etching termination layer ES10, an interlayer insulating film IL10, and wiring are formed thereon. The 10th wiring structure composed of layer W10. The interlayer insulation films IL9 and IL10 for the 9th wiring layer and the 10th wiring layer are 5 non-dope silicon oxide layers ( USG) creator. An etch stop layer ES11 and an interlayer insulating film IL11 are formed on the 10th wiring layer, and the same via hole conductor τν as in the previous embodiment is formed. Then, similarly to the previous embodiment, a structure can be formed on the surface. The aluminum wiring layer on the top of the electrode pad ρ and the sealing ring SR. Next, the top wiring layer is covered to form an insulating layer 矽 made of silicon oxide or the like, and after 10 planarization treatment, nitrogen is formed thereon in the same manner as in the previous embodiment. The passivation layer PS composed of siliconized silicon or silicon nitride oxide is shown in Figure 14. As shown, a photoresist layer pR10 is formed on the passivation layer PS, and openings are formed in the electrode pad P and the trench. Next, the photoresist pattern pRi0 is used as a mask to etch the passivation layer PS and the top insulating layer IS In the area on the electrode pad, the passivation layer PS and the top insulating layer IS will be etched to form a window for the electrode pad. In the trench 〇, the choice of the remaining time or the control time is used to form the electrode window. At the same time, the trench G is etched as deep as the eleventh interlayer insulating film IL11. On the dummy wiring of the wiring layer wio, the termination layer ES is not etched and the 'dummy wiring' is not scattered. 20 FIG. 15 shows the constituents when the virtual β and western lines are not formed on the top copper wiring layer W in the cutting field. In the dicing area SC, the defects of the tenth wiring layer W10 are not formed. And wiring. When etching the electrode pad ρ opening and the formation of the trench G, although the trench G will be superior to the 10th interlayer insulating film IL, the dummy wiring is not formed on the 10th wiring layer, and the dummy wiring can be prevented from scattering. In the scribe field of the 10th wiring layer, although the unshaped 33 1239070 is a dummy wiring, there are fewer wiring layers on it, and the adverse effects caused by the absence of the dummy wiring can be controlled to a minimum. Fig. 16 shows an example in which the electrode pad opening and the groove formation are not etched by different procedures. Since the etching for forming the trench G is performed separately from the etching for opening the electrode pad p, it can be independently selected for the formation from the etching for opening the electrode pad P. Trench G etching conditions. Therefore, by selecting the remaining conditions of the 'trench G', the dummy wiring of the wiring layer can be prevented from scattering. Figure 17 shows that the opening of the electrode pad p and the etching of the trench G are performed at the same time, but it is used for the formation of the trench G! Those who do not form a dummy wiring in areas that are affected by insect engraving. In the structure of the drawing, the dummy wiring of the tenth wiring layer W10 is not formed in the trench formation area. Therefore, even if the trench G is as deep as the 10th interlayer insulating film 10, since no dummy wiring is formed there, it is possible to prevent the dummy wiring from scattering due to etching. Fig. 18 shows the constituents when the central groove is formed in the area to be cut in addition to the grooves G on both sides in the dicing area. By forming the groove CG in the center of the area to be cut, the cutting process can be simplified. Since the cutting is performed in a wider area than the central ditch CG, the same effect as that of the other embodiments can be expected on the composition after cutting. Fig. 20A is a photo of a 0-plane microscope in a state where the sample shown in Fig. Π has been cut. The black part dc in the center is the area where the wafer disappears after dicing. Above the cutting area, fine grooves G are visible through the white areas. In the area on the left of the figure, the portion 2 starting from the position of the corresponding groove has partially disappeared. This can be inferred that the self-cut area has been peeled and expanded into the trench, and the top has cracks, which causes the surface layer to disappear. Above the groove, the black strip-shaped part of 34 1239070 is a moisture-proof seal ring SR. Furthermore, the large rectangular area above is the electrode 塾 p. In the sample of FIG. 20A, the first to fourth interlayer insulating layers 以 are formed with an organic insulating layer. The dielectric constant of the organic insulating layer is the lowest, and the parasitic capacitance of the wiring can be reduced. The 5th interlayer insulating film to the 8th interlayer insulating film IL5 to IL8 are formed by a SiOC layer. Although the dielectric constant of the SiOC layer is higher than that of the organic insulating layer, the dielectric constant is lower than that of the oxide oxide, which can reduce the parasitic capacitance of the wiring. The ninth interlayer insulating film IL9 and the tenth interlayer insulating film IL10 are formed by a silicon oxide layer. Although the dielectric constant of the silicon oxide layer is higher than that of the organic insulating layer and SiOc, the 10 series is a very stable insulator with high reliability. When the wiring layer is read to the upper layer, the larger the distance between the wirings, the looser the restrictions on the parasitic capacitance of the wiring. Therefore, the lower the wiring, the better it is to reduce the parasitic capacitance. The present invention has used three kinds of interlayer insulating films to meet the above requirements. In addition, samples obtained by changing the interlayer insulating film of the first to fourth wiring layers from the organic insulating layer to SiOC have also been prepared. Figure 20B shows a photomicrograph of the sample. The black part dc below is the area where the wafer disappears by dicing. A trench G is formed at a distance from the lower end, and a seal ring SR is formed above it. In the area on the right, the surface has disappeared from the cut side to the groove. This can be inferred that although the peeling from the side that has been cut from the industry has begun to infiltrate below the trench ', cracks have occurred on the upper side and the surface layer has been lost. As described above, by using the grooves to actively release stress, it is possible to prevent peeling from entering the wafer. The shape of the groove is not limited to the above description, but may be various shapes. FIG. 21A shows the shape of the auxiliary groove GS formed on the side of the corner 12 of the groove ⑽, which is the same as the above embodiment. In this way, it is possible to more surely prevent the intrusion of the peeling corner portion. Fig. 21B shows the shape of the ring-shaped auxiliary groove GS shown inside the above-mentioned groove GM. In this way, it is possible to more reliably prevent the invasion of peeling throughout the entire week. 5 Into Fig. 21C shows the deformation of the corner trimming method. It is a shape obtained by cutting the corners of a rectangle with 3 straight lines, not by cutting with 1 straight line. The number of straight lines may be plural, and is not limited to three.

Figure 21D shows the shape of the corners without trimming. Although the resistance to peeling invasion is weak, if this is enough, it can be fully applied, and the corners can not be trimmed. Fig. 21E shows a shape in which four grooves LGM1 to LGM4 surround the wafer area. Although the grooves LGM1 to LGM4 are not continuous grooves, they surround the wafer area at an azimuth angle.

The present invention has been described above with reference to the examples, but the present invention is not limited to these examples. The materials and values can be changed in various ways depending on the purpose. Those skilled in the art should understand that the present invention can be modified, improved, and combined. Industrial Applicability The present invention can be applied to a semiconductor device having multilayer wiring. In particular, there may be a 20-effect manufacturing method for a semiconductor device using copper wiring and removing excess metal layers by CMP. I: Brief Description of Drawings 3 FIG. 1 is a schematic plan view of a semiconductor wafer according to an embodiment of the present invention. 36 1239070 Figures 2A to 2E are cross-sectional views showing main procedures of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3A to 31 are sectional views showing the procedures for forming the wirings of Figure 2A in more detail. 5 Figures 4A and 4B are cross-sectional views showing main procedures of a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 5 is a schematic plan view of a semiconductor wafer according to another embodiment of the present invention. 6A and 6B are cross-sectional views showing main procedures of a method for manufacturing a semiconductor device according to the embodiment shown in FIG. 5; 10 FIGS. 7A and 7B are cross-sectional views showing main procedures of another method for manufacturing a semiconductor device according to the embodiment shown in FIG. 5. 8A and 8B are cross-sectional views showing main procedures of another method for manufacturing a semiconductor device according to the embodiment shown in FIG. 5; FIG. 9 is a schematic plan view of a semiconductor wafer according to another embodiment of the present invention. 15 FIGS. 10A and 10B are cross-sectional views showing main procedures of other manufacturing methods of the semiconductor device of the embodiment shown in FIG. 9. FIG. 11 is a schematic plan view of a semiconductor wafer according to another embodiment of the present invention. Figures 12A and 12B are cross-sectional views showing main procedures of other manufacturing methods of the semiconductor device of the embodiment shown in Figure 11; 20 Fig. 13 is a cross-sectional view schematically showing the structure of a first embodiment of a semiconductor device having 10 layers of wiring. Fig. 14 is a sectional view schematically showing the configuration of a modification of the first embodiment of the semiconductor device having 10 layers of wiring. Fig. 15 is a cross-sectional view schematically showing the structure of a second embodiment of a semiconductor device having 10 layers of wiring. Fig. 16 is a sectional view schematically showing the configuration of a modification of the second embodiment of the semiconductor device having 10 layers of wiring. Fig. 17 is a cross-sectional view schematically showing the structure of a third example 5 of a semiconductor device having 10 layers of wiring. Fig. 18 is a sectional view schematically showing the configuration of a fourth embodiment of a semiconductor device having 10 layers of wiring. 19A to 19E are sectional views showing a procedure for forming a metal damascene wiring in the organic insulating layer shown in Fig. 5. 10 Figures 20A and 20B are top photomicrographs of the wafer after cutting the wafer based on the structure shown in Figure 17. Figures 21A to 21E are schematic diagrams showing modification examples of the shape of the groove formed in the groove formation area. 22A and 22B are schematic cross-sectional views showing a structure of a peeling prevention groove 15 and a structure of a semiconductor device having a dummy wiring when a semiconductor wafer is cut by a conventional technique. Fig. 23 is a cross-sectional view showing the results of a review conducted by the present inventor on a conventional technique. Fig. 24 is a cross-sectional view 20 schematically showing the results of other reviews obtained by the present inventors' research. Fig. 25 is a schematic sectional view showing a phenomenon found by the present inventors. 38 1239070 [Representative symbols for main components of the drawings] 10 ... semiconductor substrate 39b " .W layer 11 ... element separation area 40a ... Ήlayer 12 ... gate insulating film 40b ... TiN layer 13 ... gate 40c ... A1 layer 15 ... Source / drain area • TiN layer 17… Conductive plug 43… Vaporite layer 21… Insulation layer 50… Lower wiring 21a ··· Nitride chip 51 · Copper diffusion prevention layer, SiC layer 21b ·· · Silicon oxide layer 52 ... SiLK layer 22 ... Etch stop layer 53 ... SiC layer 23 ... Interlayer insulating film 54 ... Oxidation layer 24 ... Barrier metal layer 57a " Ta layer 25 ... Copper layer 101 ... Crush substrate 31 ... nitride layer 102 ... interlayer insulation film 32 ... oxide layer 103 ... element separation area 33 ... nitride layer 104 ... interlayer insulation film 34 ... oxide layer 105 ... insulation layer 35 ... nitride layer 106 ... Wiring 37 ... Fill 107 ... Polyimide protective layer 38 ... Photoresist pattern 108 ... Peel stop groove 38a ... Ta layer 109 ... Interlayer insulating film 38b ... Cu layer 110 ... Wiring 39a ... TiN layer 111 ... Dummy wiring 39 1239070 112 ... Interlayer insulation film 113 ... Welding technique 114 ... Wiring 115 ············································································································ Insulating layer 125 ... Passive layer A ... Dicing area B ... Peripheral circuit area C ... Wafer area CC ... Midline CG of scribe area ... Trench, central trench CL ... Stripped CW ... Window for central trench DC ··· Cutting area dc ... Area DW within scribe area SC ... Dummy wiring ES ... Etching stop and copper diffusion preventing layer G ... Trench GM ... Trench GR ... Trench formation area GS ... Auxiliary trench GW ... Trench opening Window IL ... Interlayer insulation film IS ... Top insulation layer LGM ... Trench P ... Electrode 塾 PR ... Photoresistive PW ... Electrode pad window PS ... Passivation layer SC ... Scribing area SR ... Seal ring TV ... pass Hole conductor W ... Metal (copper) wiring layer Z1 ... Inner wall portion Z2 on the outside of the groove G ... Outside of the bottom surface of the groove G

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Claims (1)

1239070 Scope of patent application: 1. A method for manufacturing a semiconductor device, including the following procedures: (a) preparing a plan including a plurality of wafers in which semiconductor elements are formed and separating the aforementioned plurality of wafers and including a cutting field for cutting Semiconductor wafers, and the semiconductor wafers surrounding the trench formation areas surrounding each wafer area are divided outside the cutting area within the five-segment area; (b) an interlayer insulation film has been alternately formed on the semiconductor wafers; Multilayer wiring structure and dummy wiring with wiring layer; (c) forming a capping layer covering the multilayer wiring structure and containing a purification layer; and 10 (d) in the trench formation area, formed by penetrating at least the passivation layer from above Individual grooves surrounding the aforementioned plurality of wafer regions are respectively enclosed. 2. For the method of manufacturing a semiconductor device according to the scope of claim 1, wherein in the aforementioned procedure (b), at least the dummy wiring is not formed in the trench formation area in the top wiring layer. 3. The method for manufacturing a semiconductor device according to item 1 of the patent application scope, wherein the aforementioned 15-layer wiring layer is a copper wiring layer. 4. If the method for manufacturing a semiconductor device according to item 1 of the patent application scope further includes an (e) procedure, after the aforementioned (d) procedure, the semiconductor wafer is cut in the aforementioned cutting field. 5. For the method of manufacturing a semiconductor device according to item 1 of the patent scope, at least in the top 20 wiring layers, no dummy wiring is provided in the aforementioned scribe area, and the lower wiring layer is provided with dummy wiring outside the trench formation area. 6. The method of manufacturing a semiconductor device according to item 5 of the patent application, wherein the aforementioned top-layer wiring layer is an aluminum wiring layer. 7. The method for manufacturing a semiconductor device according to item 6 of the scope of patent application, wherein the wiring layer other than the top wiring layer of the above-mentioned multiple 41 1239070 layer wiring structure is a copper wiring layer of a metal damascene structure. 8. The method for manufacturing a semiconductor device according to item 7 of the patent application scope, wherein the interlayer insulating film on the aforementioned copper wiring layer includes a copper diffusion preventing layer 5 that prevents copper diffusion and an insulating layer thereon. 9. For the method of manufacturing a semiconductor device according to item 1 of the application, wherein the top wiring layer of the multilayer wiring structure includes an electrode 塾, the procedure (d) includes selectively removing the cap layer to expose the electrode pad, and And an etching step for selectively removing the cap layer and the interlayer insulating film under the trench forming area. 10 10. According to the method of manufacturing a semiconductor device according to item 1 of the scope of the patent application, the grooves have a shape that is trimmed on the sides of the corners in the wafer field. 11. The method for manufacturing a semiconductor device according to item 1 of the patent application range, wherein the width of the aforementioned groove formation area is 1/3 or less of the width of the aforementioned dicing area. 12. For the method of manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the width of the aforementioned 15 trenches is in the range of 0.5 // m to 10 / z m. 13. —A semiconductor wafer including: a semiconductor wafer including a plurality of wafer areas in which semiconductor elements are formed and a dicing area that separates the plurality of wafer areas and includes a dicing area for cutting, and is more advanced than the aforementioned dicing areas. The inside of the cutting area is divided into grooves 20 forming areas surrounding each wafer area. The multilayer wiring structure is formed above the aforementioned semiconductor wafer, and includes a multilayer wiring structure and a dummy wiring layer that alternately stack an interlayer insulating film and a wiring layer. A cover layer formed by covering the multilayer wiring structure and including a purification layer; and a trench formed in the trench formation field through at least the passivation layer to form 42 1239070. 14. For a semiconductor wafer with a scope of application for item 13, in which the aforementioned multilayer wiring structure has at least no dummy wiring in the trench formation area in the top wiring layer. 15. For the semiconductor wafer with the scope of application for item 13, wherein the width 5 of the aforementioned trench is within a range of 0.5 // m to 10 # m. 16. For a semiconductor wafer with a scope of application for item 13, wherein the top wiring layer of the multilayer wiring structure includes an electrode 塾, and further includes an opening for an electrode 贯通 which penetrates the cover layer and exposes the electrode ，, the structure groove is It penetrates through the cover layer and goes deeper into the interlayer insulating film. 10 17. The semiconductor wafer according to item 13 of the scope of patent application, further comprising a circle formed by the same layer of the aforementioned wiring layer and disposed on the outside of the aforementioned multilayer wiring structure and penetrating the interlayer insulating film in each of the aforementioned wafer fields. Moisture-proof ring. 18. For a semiconductor wafer with a scope of application for item 13, wherein the interlayer insulating film includes a copper diffusion preventing layer that prevents copper from diffusing, and the insulating layer thereon, the materials of the upper layer 15 and the lower interlayer insulating layer are different from each other. . 19. The semiconductor wafer as claimed in item 13 of the patent application, wherein the groove has a shape that is trimmed outside the corners of the wafer field. 20. —A semiconductor device comprising: a semiconductor substrate including a wafer area in which a semiconductor element is formed and a scribe area around the aforementioned wafer collar 20 area, and a groove formation area surrounding each wafer area is defined in the scribe area. The multilayer wiring structure is formed above the semiconductor substrate and includes a multilayer wiring structure and a dummy wiring layer which are alternately laminated with an interlayer insulating film and a wiring layer; a cover layer formed by covering the foregoing multilayer wiring structure, and including a passivation layer in And 43 1239070 trenches are formed by penetrating at least the passivation layer from above in the trench formation area. 21. The semiconductor device as claimed in claim 20, wherein the width of the aforementioned trench is in the range of 0.5 / zm to 10 // m. 5 22. The semiconductor device according to item 20 of the application for a patent, wherein the top wiring layer of the multilayer wiring structure includes an electrode pad, and further includes an opening for an electrode pad that penetrates the cover layer to expose the electrode pad, and the structure groove is The cover layer penetrates into the interlayer insulating film below it. 23. For example, the semiconductor device according to the scope of application for patent No. 20 has a circle which is arranged on the outside of the multilayer wiring structure in the field of 10 wafers and penetrates the interlayer insulating film to form the same layer of the wiring layer. Moisture-proof ring. 24. For the semiconductor device of claim 20, wherein the interlayer insulating film includes a copper diffusion preventing layer that prevents copper from diffusing, and an insulating layer thereon, the materials of the upper and lower interlayer insulating layers are different from each other. 15 25. The semiconductor device according to item 20 of the patent application, wherein the groove has a shape that is trimmed outside the corners of the wafer field. 26. In the semiconductor device according to claim 20, the interlayer insulating film of the multilayer wiring structure is partially defective outside the trench. 27. The semiconductor device according to claim 26, wherein the surface of the defective portion of the interlayer insulating film 20 is lower than the bottom surface of the trench. 28. For a semiconductor device according to item 27 of the patent application, wherein the bottom surface of the defective portion of the interlayer insulating film includes the interface of the interlayer insulating film, and the side surface includes the split surface from the aforementioned interface to the trench. 44