TWI238943B - Apparatus and method for masked move to and from flags register in a processor - Google Patents

Abstract

A method and apparatus are provided for writing to, and reading from, the EFLAGS register in a processor. For a particular write to EFLAGS request, a mask is generated using destination information for the write and privilege level information for the write. The mask is then ANDed with EFLAGS new value information and the result is written to the EFLAGS register in a single instruction cycle. For a particular read from EGLAGS request, a mask is generated using privilege information for the read to specify those bits of EFLAGS which can be updated during the read. The mask is then ANDed with the contents of the EFLAGS register and the result is stored in a stack in memory.

Description

1238943 Case No. 92128964__ Month Amendment V. Description of Invention (1) [Comparison with related applications] [0 0 0 1] The priority application of this application is based on the US patent application, case number 60/345455, Application date: 1 0 / 23/200 1, patent name

Weigh: " APPARATUS AND METHOD FOR MASKED MOVE TO FLAGS REGISTER, '. [Technical field to which the invention belongs] [0002] The present invention is related to the execution of computer instructions to reduce the execution of write / read EFLAGS temporarily-You Caiyu

1238943 Case No. 92128964 V. Description of the invention (2) Equipment and method. [Prior art] [0003] In an x86 pipeline microprocessor, the number of cycles required to execute an instruction (eg, POPF / popfd, CLI / STI, CLD / STD, CLC / STC) written to the EFLAGS register. very much. Because the action of writing to the EFLAGS register is affected by the current I / O privilege level (IOPL) and the state of some bits in the EFLAGS register at the time of writing. Under the Microsoft Windows R operating system, each time a subroutine responds, the EFLAGS register must be retrieved from the stack memory, resulting in a significant operating system delay. [0 0 0 4] Therefore, the present invention provides a microprocessor operation technology to reduce the delay associated with executing an instruction written to the EFLAGS register, such as a pop instruction.

[0005] At the same time, in an x86 pipeline microprocessor, the EFLAGS register is stored in one of the stacked storage push-down (pUsh) instructions, that is, PUSGF / PUSHFD, which requires a considerable number of cycles. Because the state of the bits read from the EFLAGS register and the execution status of the microprocessor are subject to the current I / O privilege level (IOPL) and the specific bits in the EFLAGS register are below The effect of the state when pushing. Under the Microsoft Windows R operating system, each time a subroutine is responded, the EFLAGS register must be stored in the stack memory, resulting in a significant operating system delay. [0 0 0 6] Therefore, the present invention provides a microprocessor operation technology to reduce

Drawing 1238943 92128964 the next day's correction --- 5. Description of the invention (3) The delay in storing EFLAGS to the stack memory related to the execution of an instruction that reads the EFLAGS register, for example, the push instruction . [Summary] [0 0 0 7] In a specific embodiment of the present invention, the present invention provides a method for performing a write operation on a multi-bit flag register in a microprocessor. The method includes using a translation stage of a microprocessor to receive a macro instruction requesting a write to the bit flag register. The method also includes a four-turn thick stage to generate a micro-instruction, which is configured to complete writing to the multi-bit flag register in an earlier write cycle. The method μ includes generating a flag mask, and using the flag mask and a predetermined operation 3 = Γ to produce a result, which is then deposited into the ticket: register 'and in In the specific embodiment, the bismuth of 1 multi-bit flag is temporarily stored as 15 the EFLAGS register. EFLAGS temporarily; ^ issue = :: completed in-instruction cycle-write to this in this issue // with effective-effective and less processing / delay. Including the use of a microprocessor to master the difference. In the method, the bit flag register :: ;;; stage, to receive a request to read the stage to generate-micro-finger ♦, 2: 2 The method also includes using the translation period to complete reading the multiple bits The flag is configured as an on-single-write weekly mark mask. The flag mask includes the method and further includes generating-flag reading at one of the current privilege levels. ^ Two messages. The privilege information is about -Under the purchase and shipping, the multiple flags are temporarily stored 11 ^ 1

Page 8 1238943 Bits used for update. The sum of the predetermined operands is stored as a result in the memory. The present invention can effectively reduce the delay of the director, for example, the delay of the push-down in a memory. Other objects and advantages of completing these EFLAGS reactor inventions during this ordering cycle will become clearer. Amend

Case No. 92128QR4 V. Description of the invention (4) The appropriate flag masks and methods of the device further include stacking the [0010] processor in the fetch operation and storing it in a single finger [0011] attached to this Graphing the method further includes using the result to produce a result. The side is stacked inside the reservoir. As the EFLAGS temporary storage device and method implementing the EFLAGS reader can be pushed down the stackable memory. The following detailed description and [Embodiment] [0 0 1 8] The following description is provided in the context of a specific embodiment and its necessary conditions, so that those skilled in the art can use the present invention. However, 'a variety of modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein' can also be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but has the widest scope consistent with the principles and novel features disclosed herein. [0019] Please refer to FIG. 1, which is a block diagram illustrating a conventional pipeline microprocessor 1000. The microprocessor has an extraction phase 105, a translation phase 110 ', a temporary storage phase 115, an addressing phase 120, a dat / ALU or execution phase 125, and a write back 130 phase. [00 0 2] During operation, the fetching stage 105 fetches macro instructions from a memory (not shown) for execution by the microprocessor 100. The translation stage 11 0 will

1238943-^ 92128964 Year 5. Article description of the invention (5) " " '~-The extracted macro instruction is translated into the corresponding micro instruction. [0 0 2 1] Each micro-instruction is used to instruct the microprocessor to perform a special sub-task, and the sub-task is a part of completing all operations of an extracted macro instruction. The temporary storage stage 丨 丨 5 retrieves the operand specified by the microinstruction from a temporary archive for use by subsequent stages in the pipeline. The addressing stage 1 2 0 calculates the memory address specified by the microinstruction for the > material storage and retrieval operations. Phase 125 is not to perform arithmetic logic unit (ALU) operation on the data retrieved from the temporary file, that is, to use the memory address calculated in the addressing phase 120 to retrieve the data from the memory. Read or write data to the memory. The write-back stage 丨 30 writes a data read operation or an execution result of an ALU operation to the temporary file. Therefore, reviewing the entire process of 'fetching macro instructions' at stage 105, these macro instructions are decoded into micro-instructions through translation stage 1 10, and the translated micro-instructions then flow through 115-130 The stage performs operations, thus constituting a pipeline operation of the microprocessor 100. [0022] In order to improve understanding of microprocessor string processing, a standard nomenclature of an x86 microprocessor will be used in the following discussion. However, those skilled in the art will find that the registers and macro instructions using the X 8 6 architecture are limited to examples, and other microprocessors and architectures can also be used as examples. [0023] The Data / ALU stage 125 includes an EFLAGS register 132. The EFLAGS register 1 32 stores the state of the processor. For conditional instruction loop (conditional l〇op) and conditional instruction jump (c〇nditi〇nal

1238943 _ Case No. 92128964_ Year Month Day__ 5. In the description of the invention (6) jump), the EFLAGS register 132 can be modified by many instructions and can be used as a comparison parameter. Each bit of the EF LAGS register holds the status of specific parameters of the last instruction, as shown in Table 1 below, which shows the 32 bits of the EFLAGS register and the function of each bit.

Form one

Page 111238943 _Case No. 92128964_ Year Month Date_ V. Description of the invention (7) EFLAGS register bit number name function 32:22:00 Reserved " Connect to low potential " 21 ID ID flag 20 VIP Virtual Interrupt pending 19 VIF Virtual Flag 18 AC Alignment Check 17 VM Virtual Chess 16 RP Reply Flag 15 0 " Connect Low «Bit " 14 NT Flag 1 Flag 13:12 IOPL Output Input Privilege Level 11 OF Overflow flag 10 DF Direction flag 9 IF Interrupt flag Peugeot 8 TF Trap flag 7 SF Symbol flag 6 ZF Zero flag 5 0 " Connect to low potential_ 4 AF Auxiliary carry flag 3 0 " Low «bit 11

[0024] In a pipeline microprocessor, such as the processor 100, any one of the instructions (that is, POPF / POPFD, CLC / STC, CLD / STD, CLI / STI) requires a considerable number of machine cycles to execute. Because the action written to the EFLAGS register 132 is subject to the current I / O privilege level (IOPL) and the EFLAGS register

Page 12 1238943

The influence of the state of some bits in a write, especially bit 丨, bit3, bit5, bit15, and bits22 ~ 31 are reserved, and their status cannot be Was changed. In addition, when the processor is operating in the protected mode of privilege level 0 (also known as the real address mode), all non-reserved bits can be modified except VIP, VIF, and VM. The νιρ and VIF flags must be cleared 'and the VM flag must remain in its current state. 〃 [0 025] Any of the foregoing writing data to the execution of the macro instruction with the register 132 will cause the generation of some micro instructions. In detail, a micro instruction will be executed first to determine the current output Enter Privileged Level (IOPL) 'These subsequent micro instructions read the current state of certain EFLAGS bits, such as: VM, RF, IOPL, VIP, VIF, and IF, and set the bit state to a new value to Is written to EFLAGS. And a new microinstruction writes the new value to EFLAGS register 132. [0 026] The aforementioned traditional method of updating the EFLAGS register has a very significant deficiency, that is, it must be Many micro-instructions need to be executed to complete writing to the EFLAGS register. Because there are several micro-instructions that must be generated and processed, the above update of the EFLAGS register will consume a lot of time and make the performance of the microprocessor [0 0 2 7] The present invention notices that under the Microsoft Windows operating system, each time a subroutine has a response, the EFLAGS register must be pulled out of the stack memory, and this Situation also Applications created on many desktop computers that are commonly used today. Since this type of instruction is widely used by the general public, there is an urgent need to minimize the execution time of these instructions

1238943 _ Case No. 92128964_ Year Month Date 日 π: _ V. Description of the Invention (9) Less 〇 [0028] The purpose of the present invention is to reduce the number of instruction cycles required to execute a write to theeflagS register. To achieve this, the present invention provides a device and method for dynamically generating an EFLAGS mask. The mask performs logical AND operation on a specified operand in combination (ie, unstacks the EFLAGS register, or selects the EFLAGS bit state), and writes the result to the EFLAGS register. The new processor disclosed here has the following advantages; the processor uses a new micro instruction, Move To EFLAGS (MTEF), which combines the special logic of the execution stage, so that the actions written to EFLAGS can be executed in Completed in a single instruction cycle. [0029] Please refer to FIG. 2 ′, which is a block diagram illustrating a processor 200 using a single microinstruction, namely Move To EFLAGS (MTEF), to complete writing to the eFLAGS temporary in a single instruction cycle. Memory. The processor 200 includes an extraction stage 202, and the extraction stage 202 includes an instruction fetch logic 204 coupled to the instruction memory 206. An instruction pointer 208 is coupled to the fetch logic 204 to instruct the fetch logic 204 to a specific location of the memory 206 to fetch the current instruction.

[0 03 0] When the fetch logic 204 fetches a macro instruction, such as: POPF / POPFD, CLI / STI, CLC / STC, or CLD / STD instruction, the translator 210 in the translation stage 212 responds to generate a MTEF D, S micro-instruction, this instruction will perform an action to move to the EFLAGS register in the data / ALU-execute stage. In the MTEF D, S microinstruction, S is a source stop, and the source stop instruction will be transferred to the data source of the EFLAGS register 214; D

Page 14 1238943 Amendment 92128984 V. Description of the invention (10): Bit: The purpose stop is specified in bit 70, which is intended to be written in the muscle AGS register 214. [0 0 3 1] Here, before discussing the processing of the MTEF microinstruction, the rest of the architecture of the processor 200 is discussed. As shown in Figure 2, the mtefd s microinstruction is sent to the translation instruction queue (XIQ) 218. Then, the mtef β, s, instruction flows to the MTEF register 22, which is one of the temporary storage stages 222. The temporary storage stage 222 is used to store the architecture state of the processor 200. An ESP architecture register 226 is temporarily included. As shown in Figure 2 *, the temporary storage stage 22 ^ includes an OP1 register 228 and an 0P2 register 230. [0032] The temporary storage phase 222 is coupled down to the loading phase 232 via the positioning phase. The processor 200 uses a conventional positioning stage 25 to calculate the addresses used by the processor 200 to process the instructions. The contents of the MTEF register 220 in the positioning stage ^ 22 are sent to and stored in the corresponding MTEF register 234 in the loading stage 232. The loading stage 232 includes a loading / adjustment logic 236 ', which is coupled to the OP1 register 228 and the OP2 register 230 of the temporary storage stage 222. The load / adjust logic 236 is also coupled to the data memory 238. The output of the load / adjust logic 236 is coupled to the OP3 register 240. As shown in Figure 2, the contents of the temporary storage stage 222 to 0)) 1 register 2 28 and the OP2 register 230 are transferred down to the OP1 register 242 and the OP2 register 244 of the loading stage 232, respectively. . [0033] The processor 200 further includes a data / ALU or execution phase 216. The execution phase 216 includes the aforementioned EFLAGS register 214. The execution phase 216 also includes a TVAL register 246 and a TMASK register 248, and the contents of the TVAL register 246 and the TM ASK register 248 are determined by the first and second gates. 92128964 V. Description of the invention (11) Combined with the operation, the result of the AND operation is stored in the EFLAGS register 2 1 4. The following discussion will be about the sum operation and the mask operation provided by the tmASK register 2 4 8. The execution stage 2 1 6 also includes a privilege level register PR IV 252. The privilege level register provides the privilege information of the instructions currently being executed by the "register 248". The results of the execution of these instructions are The results are sent to the result register 2 5 4 and the results are written to the register file 2 2 4 via a result bus (not shown). [0034] As mentioned previously, the logic is extracted for the response. 204 is provided to one of the translators 210, the extracted p0pf / p0pfd, CLI / STI, (: Ιχ / 8ϊ (:, CLD / STD macro instruction, the translator 21) generates a single micro instruction MTEF D, S, and the MTEF D, S microinstruction is sent to the translator queue (XIq) 218 coupled to the transponder 210, and then sent to the translator queue (XIQ) 218 The temporary storage phase 222. The micro instruction includes a source block, S, and a target field D. The target block is used to specify the bit that should be written in the EFLAGS temporary state 214. For example, if D = 〇, then the purpose of the stop will refer to the writer to the carry flag CF, the carry flag M, ^ table is different, is the 0 bit of the EFLAGS register In another example, BU 9 writes a designated 11 bit to the EFLAGS register, and D =: 1 writes to the DF bit of the EFLAGS register. At the MTEF D, the leg gs is written. The register popup 214 from the stack storage is set to D = 31. Select the source block S of the EF micro instruction and specify the state to be written to the S bit. For example Come to H10, s =. 'That is, the command processing ㈣Cabu steel ...' that is the command processor 1238943

20 0 Set this carry flag. In other words, in the MTTE {Γ microinstruction, s = r0 means to clear the destination bit, and S = 1 means to set the destination bit. For a POP EFLAGS instruction, the instruction ignores the 5 fields. [0036] When writing to the EFLAGS register, the execution logic 2 56 in the data / ALU execution stage 2 16 is used as a mask to ensure that only the correct bit position is written. When an MTEF micro instruction is executed, the contents of the TMASK register 248 are dynamically generated. data / ALU execution phase 21 6 execution logic

Series 256 accesses the current operation mode from the privilege register PRIV 252, and accesses the state of other bits from the EFLAGS register 214. The content provided to the new value register TVAL 246, if it is not the value of the s block, is the EFLAGS register read from the stack memory during the loading phase 232. As shown in Figure 2, TVAL and TMASK are connected by a AND gate 250, and the result of the AND gate 250 operation is written to the EFLADS register 214. Advantageously, the TMASK system is configured to change only Certain bits, and the certain bits are a bit that can be used as a function of the particular current operation mode read from the PR IV register. In this specific embodiment, the highest privilege level owned by an instruction is 3 '. The highest privilege level instruction has the highest allowability when updating the specified bits of the EFLAGS register. Instructions with lower privilege levels have more restrictions on updating this EFLAGS register. The highest privilege level is 〇〇. In a specific embodiment of the present invention, the number of bits in the mask is equal to the number of bits in the EFLAGS register. When a specific mask bit is set, it means that the mask bit is below the current privilege level of the PRIV register 252, and it can be updated. Conversely, if a specific mask bit is not set, , The mask bit cannot be updated. All in all, the department

Page 171238943-Case No. 92128964 _Year Month Day Amendment 5 'Invention Description (13) Provide the specific value written to EFLAGS, and TMASK according to the specific instruction corresponding to stored in the PRIV register 252 Privilege level to determine if a write operation is allowed. [0037] The present invention enables an instruction written to the EFLAGS register to be completed in a single instruction cycle, thereby significantly increasing the output of the processor. [0 0 3 8] Please refer to FIG. 3, which shows a flowchart for describing an outline of a high-level processing flow of the microprocessor 200 according to the present invention to perform an operation written to the EFLAGS register. The process starts at block 3 00, where 'fetch a macro instruction from memory, for example: p0pF / p0pFD, CLI / STI, CLC / STC, or CLD / STD, and the process then proceeds to block 305. . In block 305, the translator 210 translates the macro instruction into a micro-instruction that is required to be written to the EFLAGS register 214, and the flow proceeds to block 310. In block 31o, an EFLAGS mask is generated in the EFLAGS mask register TMASK 248, and the flow proceeds to block 315. In block 315, as described above, a new value will be written to EFLAGS, and the execution result of the macro instruction will be loaded into the smart register 246. The flow then proceeds to block 320. At block 320 The target information will be provided to the TMASK register 248, and the flow then proceeds to block 325. In block 325, the current privilege level is provided to the TMASK register 248. If the privilege level allows updating specified by the purpose information The specific EFLAGS bits, the TMASK register 248 will be configured with a permission to update one of the specific EFLAGS bits specified by the destination information, and the flow then proceeds to block 330. In block 330 , The contents of the TMASK register and the new Η km

Ml p. 18 1238943 --m 92128964_year month-said article 5. Description of the invention (14) " --- The content of the value register TVAL performs a sum operation 'flow then proceeds to block 335. In block 335, the sum operation of block 330 causes only the EFLAGS bits allowed by the privilege level at that time to be updated. [0 0 3 9] It is worth noting that in a traditional pipeline processor, PUSHF / PUSHFD to push down the EFLAGS register to the stack memory will require a large number of processor cycles, because The action read from the eflags register is affected by the current input / output privilege level (IOpL) and the state of some specific bits in the register at the time of writing. In particular, bit, bit TC3, bit 5, bit 15, and bits 22 to 31 are reserved states' and their states cannot be changed. Furthermore, the "flag flags 16 and 17" of the EFLAGS register are not copied. On the contrary, the values of these flags are cleared from the EFLAGS register stored in the stack memory. [0040] When a x86 processor operates in virtual 8086 mode and the fl / O privilege level (IOPL) is less than 3, the execution of a pusHF / pusHFD instruction will inevitably lead to a general protection ion f , U It) or abnormal. However, in the true addressing mode, and the ESp register or the SP register is equal to 1, 3, or 5, a PUSHF / PUSHFD instruction

Execution will inevitably cause the processor to stop functioning due to lack of stack memory space. [00 0 1] In today's pipeline microprocessors, such as processor 100, the execution of any PUSHD / PUSHFD instruction will result in the generation of several micro-instructions. First, a microinstruction will be executed to move the EFLAGS register to the temporary register; then, another microinstruction will be executed to

1238943 Modification Ά% 921289B4 V. Description of the invention (15) Clear the VM bit and RF bit; Then, execute another micro instruction to determine the current I / O privilege level (Ι〇η), so that the processor can Know if it should generate 'f' or stop operation; finally 'execute to store the EFLAGS in the stack storage. " [0 042] The aforementioned traditional microprocessor has a very significant deficiency, that is, it must execute a large number of micro instructions to complete the push of sh EFLAGS to the stack memory. Some of these many micro-instructions are used to get the current I / O privilege level (IOPL), it is necessary to move the contents of the eflags to the micro-instruction of the heap f memory, and others The order is below. It is also necessary to clear some specific bits of EFLAGS first. J is: However, many micro-instructions are generated because of the current pipeline processor architecture, which cannot be completed. The storage operation refers to the execution of f. Today's runtime logic allows only one access operation to be performed. Because of &, the execution of any instruction that includes an operation of type U = of a command must produce two consecutive "々" sets, and the execution of the two consecutive microinstruction sets requires: U,? Cycles. Under an operating system, such as Microsoft TV, the parent and the human respond to a subroutine, the EFLGS register must be stored in the stack, so if the execution of the push-down EFUGS register to the stack is reduced, Time will help improve performance. Σ ^ 043] The processor 400 in FIG. 4 provides a single microinstruction, namely Move (MFEF), to move the contents of the EFLAGS register 414 to the registers. As shown in the figure, the execution of the execution phase (data / ALU phase) Π ·· Page 20 1238943 __Case No. 92128964__year month day_correction__ V. Description of the invention (16) Logic 416 and a load-ALU storage The pipeline architecture enables one of the push-downs of EFLAGS to be completed in a single instruction cycle. Therefore, the performance of the processor can be significantly improved. [0 044] The processor 400 includes an extraction phase 402, and within the extraction phase 402 Contains a fetch logic 404 (in struction fetch logic) ° An instruction pointer 408 (instruction pointer) is coupled to the fetch logic 404 to instruct the fetch logic 404 to a specific position in the instruction memory 406 to fetch the current instruction. [0045] 当The fetch logic 404 fetches a macro instruction, for example, a PUSHF / PUSHFD instruction 'The translator in the translation phase responds to generate a comment ef micro instruction'. The micro instruction is used to execute a temporary storage from EFLAGS during the data / ALU-execution phase. [0 046] As shown in Figure 4, the MFEF microinstruction is sent to the translation instruction queue (XIQ) 419, and then reaches one of the MFEF registers 420 in the temporary storage stage 422. The storage stage 422 includes a temporary file 424, which stores the architecture state of the processor 400. The temporary file 4 2 4 includes a stack index register ESP 426. The temporary phase 422 also includes the 0P1 temporary Register 428 and 0P2 register 430. The addressing phase 431 is next to the temporary storage phase 422. The addressing phase 431 is used to calculate the address of the stored values, so that these values can be retrieved from memory and written. [0047] The contents of the MFEF register 420 The content is sent to and stored in the corresponding MFEF register 432 in the loading stage 434. The loading stage 434 includes loading / positive logic 436. As shown in the figure, the manning / correcting logic 436 is

1238943 __Case No. 92128964_ Year, Month, Day, Rev. V. Description of the Invention (17) Connected to the 0P1 register 428 and 0P2 register 430 of the temporary storage stage 422. The load / adjust logic 236 is also coupled to the data memory 438. The output of the load / adjustment logic 236 is coupled to the OP3 register 440. As shown in Figure 4, the contents of the OP1 register 428 and the OP2 register 430 in the temporary storage stage 422 are transmitted downward to the OP1 register 442 and the OP2 register 444 in the loading stage 434, respectively. ^^ 0048 ] MFET register 422, OP1 register 442, OP2 register 444 and OP3 register 440 are all connected to the data / ALU-executing logic 416 of execution stage 418, so that they are stored in these registers Any of these values may be provided to the execution logic 416. [0 0 4 9] The processing of the M F E F microinstruction from the translation stage 412 to the data / ALU-execution stage 418 is discussed in detail below. When the translator 410 receives a PUSHF or PUSHFD instruction, the translator 410 generates and outputs an MFEF microinstruction in response. The MFEF microinstruction instructs the microprocessor 400 to perform adding and reading operations. The MFEF microinstruction also instructs the stack index register ESP 426 to read the EFLAGS register 414, and dynamically changes its efugs image to A function of this active mode. Then, the E F L A G s image is stored in a stack memory in the memory 445. [005 0] The execution logic 416 of the data / ALU-execution stage 418 includes a privilege register PRIV 446, which is an IOPL that stores the currently executing instructions. The privilege register PRIV 446 is coupled to the FMASK register 448. Therefore, the current 10PL can be input for one of the FMASK registers 448. The EFLAGS register 414 is coupled to the FM ASK register 448 and provides & a second input to the FMASK register 448. Execution logic can

1238943 Case No. 92128964 V. Description of the invention (18) Provide a mask, namely FMASK. When a liver microinstruction is executed, the mask is dynamically generated. In a specific embodiment of the present invention, the mask user: the number of bits is equal to the number of bits in the EFLAGS register 414. The preparation of a special mask bit means that the mask bit can be updated under the current privilege level of the pR JV register 446, otherwise, if a specific mask bit is not If it is set, the mask bit cannot be updated. The execution logic 416 accesses the current operation mode from the privilege register PRIV 446, and accesses other bits from the EFLAGS register 414. After that, read the contents of the EFLAGS register 414, perform an AND operation on the contents and FMASK, and store the result ^ A result is temporarily stored 4 = 52 H says that the output terminal of the FMASK register is Tap to one of the AND gates 450 & and the other EFLAGS register 414 of the AND gate 450. 'Ding handle mourner [0051] In the next machine cycle, the result is written into the memory :: device T; the address is pointed by the ESP register 426 = storage is not necessary, because in its Immediately after :: The temporary storage will be provided to the storage stage 4 5 6 stored in, Luo & ^ ^, middle, and the EFLAGS image will be stored when the result is 5 Hai. Store ^ 4, so the stack memory storage logic 454 which does not need temporary memory 458 will store the result in [0052] processor 400 can be executed in a single. As a result, this treatment has two: * The output has increased significantly. ~ A% and [0 053] Now please refer to Figure 5, which shows a different flow chart for describing micro

1238943 Amendment Month Case No. 92128QR4 V. Description of the Invention (19), the processor 403 performs an operation to read the EFLAGS register according to the present invention: the operation is to execute _ push down to the stack memory. According to a specific embodiment of the present invention, the fetcher 404 fetches a set of pushF * PUSHFDs instructions from the instruction memory. In this case, a fetched instruction will be transferred before it is transferred to the stack memory and will be It is first required to read from one of the EFLAGS registers 414, as shown in block 500 at the beginning of the process. In block 505, the translator 410 translates the macro instruction into an MFEF micro instruction. The MFEF micro instruction is configured to complete reading from one of the EFLAGS registers in a single micro instruction cycle. Proceed to block 51. In block 510, an EFLAGS mask is generated in the FMASK mask register 448. In a specific embodiment of the present invention, the number of bits of the EFLAGS mask is equal to the number of bits of the EFLAGS. Therefore, in The bits in the EFLAGS mask in the FMASk register have a one-to-one correspondence with the bits in the EFLAGS register. In the process of generating the eflAGS mask in block 5 1 5 'Execution logic 4 1 6 will check the current privilege level and set the bits of the mask' The set mask bits correspond to The special EFLAGS bit allowed by the specific privilege level can be updated. As for other mask bits of the mask that correspond to the EFLAGS ^ elements that are not allowed to be updated in the specific privilege level, 'the state is not set.' Or set its value to 0, and the flow then proceeds to block 520. In block 520, the mask is summed with the contents of the efugs register, and the flow proceeds to block 525. In block 5 2 5, write the result of the sum operation to the stack memory. [0054] In the description of FIG. 2 and FIG. 3 above, it describes a device and method for enhancing a processor to execute a write to an EFLAGS register. Page 24 1238943 Amendment Tea 1289fi4 V. Description of the Invention (20) Also in the description of Figure 4 and Figure 5 above, the 1-in processor executes the reading from the muscle-like register.

What ’s more, the write and read operations can be performed in one instruction cycle: instead of: as in traditional processors, multiple cycles are required to complete the second. [COM] Although specific embodiments of the present invention have been described Such as = L = 5 soil suffer: here. The present invention can be implemented not only in hardware, but also through an identification code (such as' computer-identifiable code, data, etc.) specifically implemented by a computer that can use (eg, identifiable) components. The function of the invention is realized by testing. For example, the present invention can be implemented by using diandian code. General programming languages (for example, C, C +: ", etc.), GDSII database; hardware description language (Hardware, description languages, HDL),: Veril〇g HDL > programming and / or circuit (:) is a private I in the field of surgery, etc. can be applied to any known computer can be used (for example, identifiable) element : Second, the use of components include: semiconductor memory, magnetic disks, optical lambda M'DVD, M, etc.), and as a computer can use (for example, recognizable) transmission components (for example, carrier waves, or include Ϊ The position is: the body or the ratio ▲ type component) concrete realization-computer information in, s and, the computer code can be uploaded on the communication network: hemp :: 5 1: the road includes the Internet and corporate networks Road. Understandable is f if W its structure can be built into the processor's computer code (L, GDSn, etc.), and transferred to the hardware 1 Ι ^ ΗΠ page 25 1238943

The present invention can also be implemented by a hardware and computer program _ 銮 号 92128964_ V. Description of the invention (21) It can be realized by the combination of the code which becomes part of the integrated circuit. [0 0 5 6] Furthermore, although the present invention and I a detailed description from the purpose and characteristics of the human body, other specific embodiments still cover the name “Tai Huan” “The set point has been detailed and strictly covers the scope of the present invention [0057] Finally The specific embodiment of the present invention has been described as the previous invention is not limited to this. Only the above is: Shi embodiment, when it is not possible to limit the invention of the present invention J Jiashi this technology Those who use or manufacture the Tiangu / Department of the present invention to make the same changes in the scope of the conventional benefits and the body green Ming ^ τμ μ ^ I decoration, will still not lose the gist of the present invention ^ and Θ; guess Both arsenic and range should be considered as the further implementation status of the present invention.

Page 26 1238943 ^ S_92128964 Brief description of the drawings [Illustration of the invention] [0 0 1 2] The present invention combines the following description and the attached drawings, the second, eighth purposes, features and advantages, as shown in [0013] A series of ϊυ will get a better understanding: pipeline phase; block diagram 'which describes a traditional microprocessor [0014] Figure two series is a specific embodiment; block diagram which describes the microprocessing of the present invention [0 0 1 5] Figure three series [0 0 1 6] Another specific embodiment of the figure four series [0 0 1 7] Figure five series are explanatory diagrams. The operation of the processor describes the flowchart of the micro-processing of the flow chart of the operation of the present invention. The description of the flow chart of the processor is as follows: 1 0 〇 pipelined microprocessor architecture I 0 5 extraction phase II 〇 translation phase 11 5 temporary storage phase 120 Addressing phase 125 DATA / ALU phase (execution phase) 1 3 0 write back phase 2 0 0 processor 2 0 2 fetch phase 204 instruction fetch logic 2 0 6 instruction memory

1238943 _ Case No. 92128964_ Year, month, and day correction diagram, simple description 20 8 instruction indicators 2 1 2 translation stage 2 1 0 translator 22 2 temporary stage 224 temporary file 23 2 loading stage 23 6 loading / correction logic 238 Data memory 216 DATA / ALU phase 2 5 4 result 3 0 0 ~ 3 3 5 flow chart 4 0 0 processor 402 fetch phase 404 instruction fetch logic 406 instruction memory 408 instruction index 4 1 2 rendering phase 4 1 0 rendering 4 2 2 Temporary stage 424 Temporary file 431 Addressing stage 434 Loading stage 436 Loading / adjusting logic 438 Data memory

Page 28 1238943 Case No. 92128964 Rev. Date Brief description of the diagram 418 DATA / ALU phase 4 5 2 Results 456 Storage phase 454 Storage logic 445 Stacked memory in memory 5 0 0 ~ 5 2 5 Flow chart

Claims (1)

1238943 ----- Case No. 92128Qfi4 6. Scope of Patent Application year 1. A method of performing a write operation to a multi-bit flag register in a processor, the method comprising: receiving a macro instruction to a translation stage, the macro instruction requires a write to The multi-bit flag register; and generating a micro-instruction from the translation stage, the micro-instruction is configured to complete the writing to the multi-bit flag register in a single write cycle. 2. The method as described in item 1 of the scope of patent application, the method comprising: generating a flag mask. 3. The method as described in item 2 of the scope of patent application, the method comprising: performing a logical "and" operation on the flag mask with a pre-specified operand to produce a result. 4. The method as described in item 2 of Shenyan's patent scope, the method comprising: storing the result in the multi-bit flag register. 5. The method according to item 1 of the scope of patent application, wherein the processor is an X 8 6 processor. 6. The method as described in item 1 of the scope of patent application, wherein the ten-bit multi-bit flag register is an EFLAGS register. 7. The method as described in item 1 of the scope of patent application, wherein the macro instruction is one of the following instructions: POF, POFD, CL1, ST1, CLC, STX, CLD, and STD 〇 more than one bit A method for the read operation of the flag register, the method includes: ㈣ϊ 2: set instruction to a translation stage, the macro instruction is required to read from one of the flag registers of the 70th bit; as well as Page 30 1238943 _Case No. 92128964_ Rev. Year_6. The scope of the patent application generates a micro instruction from the translation stage. The micro instruction is configured to complete the slave multi-bit flag in a single write cycle. The reading of the register 0 9. The method as described in item 8 of the scope of patent application, the method includes generating a flag mask, the flag mask including privileged information, which is about the During a read operation, the bits in the multi-bit flag register are set as bits that can be updated according to a current privilege level. 10. The method as described in item 9 of the scope of patent application, the method comprising: performing a logical "and" operation on the flag mask and the multi-bit flag register to produce a result. 11. The method according to item 10 of the patent application scope, the method comprising: storing the result in a stack memory of a memory. 1 2. The method according to item 8 of the scope of patent application, wherein the processor is an x86 processor. 1 3. The method according to item 12 of the scope of patent application, wherein the multi-bit flag register is an EFLAGS register. Page 31