TW200406684A - Apparatus and method for masked move to and from flags register in a processor - Google Patents

Abstract

A method and apparatus are provided for writing to, and reading from, the EFLAGS register in a processor. For a particular write to EFLAGS request, a mask is generated using destination information for the write and privilege level information for the write. The mask is then ANDed with EFLAGS new value information and the result is written to the EFLAGS register in a single instruction cycle. For a particular read from EGLAGS request, a mask is generated using privilege information for the read to specify those bits of EFLAGS which can be updated during the read. The mask is then ANDed with the contents of the EFLAGS register and the result is stored in a stack in memory.

Description

200406684 V. Description of the invention (1) [Comparison with related applications] [0 0 0 1] The priority application of this application is based on the US patent application

Case No. 60/345455, Application Date: 1 0/23/200 1, Patent Name: " APPARATUS AND METHOD FOR MASKED MOVE TO FLAGS REGISTER ". [Technical Field to which the Invention belongs] [00 0 2] This invention is The area of execution of computer instructions, especially _

A device and method for reducing the instruction cycle of writing / reading EFLAGS register. / [Prior art] [0003] In a x86 pipeline microprocessor, execute an instruction written to the EFLAGS register (for example: popF / popFj), CLI / S Dingong, CLD / STD, CLC / STC) The number of cycles required is quite large. Because the action of writing to the EFLAGS register is affected by the current I / O privilege level (10PL) and the state of some bits in the EFLAGS register at the time of writing. Under the Microsoft Windows R operating system, each time a subroutine has a response, the EFLAGS register must be retrieved from the mother stack storage, resulting in a significant operating system delay. [0004] Therefore, the present invention provides a microprocessor operation technology to reduce the delay associated with executing an instruction written to the EFLAGS register, such as an unstack (P0P) instruction.

[0055] Meanwhile, in an x86 pipeline microprocessor, the EFLAGS

200406684 V. Description of the invention (2) ~ The temporary register is stored in one of the stacked registers, the push instruction (PUSGF / PUSHFD), which requires a considerable number of cycles. Because the state of the bits read from the EFLAGf register and the subscription status of the microprocessor are subject to the current I / O privilege level (IOpL) & the specific bits in the EFLAGS register The influence of Yuan's state when pushing. Under Microsoft's operating system, each time a subroutine is responded, the "register must be stored in the stack memory, resulting in a significant system delay. V ,, [000 6] Therefore, the present invention provides a microprocessor operation technology to reduce the delay of executing the instructions of a to buy the EFLAGS register and storing the delays from J to the heap $ memory, such as push instructions. [Summary of the Invention] [0007] A method in a processor. This method requires writing to a register including the use of the turn to a single write and also including the generation of arithmetic and multi-bit flag registers [0008] In the present invention One of the multi-bit flags includes the use of a micro-bit flag temporary translation stage to generate a flag mask to complete the calculation, to generate a temporary register, and for the EFLAGS, the present invention can be used in Specifically, one of the registers of the processor on the temporary register is a microinstruction to the multiple bits and the result is used in the specific register. In the example, a one-to-one macro translation is performed, and the micro flag flags the flag. The results are written with the embodiment of the present invention. This command is temporarily masked by the register and is immediately hit. The method that is provided in the microcomputer to receive a method also includes I and is in the state. This method is intended to be loaded into the multi-bit flag instruction. Cycle completes a write to the

Page 7 V. Description of the invention (3) EFLAGS register, because [0009] copy / Ming = / effect to reduce the processor's delay on the-multi-bit flag register-body / access The present invention provides a method including the use of a microprocessor. In this method, the bit flag register is 1 ^, ㈣, to receive-request to read this stage to generate a micro-finger ♦; 2: 2: The method also includes using the translation; complete reading the multiple bits Yuan Banner; Department = Dagger-Writing Week Under-Current Privilege Level; The right information is about the device which is suitable for updating. The flag flag temporary flag mask And a predetermined operation and = method further includes using the method further including storing the result η ;; -result. The party [ooun in the present invention ‘: right :; one of the bodies is stacked in a reservoir. The delay of the processor of the fetch operation ::;: less; delay due to the stack memory push-down performed by the EFUGS reader] delay: = = == stored to complete the _ stacks in the -single-instruction cycle; [Oon] Other objects and advantages of the present invention

The chart attached to Ik should be more clear. The following description is provided in the context of a specific embodiment and its necessary conditions, so that those skilled in the art can use the description. However, various modifications made to the preferred embodiment are obvious to those skilled in the art, and the principles discussed in this article—Parahara, 200406684, 5. Description of the invention (4), can also be applied to other Examples. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but has the widest scope consistent with the principles and novel features disclosed herein. [0019] Please refer to FIG. 1, which is a block diagram depicting a conventional pipeline microprocessor 100. The microprocessor has an extraction stage 005, a translation stage 110, a temporary storage stage 115, and a certain address stage. 12 o, a dat / ALu or execution stage 125, and a write back 13 o stage. [0020] When in operation, the fetch stage 105 fetches macro instructions from memory (not shown) for use in The microprocessor 丨 〇〇 executes. The translation stage 丨 丨 〇 translates the extracted macro instructions into corresponding micro instructions. [0 0 2 1] Each micro instruction is used to command the microprocessor 丨 〇〇 Execute a special sub-task, and this sub-task is part of completing all operations of an extracted macro instruction. The temporary storage stage 丨 5 is retrieved from a temporary file and designated by the micro instruction The operand is used by the subsequent stages in the pipeline. The addressing stage 1-20 calculates the memory address specified by the microinstruction 'for data storage and retrieval operations. Qj) ata / ALU stage 125 does not exist Perform the arithmetic logic unit (ar ithmeti ^ 10gic unit (ALU) operation, that is, using the memory address that was calculated in the addressing phase 120 to read data from or write data to the memory. Write back stage 丨30 writes a data read operation or an execution result of an ALU operation to the temporary file. Therefore, reviewing the entire process, the extraction stage 丨 05 extracts macro instructions, and these macro instructions pass the translation stage 11 〇 is decoded into micro-instructions, and the translated micro-instructions then flow through the 11 5 -1 30 stage to perform the operation, thus constituting the micro-processing

200406684 V. Description of the invention (5) Pipeline operation of device 100. [0022] To improve understanding of string processing in microprocessors, the discussion will use a standard nomenclature for x86 microprocessors. However, those skilled in the art will find that the registers and macros using the x86 architecture are limited to illustrations, other microprocessors are 7 years old, and Yongzhuo can also be used as an example. [0023] The Data / ALU phase 125 includes the EFLAGS register 132, which

E F L A G S register 1 3 2 stores the state of the processor. For conditional instruction loops and conditional instruction jumps, the EFLAGS register 1 32 can be modified by many instructions and can be used as a comparison parameter. Each bit of the EFLAGS register holds the status of specific parameters of the last instruction, as shown in Table 1 below, which shows the 32 bits of the EFLAGS register and the function of each bit.

Page 10, 200406684 V. Description of the invention (6) Form EFLAGS register bit number name function 32:22:00 Reserved " Connect to low potential " 21 ID ID flag 20 VIP virtual interrupt pending 19 VIF virtual interrupt flag Standard 18 AC registration check 17 VM virtual mode 16 EF reply flag 15 0 " Connect to low potential " 14 NT nested 1 as flag 13:12 IOPL I / O privilege level 11 OF overflow flag 10 DF direction flag Standard 9 IF interrupt flag enable 8 TF trap flag 7 SF symbol flag 6 ZF zero flag 5 0 11 connected to low potential 11 4 AP auxiliary carry flag 3 0 " connected to low potential 11 ΚΙ page 11 200406684

[0 024] In a today's pipeline microprocessor, such as a processor, any one of the instructions (that is, POPF / POPFD, CLC / STC, CLD / STD'CLI) written to the EFLAGS register is executed. / STI) requires a significant number of machine cycles to execute. Because the action written to the EFLAGS register is subject to the current I / O privilege level (I0pL) & EFUgs

The influence of the status of some bits at the time of writing, especially bit 丨, bit ... 3, bit 5, bit 15, and bits 22 ~ 31 are reserved (Ueserved), and their status cannot be Was changed. In addition, when the processor is operating in privileged level 0 protection mode (also known as real address mode), all non-reserved bits can be modified except VIP ′ VI F and VM. The VI P and V IF flags must be cleared, and the 0 flag must be present.

[0025] The execution of any of the aforementioned macro instructions that write data to the efugs register 132 will result in the generation of some micro instructions. In detail, a micro-instruction will be executed first to determine the current I / O privilege level (IOPL), and some subsequent micro-instructions will read the current status of certain eflags bits, such as: VM, RF, IOPL, ΠP, VIF, and IF, and set the bit το state to a new value to be written to EFUGS. A final microinstruction writes the new value to the EFLAGS register 132. [0 02 6] The aforementioned traditional method of updating the EFUGS register has a very significant deficiency, that is, it must execute a large number of micro instructions to complete writing to the EFLAGS register. Because there are several micro-instructions that must be generated and processed, it will take a lot of time to update the EFUGS register as described above. 200406684 V. Invention Description (8), which reduces the performance of the microprocessor. [0 0 2 7] The present invention notices that under the Microsoft Windows R operating system, each time a subroutine has a response, the EFLAGS register must be pulled out of the stack memory, and this situation also Occurs on many desktop applications that are commonly used today. Since this type of instruction has been widely used by the public, there is an urgent need to reduce the execution time of these instructions to a minimum. [0 028] The purpose of the present invention is to reduce the time required to execute a write to the eflags temporary storage. The number of order cycles. To achieve this, the present invention provides a device and method for dynamically generating an EFLAGS mask. The mask performs logical AND operation on a specified operand in combination (that is, unstacks the EFLAGS register 'or selects the EFLAGS bit state), and writes the result to the EFLAGS register. The new processor disclosed here has the following advantages; the processor uses a new microinstruction, namely Move To EFLAGS (MTEF). This microinstruction combines the dedicated logic of the execution stage to make the action written to EFLAGS This can be done in a single instruction cycle. [0 0 2 9] Please refer to FIG. 2 ', which is a block diagram depicting a processor 200 using a single microinstruction, namely Move τοEFLAGS (MTEF), in a single instruction cycle. Finish writing to the EFLAGS scratchpad. The processor 2 0 0 includes an fetch phase 2 0 2, and the fetch phase _ 202 includes an fetch logic 204 (instruction fetch logic) which is connected to the instruction memory 2 0 0 an instruction pointer 208 Is coupled to the fetch logic 204 to instruct the fetch logic 204 to a specific location of the memory 206 to fetch the current instruction.

Page 13 200406684 V. Description of the invention (9) [0 03 0] When the extraction logic 204 fetches a macro instruction, such as POPF / POPFD, CLI / STI, CLC / STC, or CLD / STD instruction, translate

In response, the translator 210 of stage 2 12 generates a MTEF D, s microinstruction. This instruction will execute an action of moving to temporary storage of EFLAGS in the data / ALU-executing stage 2 1 6. In the MTEF D, S microinstruction, s is a source stop, and the source stop instruction will be transferred to the data source of the EFLAGS register 214; D is a destination stop, and the purpose field is designated in the EFLAGS temporary The bit in which the memory 214 is intended to be written. [0 03 1] Here, before discussing the processing of the jjTEF microinstruction, the rest of the architecture of the processor 4 will be used. As shown in Figure 2, the% τ e f d, § mechanical deduction order is sent to the translation instruction line (X I q) 2 1 §. Then, the μ τ £ ρ j), S, instruction flows to the MTEF register 22, which is one of the temporary storage stages 222. The temporary storage stage 222 is used to store the architecture state of the processor 200. The temporary file 224 includes an ESP architecture register 226. As shown in FIG. 2, the temporary storage stage 222 also includes an OP1 register 228 and an OP2 register 230. Dagger [0 032] The temporary storage stage 222 is coupled down to the loading stage 2 3 2 via the positioning stage. The processor 200 uses a conventional positioning phase 2 50 to calculate the addresses used by the processor 200 to process the instructions. The contents of the MTEF register 220 in the positioning stage 222 are sent to and stored in the corresponding MTEF register 234 in the loading stage 232. The loading phase 232 includes loading / correction logic 23 6. ′ The loading / correction logic 236 is coupled to the temporary storage stage 222-1 = 2, 8 and 0 P 2 register 2 3 〇. The load / adjust logic 2 3 6 is also coupled to the lean memory 238. The output of the load / adjust logic 236 is coupled to the OP3 register 240. As shown in Figure 2, the temporary storage stage 222-1 register 200406684 V. Description of the invention (228) and the 0P2 register 230 are transferred down to the OP1 register 242 of the loading stage 232, respectively. And OP2 register 244. [0033] The processor 200 further includes a data / ALU or execution stage 216. The execution stage 216 includes the aforementioned EFLAGS register 214. The execution phase 216 also includes a TVAL register 246 and a TMASK register 248, and the contents of the TVAL register 246 and the TMASK register 248 are combined by a sum operation of a sum gate 250, and The result of the operation is stored in the EFLAGS register 214. The following discussion will be about the sum operation and the mask operation provided by the TMASK register 2 48. The execution stage 2 1 6 also includes a privilege level register PR IV 252. The privilege level register provides the privilege information of the instructions currently being executed by the "register 248". The results of the execution of these instructions are The results are sent to the result register 2 5 4 and the results are written to the register file 2 2 4 via a result bus (not shown). [0034] As mentioned before, the extraction logic is used for the response. 204 is provided to one of the translators 210 and the extracted p0pF / p0pFD, CLI / STI, CLX / STC, CLD / STD macro instructions. The translator 21 generates a single micro instruction, namely MTEF D, S And send the MTEF D, S microinstruction to the translator queue (X 丨 q) 2 丨 6 coupled to the translator 21 0, and then to the translator queue (XIQ) 216 temporarily Storage stage 222. The zero order micro instruction includes a source field, and a field d. The field is used to specify the bits to be written in the EFLAGS register 2 1 4. For example, if D = 〇, the field of this item will specify a write to the carry flag CF, the carry flag bit, as shown in the table 'is EFLAGS register 〇 Element. In another embodiment, d = 9 to specify if a write to the EFLAGS register the bit, d = a specified 1〇

Page 15 200406684 V. Description of the invention (11) The DF bit written into the EFLAGS register. In the MTEF D, s microinstruction, one of the EFLAGS register 214 pulled out of the stack memory is popped (D = 31). [0035] The source block s of the MTEF microinstruction specifies the state of the bits written to the EFLAGS register 214. For example, if 0 = 10, Hong 0 is commanded to the processor 200 to clear the DF. If D = 0, s-j, the command processor 200 is set to set the carry flag. In other words, in the MTEF microinstruction, s = 0 means that the destination bit is cleared, and S = 1 means that the destination bit is set. For a POP EFLAGS instruction, the instruction ignores the S block. [0036] When writing to the EFLAGS register, the execution logic 256 in the data / ALU execution stage m is a mask to ensure that only the correct = meta position is written to A. When an MTEF micro instruction is executed, the contents of the TM ^ K register 248 are dynamic. The execution logic of the data / ALU execution phase 2 to 6 is 256, which accesses the status from the privilege register PRIV 252, and the state where the LA bit 214 accesses other bits. Provided 乂 Temporary I ^ TVAL 246, if it is not a value of 5 columns, it is the EFUGS register read from the stack memory during the loading phase 2 3 2. As shown in the second figure, TVAL and TMASK are connected together with gate 250 and the result of the fj 250 operation is written to EFLA]) S register 214, which is advantageous: it can be configured to change only Some bits, and the certain bits are: as a function of the specific current operation mode read by the PRIV register, in this specific embodiment, the highest privileges held by the instruction, etc. * Level instruction * has the highest tolerance when updating the μ-private position of the EFLAGS register. Refer to the lower privilege level 200406684 V. Description of the Invention (12) ---- There are more restrictions on updating the EFLAGS register. The highest privilege level is 0. In a specific embodiment of the present invention, the number of bits in the mask is equal to the number of bits in the EFLAGS register. When a specific mask bit is set, it means that the mask bit is below the current weight level of the pRIV register 252, and can be updated. On the contrary, if a specific mask bit is set, Then the mask bit cannot be updated. In a word, the mouth provides the specific value written to EFLAGS, and TMASK determines whether a write operation is allowed according to the privilege level of the specific instruction stored in the PRIV register 252. [00j7] The present invention enables an instruction written to the EFLAGS register to be completed in a single instruction cycle, thereby significantly increasing the throughput of processing. Wang Yi [j038] Please refer to FIG. 3, which shows a flowchart for describing the outline of the high-level processing flow of the micro 200 in accordance with the present invention to execute a J-diff written to the efugs register. The process starts at block 300, where 彳 < Yi Yimei extracts a macro instruction, for example: =, CLC / STC, or CLD / STD, and the process then proceeds to block 305_. In block 305, the translator 2110 translates the macro instruction into a microinstruction that requires $ 仃 to be written to the EFLAGS register 214, and the flow proceeds to block ^ 10. At block 310 ', in the EFUGS mask register ιφμγ; an EFLAGS mask is generated, and the flow proceeds to block 315. In Fang \, as described in the text, a new value will be written to EFLAGS, and the execution result of the 4 macro instruction will be loaded into the τ procedure and then proceeded to the square paste. In block 320, the purpose; the message will be provided | for 200406684 V. Description of the invention (13): TMAjK register 248, and the flow then proceeds to block 325. At block 325, the privilege level is assigned to the surface register m. If the specific EFLAGS bits are specified by the information of the privilege, etc., the register 248 will be configured with a permission to update the information by the destination The value of these specific muscle dislocations-the value, the process then proceeds to f ghost 330. In block 33, an operation is performed on the contents of the TMASK register and the contents of the new exchange and the benefit TVU, and the flow proceeds to the second. In block 335, the sum of block 330 causes only the EFLAGS bits allowed to be updated by the current guarding privilege level to be updated. [0 039] It is worth noting that, in a traditional pipeline processor, executing P ^ SHF ^ PUSHFD to push down the EFLAGS register to the stack memory will result in a large number of processor cycles of 1. Because staging from that EFLAGS

The behavior of the device is affected by the current I / O privilege level (IopL) and the state of the πlAGS register 'the specific bits at the time of writing. In particular, bits', bits t13, bits 5, bits 15, and bits 22 to 31 are reserved.

Evil, and its state cannot be changed. Furthermore, the VM fRF flags of the EFLAGS register (/ LE 16 and bit 17) have not been copied. On the contrary, the values of these flags are from the virtual image of the EFLAGS register stored in the stack memory. Clear it out. [0 040] When a χ86 processor operates in virtual 8086 mode and its 1/0 privilege level (IOPL) is less than 3, the execution of a PUSHF / PUSHFD instruction will inevitably lead to a general protection error (genera 1 pr ^ ec ^ 丨 〇η f ^ u It) or abnormal. However, in the real addressing mode and the ESp register or the SP register is equal to 1, 3, or 5, a puSHF / puSHFD instruction

Page 18 200406684 V. The implementation of invention description (14) will inevitably cause the processor to stop operating due to lack of stack storage space.

[0 0 4 1] In a pipeline microprocessor today, such as the processor 100, the execution of any PUSHD / PUSHFD instruction will result in the generation of several micro instructions. First, a microinstruction will be executed to move the contents of the EFLAGS register to a temporary register; then, another microinstruction will be executed to clear the VM bit and the RF bit; then, execute Another microinstruction determines the current I / O privilege level (IOPL), so that the processor can know whether an exception should be generated or the operation should be stopped. Finally, a final microinstruction is executed to store the EFLAGS in the Stacked storage. [〇 〇 4 2] The aforementioned traditional microprocessor has a very significant deficiency, that is, it is necessary to execute a large number of micro instructions to complete the push of EFLAGS to the stack memory. Among the many micro-instructions, some are used to obtain the current 1/0 privilege level (I0PL), and it is necessary to move the contents of the EFLAGS to micro-instructions suitable for storage, and others are used to order names I, of W 'It is necessary to clear some specific bits in advance. 1 疋 There are still many micro-instructions generated because today's pipeline processors Ben =', can not complete a suitable ALU operation. 2 instructions with a storage operation! ° The execution phase logic of this day only allows the execution of an ALU and a record. Therefore, any instruction that includes an operation of an ALU type and a Jtp! = Type operation The execution must be performed in two, two, and seven fish sets, and the execution of the two consecutive microinstruction sets requires a user cycle. ☆ Under an operating system, such as Microsoft Windows, In each response to a subroutine, the EFUGs register is Xiang 200406684. V. Description of the invention (15) is pushed down to the stack storage, so if the push down EFLAGS temporary storage can be reduced to the heap storage Processor execution time will help improve processor [0043] The processor 400 in FIG. 4 provides a single microinstruction, which is Move

From EFLAGS (MFEF) to move the contents of the EFLAGS register 414 to the stacker. As shown in the figure, the execution logic of the execution phase (data / ALU phase) 416 and a load-ALU storage pipeline architecture enable one of the EFLaGS pushdowns to be completed in a single instruction cycle. Therefore, the performance of the processor can be significantly improved. [0044] The processor 400 includes an fetching stage 402, and the fetching stage 402 contains an instruction fetch logic 404 which is connected to the instruction memory 406. An instruction pointer 408 (instruction pointer) is coupled to the fetch logic 404 to instruct the fetch logic 404 to a specific location in the instruction memory 406 to fetch the current instruction. [0 045] When the fetch logic 404 fetches a macro instruction, such as a PUSHF / PUSHFD instruction, the translator in the translation phase responds to generate an mfef microinstruction 'the microinstruction is used to execute a data instruction in the data / ALU-execution phase Moved from EFLAGS register 414. [0 046] As shown in FIG. 4, the MFEF microinstruction is sent to the translation instruction queue (XIQ) 419, and then reaches one of the MFEF registers 420 in the temporary storage stage 422. The temporary storage stage 422 includes a temporary storage file 424, which stores the architectural status of the processor 400. The temporary storage case 4 2 4 includes a stack index register ESP 426. Temporary stage 422 also includes 0P1 register 428 and 0P2

Page 20 200406684

Register 430. The addressing phase 431 is next to the temporary storage phase 422. The addressing stage 431 is used to calculate the addresses of the stored values, so that these values can be retrieved from and written into the memory. [0047] The contents of the MFEF register 420 are sent to and stored in the corresponding MFEF register 432, which contains 1 ## 434. The loading phase 434 includes loading / correction logic 436. As shown in the figure, the load / adjust logic 436 is connected to the OP1 register 428 and the OP2 register 430 of the temporary storage stage 422. The load / adjust logic 236 is also coupled to the data memory 438. The output of the load / adjust logic 236 is coupled to the OP3 register 44. As shown in Figure 4,

The contents of OP1 register 428 and 0P2 register 43 in the storage stage 422 are respectively

It is transmitted down to the OP1 register 442 and the OP2 register 444 in the loading stage 434. W

[0048] MFET register 422, OP1 register 442, OP2 register 444, and OP3 register 440 are all coupled to data / ALU-the execution logic 4 1 6 'of execution stage 418 makes the storage in these These values of the register can be provided to the execution logic 4 1 6. [0 049] The processing of the review microinstruction from the translation stage 412 to the data / ALU-execution stage 418 is discussed in detail below. When the translator 41 receives a PUSHF or PUSHFD instruction, the translator 41 generates and outputs an MFEF microinstruction in response. The MFEF microinstruction instructs the microprocessor 400 to perform additions and reads. The MFEF microinstruction also instructs the stacking index register.

ESP 426 goes to a to buy EFLAGS register 414, and dynamically changes its EFLAGS image to a function of the current operation mode. Then, the EFLAGS image is stored in a stack memory in the memory 4 4 5.

Page 21, 200406684 V. Description of the invention (17) [0050] The execution logic 416 of the data / ALU-execution stage 418 includes one, a right register PRIV 446, and the privilege register pRIV 446 stores the currently executing instructions. I0PL. The privilege register pRIV 446 is coupled to the FMASK register 448. Therefore, the current 101% can be input for the -8% register as one of 448. The EFLAGS register 414 is coupled to the FMASK register 448 to provide a second input to the FMASK register 448. The execution logic can provide a mask, that is, FMASK. When a financial evaluation micro-instruction is executed, the mask is dynamically generated. In a specific embodiment of the present invention, the number of bits of the mask = is equal to the number of bits 该 of the EFLAGS register 4 丨 4. When a specific mask bit is set, it means that the mask bit is below the current privilege level of the "" register 446, and it can be updated. Otherwise, if a specific mask bit is not If set, the mask bit cannot be updated. The execution logic 416 accesses the current operation mode from the privilege register PRIV 446, and accesses the state of other bits from the EFLAGS register 414. After that, the contents of the EFLAGS register 414 are read, and the contents are combined with the F port to perform a sum operation, and the result is stored in a result temporarily as 452. Suffice it to say that the output terminal of the FMASK register is one of the wide input terminals, and the other input terminals of the 450 are connected to the EFLAGS register 414. [〇〇51] In the next machine cycle, the result stored in the result temporary cry 452 is written to the address of the stack memory Ϊ Ϊ! TSP ^ # " 426 ^ ^ ° EFLAGS ^ ^ ^ ^ y is not necessary, because in the immediately following machine cycle, the storage logic of the bass is provided to the storage phase 456, so it is not not = temporary

Page 22 200406684 V. Description of the invention (18) The guard stores the image of the EFLAGS. Miao — ^ ^ ^ 豕 Storage logic 454 will store the result in the stack memory of Ji Fei 4 5 8. [0052] The processor 400 can execute the PUSHF-PUSHFD instruction. L ^ ^ Female, said Gongding Therefore, the performance and output 1 of the processor 400 have improved significantly. [0053] Please refer to FIG. 5, which shows a flowchart for describing the micro difference 40. According to the present invention, an operation to read the eflags register is executed. The operation is: Push to the stacker. According to a specific Λ embodiment of the present invention, the fetcher 404 fetches a PUSHF or PUSHFD macro instruction from the instruction memory. In this case, an fetched instruction will first request before it is transferred to the stack memory. Read from one of the efugs registers 414, as shown by block 500 at the beginning of the process. In block 505, the translator 410 translates the macro instruction into a liver micro-instruction. The MFEF micro-instruction is configured to complete reading from one of the EFLAGS temporary storage in one single micro-instruction cycle. The flow then proceeds to block 51. In block 510, an EFLAGS star is generated in the FMASK mask register 448. In the embodiment of the present invention, the muscle AGS material == the number of masks is equal to the number of bits of the EFLAGS. Therefore, in The bits in the EFLAGS mask in the ruler register have a one-to-one correspondence with the bits in the EFLAGS register. In the process of generating the EFLAGS mask in block 515, the logic is executed. 4 1 6 will check the current privilege level, and set the bits of the mask. 'The set mask bits correspond to specific EFLAGS bits allowed by the specific privilege level to be updated. As for the Other masks for EFLAGS bits that are not allowed to be updated for a particular privilege level

200406684 V. Description of the invention (19) The mask position is not set, or it proceeds to block 520. In block 52o, the flow is followed by the contents of the register-and the operation is performed. The flow together with the EFLAGS is performed in block 525, and the result of the sum operation is passed to block 525. [0054] Regarding the figure above, and FIG. 3 write the ^^ memory. This kind of enhanced processing: implementation-write people to EFLAGS temporary storage = description 1 In the above description about Figure 4 and Figure 5, the device 2 method. The processor executes a temporary cry from the EFLAGS, and the second description Tian Tian describes an addition to the write and read operations and methods. It is advantageous rather than the traditional processor I, which requires a plurality of cycles to be equal to [0055] Although specific embodiments of the present invention have been described:; = is not limited to this. The present invention can not only be implemented in hardware = the computer program code facilitates the functions of the present invention disclosed herein, or, ^ simulation, or test implementation. For example, the present invention can be implemented by the following computer code: general programming languages (eg, C, C ++, etc.); GDSII database; hardware description languages (HDL), including : VerUogh, VHDL 'AHera HDL (AHDL), etc .; or other programming tools and / or circuits (ie, illustrated) capture tools in this technical field. The computer code can be applied to any known computer-usable (eg, recognizable) components. The computer-usable components include: semiconductor memory, magnetic disk 3, optical disks (eg, CD-ROM, DVD-ROM, etc.) Etc.), and like a computer

200406684 V. Description of the invention (20) One of the specific implementations that can be implemented using (for example, identifiable) transmission elements (for example, digital, optical, or analog elements), is the included number. For its part, the computer code can transmit information through communications, including the Internet and corporate networks. ;, Upload the function or structure of the present invention can be built into the processor's power = understand that it is implemented (for example, HDL, GDSII, etc.), and it is = long form to be integrated circuit portion. The present invention can also be implemented by a combination of hard and hard code. ', Computer program [0050] Furthermore, although the present invention and its objectives, features, and detailed description, other specific embodiments are still covered by the scope of the present invention. "Finally, the present invention The specific embodiments have been described as before, and the invention is not limited thereto. The above are only comparative examples of the present invention. When the scope of the present invention cannot be limited, it is intended to provide a mature solution. ^ Those skilled in the art use or manufacture the present invention. Any equal changes and modifications made in accordance with the scope of the present application will not lose the essence of the present invention, nor depart from the spirit and scope of the present invention. It should be considered as a further implementation of the present invention.

Page 25 200406684

[Illustration of the Invention] [0012] After the foregoing description of the present invention is combined with the following description and attached drawings, [0 0 1 3] FIG. 1 is a block and pipeline stage; [0 0 1 4] FIG. 2 is a series It is a specific embodiment of a block diagram; its purpose, features, and advantages can be better understood in the configuration: 'It describes a traditional microprocessor' and it describes the microprocessor of the present invention [0 0 1 5] Figure 2 is a flowchart illustrating the operation of the microprocessor of Figure 2;

[0 0 1 6] FIG. 4 is a block diagram illustrating another specific embodiment of the microprocessor of the present invention; [0 0 1 7] FIG. 5 is a flowchart illustrating the operation of the microprocessor of FIG. . Figure number description: 1 0 0 pipelined microprocessor architecture I 0 5 extraction phase II 〇 translation phase 11 5 temporary storage phase 1 2 0 addressing phase 125 DATA / ALU phase (execution phase) 1 3 0 write back phase 2 0 0 Processor 2 0 2 fetch phase 204 instruction fetch logic 2 0 6 instruction memory

Page 26 200406684 Schematic description 208 instruction indicators 2 1 2 translation stage 210 translator 2 2 2 temporary stage 224 temporary file 232 loading stage% 236 loading / adjusting logic 238 data memory 216 DATA / ALU stage 254 Results 3 0 0 ~ 3 3 5 Flow chart 4 0 0 Processor 4 0 2 Fetch phase 404 instruction fetch logic 406 instruction memory 408 instruction index 4 1 2 translation phase 4 1 〇 translator 422 temporary storage stage 424 temporary file 4 3 1 Addressing phase 434 Load phase 436 Load / adjust logic 438 Data memory

Page 27 200406684 Brief description of the diagram 418 DATA / ALU phase 4 5 2 Results 4 5 6 Storage phase 454 Storage logic 445 Stacked memory in the memory 5 0 0 ~ 5 2 5 Flow chart

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Claims (1)

200406684 6. Scope of Patent Application 1. A method for performing a write operation to a multi-bit flag register in a processor, the method includes: receiving a macro instruction to a translation stage, the macro instruction Requires a write to the multi-bit flag register; and generates a micro-instruction from the translation stage, the micro-instruction is configured to complete the write to the multi-bit flag in the J write cycle Temporary. 2. The method described in item [Scope of patent application], which method ^ flag mask. G. Generate a 3. The method as described in item 2 of the scope of patent application, which method includes: fruit. A pre-scheduled operation is performed on the logic to perform an AND operation to generate a method. The method includes storing the processor as a multi-bit flag and the macro instruction as ST1, CLC, STC. 4 · The result of the method described in item 2 of the scope of patent application to the multi-bit flag register. 5. The method of X 8 6 processor as described in the scope of patent application 1. The method register described in item 丨 of the scope is an EFLAGS register. 7 • One of the following instructions of the method described in item 1 of the scope of patent application: P0pF, p0pFD, CL1 CLD and STD ° 8 · One method of executing from one of the multi-bit flag registers. The method includes:% # i A &… ??: owe a macro instruction to the-translation stage 'The macro instruction requires k 忒 bit Read from one of the TL flag registers; and Page 29 200406684 6. Scope of patent application A micro instruction is generated from the translation stage. The micro instruction is configured to complete the reading from the multi-bit flag register in a single write cycle. 9. The method according to item 8 of the scope of patent application, the method comprising: generating a flag mask, the flag mask including privilege information, the privilege information is related to a read operation, according to a current Privilege level, the bits in the multi-bit flag register are set as bits that can be updated. 10. The method as described in item 9 of the scope of patent application, the method comprising: performing a logical "and" operation on the flag mask and the multi-bit flag register to produce a result. 11. The method as described in claim 10 of the scope of patent application, the method comprising: storing the result in a stack memory of a memory. 1 2. The method according to item 8 of the scope of patent application, wherein the processor is an X 8 6 processor. 1 3. The method according to item 12 of the scope of patent application, wherein the multi-bit flag register is an EFLAGS register. Page 30