1237943 九、發明說明： 【發明所屬之技術領域】 本發明係’用以產生-電力開啟重置脈衝信號之電力 開啟重置電路。 【先前技術】 積體電路之使命功能可能在沒討靠的電力開啟重置電 路的情況下被反覆無常地執行。從主電壓供應源之初始電慶上 升直到主電壓供應源已經充分上升至如所預料地供應電源至一 積體電路或積體電路之-部分，電力開啟重置電路即時提供一 延遲…般而言，電力開啟重置電路之輸出係連接至執行電路 之使命功能之電路之一致能輸入。 美國專利第5,936,444之雷力龆鲂舌ga +、 1啟重置電路係憑靠著具有 令聞值電壓之電晶體。然而’具有零間值電 加CM0S製程之步驟，因而實質上提高成本。曰體〜 產“因有並非吹毛求疯地憑靠著零間值電壓電晶體以 產生功此之電力開啟重置電路之需求。 【發明内容】 本發明提供一種用以產生一雷力 度土电刀開啟重置信 方法，該電力開啟重置作於呈右一乂道 及 尸，左 虎具有剛導部分（hading part)血一 尾隨部分（trailing part)。 Pm)，、 在本發明之一個實施樣態+， 、、店 , 從兒略巴兮一電愿供雍 μ，一接地端，具有一輸出電壓並輪出電力 〃 α 輪出節點…起動電路，以及具有 ^唬之- “。起動電路係適合於初始化決 出即點之輸出電壓之^ 1237943 八之任何節點電壓’並適合於產生電力開啟重置信號之前導部 ’刀1起動電路之-例子係為電壓偵測器。信號源電路係適合於 在化號源電路之輸人之—輸人電壓超過信號源電路之—斷開點 路之-例係為電麼偵測器。產生電力開啟重置信號之電路之所 有電晶體之所有閾值電壓’係具有藉由離子植入法來調 零閾值電壓。 在某些貝把例中’起動電路包含一電壓摘測器、一電晶體 以及，接至電壓供應源與接地端之—電容器。起動電路之電壓 偵，U；r、連接至$壓供應源與接地端。起動電路之電壓偵測哭 具有連接至電容器之-輸人以及—輸出。電晶體係連接至接: 端以及電壓制器之輸出，並譬如在信號源電路產生一電力開 啟重置信號之尾隨部分之前隔絕起動電路與電力開啟重置戸 號。這種隔絕在起動電路已經產生電力開啟重置信號之前導部 分之後’以及信號源正產生電力開啟重置信號之尾隨部分時是 有用的。於此情況下，起動電路與信號源產生供電力開啟重置 信5虎用之不一致信號（C〇nfHcting &⑽1)。 在Λ一實施财，起動電路包含—電壓㈣器、-電晶體 及一電容器’藉由轉接電壓供應源至第一電晶體之一閘極，起 動電路之電壓制器之輸出產生電力開啟重置韻之前導部 分0 在另貝她例中，起動電路包含一電壓偵測器、 及-電容器，為因應電壓供應源之—持續電壓上升 心 電壓超過電壓_器之—斷開點，電壓偵測器連接接地端„1第 一電晶體之一閘極，且第一雷曰邮 弟 ％日日肢隔絕起動電路與電力開啟重 置信號。 1237943 在另一實施例中，譬如在信號源電路之輸入之輸入電壓超 過信號源電路之斷開點電壓時，信號源電路之電壓偵測器產生 電力開啟重置信號之尾隨部分。 ^某些貫施例包含一回授電晶體。回授電晶體具有連接至電 壓供應源之-第-載電流端子，連接至信號源電路之—電壓侦 測器之一第二載電流端子’以及連接至信號源電路之輸出:―、 閘極。在信號源電路產生電力開啟重置信號之尾隨部分之後， 回授電路隔絕電壓供應源與信號源電路，藉以在已產生電力開 啟重置信號之前導與尾隨部分兩者之後節約電源。因此，為因 應該產生電力開啟重置信號之尾隨部分，電壓供應源係與產生 電力開啟重置信號之尾隨部分之信號源電路隔絕。 在各種不同的實施例中，電壓供應源之一電壓上升導致一 個或多個不同響應。在—種響應下，在信號源電路之輸入之電 壓係譬如稭由將信號源電路之輸人搞接至接地端，而被設定成 低於信號源電路之斷開點電壓。在另一種響應下，信號源電路 產生與電力開啟重置信號之前導部分相符之—信號。這種相符 性在信號源電路產生電力開啟重置信號之尾隨部分時之前係有 關連性。在電壓供應源繼續上升之前，信號源電路尚未產生電 力開啟重置k號之尾隨部分。因此，在電壓供應源之繼續上升 :前’如果信號源電路產生與電力開啟重置信號之前導部分相 付之-信號，則信號源電路之輸出不需與電力開啟重置信號隔 絕。 在各種不同的實施例中，在電壓供應源之電壓上升之後， 電壓供應源之-持續電壓上升導致一響應，例如譬如藉由將反 相器之輸入耗接至電壓供應源，而將在信號源電路之一輸入之 一電壓提咼至該於信號源電路之斷開點電壓。 1237943 在本發明之—個實施樣態中，係提供—種電力開啟重置， 〜之產生方法，電力開啟重置信號具有— ϋ 分。盏m广則—部分與一尾隨部 為因應一電壓供應源之一電壓上升，此 節點電壓係被初始化，且電力開啟重置 ^夕偏 生。 里置1口唬之則導部分係被產 ιΓΓΙ些節點決定輸出節點之輸出電壓。-信號源 :路之輸入電壓係經由具有由離子植入法所調整之一非愛間值 :昼之至少一第-電晶體來設定。為因應電壓供應源之一持續 4上升，信號源電路之輸人電壓係提高至超過信號源電路之 物⑽。電力開啟重置信號之尾隨部分係從信號源產生。 於-實施例中，產生電力開啟重置信號之前導部分之步驟 匕含多重步驟。—反相11輸出係連接至電壓供應源，使反相器 之輪出電壓輸出至電源電壓之電壓。電壓供應源係經由反相器 S接至連接至接地端之_•電日日日體之—閘極，而導通電晶體。 —第二反相ϋ之-輸人係經由連接至接地端之電晶體而連接至 接地端’使在第二反相器之輸入之電壓低於反相器之斷開點。 於貫她例中，h唬源之輸入電壓係經由具有由離子植入 法所調整之一非零閾值電壓之至少一第二電晶體。第一與第二 電晶體係連接至不同電壓，例如一電壓供應源與接地端。孽如 電晶體與電阻之電路元件將第一與第二電晶體連接至不同的電 壓，藉以允許兩種不同的電壓同時被耦合至信號源之輸入電壓。 方、貝施例中，k號源產生一個與電力開啟重置信號之前 導部分相符之信號。在電壓供應源之繼續上升之前，信號源尚 未產生電力開啟重置信號之尾隨部分。因此，在電壓供應源之 繼績上升之岫，如果信號源產生一個與電力開啟重置信號之前 f部分相符之#唬，則信號源之輸出不需與電力開啟重置信號 隔絕。 1237943 許多實施例之另_ 之削後之電力開啟重置 種益處係為在產生電力開啟重置信號 电路之功率消耗是可忽略的。 【實施方式】 置二？顯7 一種電力開啟重置電路之電路圖。電力開啟重 八电、匕3目產生—電力開啟重置信號之起動電路之前導部 分’以及一個產生一雷六pq私| 电力開啟重置信號之尾隨部分之信號源電 路。起動電路包含N型雷曰邮11n Μ 孓包日日肢110、122與124;ρ型電晶體lw1237943 IX. Description of the invention: [Technical field to which the invention belongs] The present invention is a power-on reset circuit for generating a power-on reset pulse signal. [Prior technology] The mission function of the integrated circuit may be performed erraticly without the help of a power-on reset circuit. From the initial voltage rise of the main voltage supply source until the main voltage supply source has fully risen to supply power to an integrated circuit or a part of the integrated circuit as expected, the power-on reset circuit immediately provides a delay ... In other words, the output of the power-on reset circuit is a uniform input of a circuit connected to the mission function of the execution circuit. The U.S. Patent No. 5,936,444 has a thunderbolt ga +, 1 reset circuit that relies on a transistor with a command voltage. However, ′ has the step of zero-interval plus CM0S manufacturing process, thus substantially increasing the cost. "The body ~ the production" because there is no need to madly rely on the zero-intermediate voltage transistor to generate work power to open the reset circuit. [Summary of the invention] The present invention provides a method for generating a lightning force geoelectric The knife-on reset letter method, the power-on reset is performed on the right side of the gangway and the corpse, the left tiger has a hading part, a blood trailing part (Pm), and is one of the present invention. Implementation mode +, ,,, and store, from the electric power station, a power supply, a ground terminal, an output voltage and power out 轮 α, a power out node ... starting circuit, and a--". The starting circuit is suitable for initial determination of the output voltage of the immediate point ^ 1237943 Eight of any node voltage 'and is suitable for generating the leading part before the power-on reset signal. The example of the knife 1 starting circuit is a voltage detector. The signal source circuit is suitable for the input of the signal source circuit—the input voltage exceeds the signal source circuit—the disconnection point—for example, is an electrical detector. All the threshold voltages of all the transistors of the circuit generating the power-on reset signal have zero threshold voltages by ion implantation. In some cases, the 'starting circuit' includes a voltage pick-up, a transistor, and a capacitor connected to the voltage supply and ground. Voltage detection of starting circuit, U; r, connect to $ voltage supply source and ground terminal. The voltage detection circuit of the starter circuit has -input and output connected to the capacitor. The transistor system is connected to the terminals and the output of the voltage controller, and for example to isolate the starting circuit from the power-on reset signal before the signal source circuit generates a trailing portion of the power-on reset signal. This isolation is useful after the leading portion of the start-up circuit has generated the power-on reset signal and when the signal source is generating the trailing portion of the power-on reset signal. In this case, the starting circuit and the signal source generate an inconsistent signal (ConnHcting & ⑽1) used by the power supply reset reset signal. In the implementation of Λ, the starting circuit includes a voltage generator, a transistor and a capacitor. By switching the voltage supply source to one of the gates of the first transistor, the output of the voltage controller of the starting circuit generates electricity to turn on the power. Leading part 0 before setting the rhyme. In another example, the starting circuit includes a voltage detector and a capacitor. In response to the voltage supply source—the continuous voltage rises, the heart voltage exceeds the voltage generator—the disconnection point. The tester is connected to the grounding terminal. The gate of one of the first transistors, and the first circuit breaker is isolated from the start circuit and the power-on reset signal. 1237943 In another embodiment, for example, in the signal source circuit When the input input voltage exceeds the disconnect point voltage of the signal source circuit, the voltage detector of the signal source circuit generates a trailing portion of the power-on reset signal. ^ Certain embodiments include a feedback crystal. Feedback power The crystal has a first current-carrying terminal connected to the voltage supply source, a second current-carrying terminal of the voltage detector connected to the signal source circuit, and an output connected to the signal source circuit: ―, gate After the signal source circuit generates the trailing portion of the power-on reset signal, the feedback circuit isolates the voltage supply source and the signal source circuit, thereby saving power after both leading and trailing portions are generated before the power-on reset signal has been generated. Therefore, In order to generate the trailing portion of the power-on reset signal, the voltage supply source is isolated from the signal source circuit that generates the trailing portion of the power-on reset signal. In various embodiments, a voltage rise of one of the voltage supply sources causes a Or multiple different responses. Under this kind of response, the voltage at the input of the signal source circuit is set to be lower than the disconnection point of the signal source circuit, for example, by connecting the input of the signal source circuit to the ground terminal. Voltage. In another response, the signal source circuit generates a signal that matches the leading part of the power-on reset signal—this consistency is related before the signal source circuit generates the trailing part of the power-on reset signal. Before the voltage supply continues to rise, the signal source circuit has not yet generated power to reset the trailing part of number k. Therefore Before the voltage supply continues to rise: before 'If the signal source circuit generates a signal that is equal to the leading part before the power-on reset signal, the output of the signal source circuit does not need to be isolated from the power-on reset signal. In the embodiment, after the voltage of the voltage supply source rises, the continuous voltage rise of the voltage supply source causes a response, for example, by consuming the input of the inverter to the voltage supply source, the One input one voltage is raised to the voltage at the disconnection point of the signal source circuit. 1237943 In one embodiment of the present invention, a power on reset is provided, and the method of generating ~ power on reset signal It has — ϋ points. Mm wide rules — part and a trailing part are in response to a voltage rise of a voltage supply source, the voltage of this node is initialized, and the power is turned on and reset. Even if it ’s partial, there is a guide to setting it up. Part of the system is to determine the output voltage of the output nodes. -Signal source: The input voltage of the circuit is set by having a non-intermediate value: at least one first transistor which is adjusted by the ion implantation method. In response to the continuous rise of one of the voltage supply sources, the input voltage of the signal source circuit is increased to exceed that of the signal source circuit. The trailing part of the power-on reset signal is generated from the signal source. In the embodiment, the steps of generating the leading part of the power-on reset signal include multiple steps. — The inverting 11 output is a voltage connected to the voltage supply source, so that the output voltage of the inverter is output to the voltage of the power supply. The voltage supply source is connected via the inverter S to the gate connected to the ground terminal, and the crystal is turned on. —Second Phase Inverter—The input is connected to the ground terminal via a transistor connected to the ground terminal so that the voltage at the input of the second inverter is lower than the disconnection point of the inverter. In her example, the input voltage of the hbl source is via at least a second transistor having a non-zero threshold voltage adjusted by the ion implantation method. The first and second transistor systems are connected to different voltages, such as a voltage supply source and a ground terminal. Circuit elements such as transistors and resistors connect the first and second transistors to different voltages, thereby allowing two different voltages to be coupled to the input voltage of the signal source at the same time. In the Fang and Bei examples, the k source generates a signal that matches the leading part of the power-on reset signal. Before the voltage source continues to rise, the signal source has not yet generated a trailing portion of the power-on reset signal. Therefore, before the success of the voltage supply source rises, if the signal source generates a #f which is in accordance with the f part before the power-on reset signal, the output of the signal source does not need to be isolated from the power-on reset signal. 1237943 Another embodiment of the power-on reset after cutting is a benefit in that the power consumption of the circuit that generates the power-on reset signal is negligible. [Embodiment] Two? Display 7 A circuit diagram of a power-on reset circuit. Power-on heavy-weight power generation, dagger 3 mesh generation—the leading part of the starting circuit of the power-on reset signal 'and a signal source circuit that generates a thunder six pq private | trailing part of the power-on reset signal. The starter circuit includes N-type thunderbolt 11n Μ 孓 日 110, 122, and 124; ρ-type transistor lw
” 、及反相$ 116°^號源電路包含N型電晶體132、134、 136、138與144;以及p型電晶體142、146與⑷。 起動電路係連接如下。電晶體π〇具有一個連接至節點 112之閘極，以及連接至接地端1()8之兩個載電流端子。電晶 體114、122與120各具有連接至節點112之一個載電流 以及連接至電壓供應源105之另一個載電流端子。電晶體m 之閘極與電晶體丨14之閘極係連接至節點卜丨2。電晶體1之 閘極係連接至節點丨18。反相器116具有一個 j % 之輸入，以及一個連接至節點118之輸出。反相器^作^一 種電壓偵測器，其因應於電壓供應源之一電壓上升而產生電力 開啟重置信號之前導部分。電晶體丨24具有一個連接至接:端 丨〇8之載電流端子，另一個連接至節點126之載電流端子，以 及之一個連接至節點11 8之閘極。 反相器1 52具有連接至節點1 50之一輸入與連接至節點 1 26之一輸出。反相器1 28具有連接至節點126之一輸入以及 產生電力開啟重置信號1 30之一輸出。反相器128之輸出係連 接至電力開啟重置電路之輸出郎點。因為節點12 6之電壓決定 電力開啟重置信號之數值，所以節點126係為決定輸出節點之 10 1237943 輪出電壓之節點。雷Λ ， 置"2 "… 號130係為產生電力開啟重 置l唬之尾奴邛勿之信號源電路之一輸入。 信號源電路係連接如下。電晶體132具有一 開啟重置信號130之閘極，—伽、έ ^ ® , 们連接至接地端I〇8之載電流端 子’：曰-二固連接至電晶體丨34之-載電流端子之載電流端 二。電曰曰肢m、丨物38具有一個連接至電壓供應源丨〇5之 ㈣連接在節點丨40與電晶體132之一載電流端子 間之載電〜端子。電晶體丨42具有一個連接至節點⑽之閘 -個連接至節點14G之載電流端子，以及另—個連接至電 錢應源H)5之載電流端子。作為電力開啟信號之尾隨部分之 1壓偵測ϋ之電晶體144肖146之反相器’係具有—個連接 至節點140之輸入以及一個連接至節點15〇之輸出。電晶體⑷ 之其中-個載電流端子係連接至接地端1〇8。電晶體146之其 中-個載電流端子係連接至電晶體148之一载電流端子。電晶 體148具有-個連接至節，點126之閘極，一個連接至電晶體⑽ 之—載電流端子之載電流端子，以及另一個連接至電壓供應源 丨〇5之載電流端子。 ^ 第2圖顯示一種產生一電力㈤啟冑置信號之前導與尾隨部 分之處理流程。在205,電壓供應源105之電壓從接地電壓上° 升。此種電壓上升導致電力開啟重置信號13〇之前導部分:產 生，如下所示。在210,產生電力開啟重置信號之前導部分之 起動電路之一電容器係從電壓供應源丨〇5被充電。於此例1 中，電容器係為一種接有電容器之電晶體，例如電晶體丨。 充電電容器之電壓決定節點112之電壓，其亦決定反相器ιΐ6 =輸入電壓。首先，充電電容器之電壓係滴到足以能低^反相 器丨丨6之斷開點。在節點1丨8之反相器丨丨6之輪出電壓因而是 1237943 高的，並跟隨上升電壓供應源1〇5之後。因此，在2〗5，電壓 供應源105係經由反相器116而連接至電晶體124之閘極。當 私壓供應源105上升超過電晶體丨24之閾值電壓時，電晶體I% 導通並將接地端1〇8連接至節點126，其係為反相器128之輸 入因此在220 ’電晶體1 24之閘極係連接至接地端丨〇8。然後 在225，反相器128之輸入係經由電晶體】24而連接至接地端 ⑽。因為反相器丨28之輸出係為電力開啟重置信號，將反相器 128之輸入耦接至接地端1〇8可將決定輸出節點之輸出電壓之 電路之節點予以初始化。因此，反相器128之輸出係連接至電 壓供應源105。在230,電力開啟重置信號13〇之前導部分出現 於電力開啟重置電路之輸出節點。 、電力開啟重置信號130係由電晶體132之間極所接收，並 導通電晶體132。串聯連接的電晶體134、136與丨38作為雨阻 節點M0係經由電晶體】32、i 34、i 36與i 38、而連接至接私地端 ⑽。節點14〇係連接至電晶體144與146之閘極。電晶體⑷ 與丨46係作為一種供電力開啟重置信號之尾隨部分用之電壓偵 測器，並連接至接地端丨08。因此，在235，電力開啟重置信號 之尾隨部分之信號源電路之輸入係連接至接地端丨〇8。在240 = ^此時點在節點140之電壓係低於電力開啟重置信號之尾隨部 分之信號源電路之斷開點電壓。因為於此時點在節點丨仞之電 壓係低於此種斷開點電壓，所以，經由電晶體丨48，節點】％ 之電壓跟隨在電壓供應源|〇5之後，而電晶體148係藉由節點 丨一26之低電壓（連接至接地端ι〇8)而導通。反相器〖η取節點丨5〇 商電壓作為輸人，並傳送接地端iQ8之電壓作為輸出。因此， 反相器丨52之輪出係與來自電晶體丨24之信號相符，並與 開啟重置信號之前導部分相符。 一私 1237943 ^250，電壓供應源丨〇5之電壓繼續上升。在％，節點 Η2之|壓在接有電容器之電晶體⑽繼續充電時繼續上升。 在60 gp ,點i 12之電壓超過反相器】} 6之斷開點。在節點1 1 8 之反相器U6之輸出電壓在連接至接地端1〇8之後降下至低 值°這使電晶體！24之閘極之電壓低於電晶體124之閾 並斷開電晶體丨24。因此，在265，產生電力開啟重置信號之前 導部分之電路係與電力開啟重置信號丨30隔絕開來。 當電壓供應源105之電壓繼續上升時，電晶體142導通， 而卽點M0變成經由電晶體142而連接至電壓供應源1〇5。節 ，.占140係連接至电晶體144與146之間極。電晶體144與 6、作為ί、电力開啟重置仏破之尾隨部分用之一電麼偵測器，並 連接^接地端⑽。因此，在27()，電力開啟重置信號之尾隨部 分之信號源電路之輸入係連接至電壓供應源丨〇5。當電壓供應 源105之電壓充分上升時，在275，供電力開啟重置信號之尾 隨部分用之信號源電路之輸入電壓係被提高至超過信號源電路 之斷開點。在節點150之信號源之輸出電壓係耦合至接地端丨〇8 並降低。反相H 152接收於節點15〇之低電壓作為輸入，並傳 达之電壓供應源105之高電壓作為輸出至節點丨％。反相器128 接收於節點m之高電壓作為輸入，並傳送接地端1〇8之°低電 ㈣為輸出^種從反相n 128輸出之低電壓係為電力開啟重 置m之尾隨部分Q因此’在28〇’電力開啟重置信號之尾隨 部分出現於電力開啟重置電路之輸出節點。 第3圖顯不依據本發明之-實施例之一種積體電路之簡化 方塊圖。積體電路350包含一記憶體陣列3〇〇，其係藉由使用 局部化電荷陷牌記憶體單元而於一個半導體基板上實現。電源 電壓308與電力開啟重置電路340提供電源至積體電路35〇。 13 1237943 300之列而配置的複 一列解碼器30 1係連接至沿著記憶體陣列 數個字元線302。一行解碼器3〇3係連接至沿著記憶體陣列3〇〇 之仃而配置之複數個位元線3〇4。位址係提供於匯流排3〇5至 了％碼态303與列解碼器3〇1。在方塊3〇6中之感測放大器與 資料輸入結構係經由資料匯流排3〇7而連接至行解碼器3〇3。", And the inverse $ 116 ° ^ source circuit includes N-type transistors 132, 134, 136, 138, and 144; and p-type transistors 142, 146, and ⑷. The starting circuit is connected as follows. The transistor π has one Gate connected to node 112, and two current-carrying terminals connected to ground terminal 1 () 8. Transistors 114, 122, and 120 each have one current-carrying node connected to node 112 and another to voltage supply source 105. A current-carrying terminal. The gate of transistor m and the gate of transistor 14 are connected to node 2. The gate of transistor 1 is connected to node 18. Inverter 116 has a j% input And an output connected to node 118. The inverter is used as a voltage detector which generates a leading part of the power-on reset signal in response to a voltage rise from one of the voltage supply sources. The transistor 24 has a connection To the connection: the current-carrying terminal of terminal 丨 08, the other current-carrying terminal connected to node 126, and one connected to the gate of node 118. Inverter 1 52 has an input connected to node 1 50 and Connect to one of the outputs of nodes 1 to 26. Inverted 1 28 has one input connected to node 126 and one output generating power on reset signal 1 30. The output of inverter 128 is connected to the output point of the power on reset circuit. Because the voltage of node 12 6 determines the power The value of the reset signal is on, so node 126 is the node that determines the output voltage of the 10 1237943 rounds of the output node. Lei Λ, set " 2 " ... No. 130 is the tail slave for generating power to reset Input of one of the signal source circuits. The signal source circuit is connected as follows. Transistor 132 has a gate to turn on the reset signal 130, which is connected to the current-carrying terminal of ground terminal 108: The -2 solid is connected to the transistor-34-the current-carrying terminal of the current-carrying terminal 2. The electrical conductor m, 38 has a connection to a voltage supply source, and the 5 is connected to the node 40 and the transistor. One of the current carrying terminals between the current carrying terminals of 132 ~ terminals. The transistor 42 has a gate connected to the node-, a current carrying terminal connected to the node 14G, and another one which is connected to the power source of the battery. Carrying current terminal. Turn on as power The trailing part of the signal is 1-voltage detection. The transistor 144 and 146 inverters have an input connected to node 140 and an output connected to node 150. Among them, one of the transistor currents The terminal is connected to the ground terminal 108. One of the current-carrying terminals of the transistor 146 is connected to one of the current-carrying terminals of the transistor 148. The transistor 148 has a gate connected to the node, point 126, and one connection. To the transistor ⑽-the current-carrying terminal of the current-carrying terminal, and another current-carrying terminal connected to the voltage supply source 05. ^ Figure 2 shows a processing flow of the leading and trailing parts of generating a power start setting signal. At 205, the voltage of the voltage supply source 105 rises from the ground voltage. This voltage rise causes the leading part of the power-on reset signal 13 to be generated, as shown below. At 210, one of the capacitors of the starting circuit before the power-on reset signal is generated is charged from the voltage supply source 05. In this example 1, the capacitor is a transistor connected to a capacitor, such as a transistor. The voltage of the charging capacitor determines the voltage of node 112, which also determines the inverter ιΐ6 = input voltage. First, the voltage of the charging capacitor is dropped to a point that is low enough to turn off the inverter. The output voltage of the inverter 丨 6 at node 1 丨 8 is therefore 1237943 high, and follows the rising voltage supply source 105. Therefore, at 2 5, the voltage supply source 105 is connected to the gate of the transistor 124 via the inverter 116. When the private voltage supply source 105 rises above the threshold voltage of the transistor 24, the transistor 1% is turned on and the ground terminal 108 is connected to the node 126, which is the input of the inverter 128 and therefore at 220 'transistor 1 The gate of 24 is connected to the ground terminal 08. Then at 225, the input of inverter 128 is connected to ground terminal 经由 via transistor 24. Because the output of the inverter 28 is a power-on reset signal, coupling the input of the inverter 128 to the ground terminal 108 can initialize the nodes of the circuit that determines the output voltage of the output node. Therefore, the output of the inverter 128 is connected to the voltage supply source 105. At 230, the leading part of the power-on reset signal 13 appears at the output node of the power-on reset circuit. The power-on reset signal 130 is received by the transistor 132 and turns on the crystal 132. The transistors 134, 136, and 38 connected in series as rain resistance nodes M0 are connected to the private ground terminal 电 through transistors] 32, i 34, i 36, and i 38. Node 14 is connected to the gates of transistors 144 and 146. Transistors ⑷ and 46 are voltage detectors used as a trailing part of the power-on reset signal, and are connected to the ground terminal 08. Therefore, at 235, the input of the signal source circuit of the trailing part of the power-on reset signal is connected to the ground terminal 08. At 240 = ^ at this time, the voltage at the node 140 is lower than the voltage of the source circuit of the trailing portion of the power-on reset signal. Because the voltage at the node at this time is lower than the voltage at this disconnection point, via the transistor 48, the voltage of the node]% follows the voltage supply source | 05, and the transistor 148 is The low voltage (connected to the ground terminal 8) of node 26 is turned on. The inverter [η] takes the node quotient and 50 quotient voltage as the input, and transmits the voltage of the ground terminal iQ8 as the output. Therefore, the output of the inverter 52 corresponds to the signal from the transistor 24, and it corresponds to the leading part before the reset signal is turned on. A private 1237943 ^ 250, the voltage of the voltage supply source 05 continues to rise. At%, the node Η2 of || continues to rise as the capacitor ⑽ connected to the capacitor continues to charge. At 60 gp, the voltage at point i 12 exceeds the inverter]} 6 cut-off point. The output voltage of the inverter U6 at the node 1 1 8 drops to a low value after being connected to the ground terminal 108. This makes the transistor! The voltage of the gate of 24 is lower than the threshold of the transistor 124 and the transistor 24 is turned off. Therefore, at 265, the circuit of the leading part for generating the power-on reset signal is isolated from the power-on reset signal. When the voltage of the voltage supply source 105 continues to rise, the transistor 142 is turned on, and the point M0 becomes connected to the voltage supply source 105 through the transistor 142. Section, accounted for 140 series connected to the transistor between 144 and 146. Transistors 144 and 6. As one of the detectors used for the power-on reset reset follow-up, use an electrical detector and connect it to the ground terminal. Therefore, at 27 (), the input of the signal source circuit of the trailing portion of the power-on reset signal is connected to the voltage supply source 05. When the voltage of the voltage supply source 105 rises sufficiently, at 275, the input voltage of the signal source circuit used by the trailing portion of the power-on reset signal is increased to exceed the disconnection point of the signal source circuit. The output voltage of the signal source at node 150 is coupled to ground and reduced. The inverting H 152 receives the low voltage of the node 15 as an input, and the high voltage of the passed voltage supply source 105 as an output to the node ％. The inverter 128 receives the high voltage at the node m as an input and transmits the low voltage of the ground terminal 108 ° as an output. The low voltage output from the inverting n 128 is the power on and resets the trailing part of m Therefore, the trailing part of the "on 28" power-on reset signal appears at the output node of the power-on reset circuit. Fig. 3 shows a simplified block diagram of an integrated circuit which is not according to an embodiment of the present invention. The integrated circuit 350 includes a memory array 300, which is implemented on a semiconductor substrate by using localized charge trapping memory cells. The power supply voltage 308 and the power-on reset circuit 340 provide power to the integrated circuit 350. A plurality of decoders 30 1 arranged in a row of 13 1237943 300 are connected to a plurality of word lines 302 along the memory array. A row of decoders 303 is connected to a plurality of bit lines 304 arranged along the memory array 300. The address is provided in the bus 305 to% code state 303 and the column decoder 301. The sense amplifier and data input structure in block 306 are connected to the row decoder 303 via a data bus 307.
資料係經由資料輸入線3H，從積體電路350上之輸入/輸出 蜂，或從積體電路350内部或外部之其他資料源而提供至方塊 3〇6中之資料輸人結構。資料係經由資料輸出線312，而從方塊 306中之感測放大器提供至積體電路35〇上之輸人增出璋，或 提供至積體電路350之内部或外部之其他資料目標。 塚上所迷 平乂1 土貝％例揭露如上，狄 =用以限定本發明，任何熟習此技藝者，在不脫離本發明： ^神和範圍内’當可作各種之更動與潤飾，因此样明之^ 祀圍當視後附之申請專利範圍所界定者為準。 X ’The data is provided to the data input structure in block 306 via the data input line 3H from the input / output bee on the integrated circuit 350, or from other data sources inside or outside the integrated circuit 350. The data is provided via the data output line 312 from the sense amplifier in block 306 to the input and output on the integrated circuit 350, or to other data targets inside or outside the integrated circuit 350. Takakami Mizuchi 1 The example of soil shells is disclosed as above, Di = is used to limit the present invention, and any person skilled in this art will not depart from the present invention: ^ Within the scope of God and various modifications and retouching, so Like Mingzhi ^ Siewei shall be determined by the scope of the attached patent application. X ’
14 1237943 【圖式簡單說明】 弟丨圖頒示一種電力開啟重置電路之電路圖 第2圖顯示一種產生一電力開啟重置信號之前導與尾隨部 分之處理流程。 第3圖顯示一種具有電力開啟重置電路之積體電路。 【主要元件符號說明】14 1237943 [Brief description of the diagram] Figure 丨 shows the circuit diagram of a power-on reset circuit. Figure 2 shows a processing flow of the leading and trailing parts before generating a power-on reset signal. FIG. 3 shows an integrated circuit having a power-on reset circuit. [Description of main component symbols]
105 :電壓供應源 108 :接地端 1 10、114、120、122、124、132、134、136、138、142、 144、 U6、148 :電晶體 112、118、126、140、150 :節點 116、128、152 :反相器 130 :電力開啟重置信號 205〜280 :流程步驟105: voltage supply source 108: ground terminal 1 10, 114, 120, 122, 124, 132, 134, 136, 138, 142, 144, U6, 148: transistors 112, 118, 126, 140, 150: node 116 , 128, 152: Inverter 130: Power on reset signal 205 ~ 280: Process steps
300 ： 記憶體陣列 301 ： 列解碼器 302 ： 子元線 303 ： 行解碼器 304 ： 位元線 305 ： 匯流排 306 : 方塊 307 ： 資料匯流排 308 ： 電源電壓 311 : 資料輸入線 15 1237943 3 1 2 :資料輸出線 340 :電力開啟重置電路 350 :積體電路300: memory array 301: column decoder 302: sub-line 303: row decoder 304: bit line 305: bus 306: block 307: data bus 308: power supply voltage 311: data input line 15 1237943 3 1 2: Data output line 340: Power on reset circuit 350: Integrated circuit